WO2013189139A1 - 非晶硅平板x射线传感器的制作方法 - Google Patents

非晶硅平板x射线传感器的制作方法 Download PDF

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Publication number
WO2013189139A1
WO2013189139A1 PCT/CN2012/083711 CN2012083711W WO2013189139A1 WO 2013189139 A1 WO2013189139 A1 WO 2013189139A1 CN 2012083711 W CN2012083711 W CN 2012083711W WO 2013189139 A1 WO2013189139 A1 WO 2013189139A1
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Prior art keywords
amorphous silicon
film
photoresist
layer film
layer
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PCT/CN2012/083711
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English (en)
French (fr)
Inventor
徐少颖
谢振宇
郭建
陈旭
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北京京东方光电科技有限公司
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Priority to US13/995,424 priority Critical patent/US9773938B2/en
Publication of WO2013189139A1 publication Critical patent/WO2013189139A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14692—Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type
    • H01L31/1055—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type the devices comprising amorphous materials of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • Embodiments of the present invention relate to a method of fabricating an amorphous silicon flat panel X-ray sensor. Background technique
  • Thin film transistor (TFT) flat panel X-ray sensor is a vital component in digital imaging technology and is used in X-ray chest X-ray, CT (computed tomography) and other fields.
  • FIG. 1 shows a circuit configuration diagram of an amorphous silicon TFT panel X-ray sensor.
  • a flat panel X-ray sensor includes a matrix of a plurality of pixel units. Each pixel unit includes a photodiode 15 and a field effect transistor 14. Each FET 14 is connected to its adjacent one of the gate scan lines 12, and each photodiode 15 is connected to its adjacent one of the data lines 11 via a FET 14 in the pixel unit.
  • a gate of each FET 14 in each row of pixel cells is connected to a gate scan line 12 of the row, and a source is respectively connected to a corresponding one of the data lines 11, and a drain It is connected to the negative electrode of the photodiode 15.
  • the anode of the photodiode 15 is connected to the bias line 13.
  • Each of the gate scan lines is connected to the gate control unit, and each of the data lines 11 is connected to the source control unit.
  • amorphous silicon flat panel X-ray sensors typically require 10 mask process (lithographic process) to prepare.
  • the use of a multi-pass mask process makes the entire manufacturing process not only costly and complex, but also results in a decrease in yield and a reduction in equipment throughput due to the number of processes. Summary of the invention
  • Embodiments of the present invention provide a method for fabricating an amorphous silicon flat panel X-ray sensor, which can reduce the number of use of the mask when the flat panel X-ray sensor is produced, simplify the production process, and improve the yield.
  • One aspect of the present invention provides a method of fabricating an amorphous silicon flat panel X-ray sensor, comprising: forming a pattern including a gate electrode and a gate scan line on a substrate; on a substrate on which a gate line and a gate scan line are formed A data line, a TFT switching element, and a light sensing element are formed; a passivation layer and a bias line are formed on the substrate on which the data line, the TFT switching element, and the light sensing element are formed.
  • a method of forming a data line, a TFT switching element, and a light sensing element on a substrate on which a gate line and a gate scan line are formed includes: forming a data line, a TFT switching element, and a light sensing by a mask process An element, wherein a mask corresponding to a channel of the TFT switching element is semi-transmissive on the mask in the mask process, for obtaining a photoresist partial retention region, and the data line and the light sensing
  • the corresponding region of the component and the TFT switching element except the channel is opaque, and is used to obtain a photoresist completely reserved region, except for a region corresponding to the channel of the TFT switching element, a region corresponding to the data line, and light.
  • the area other than the area corresponding to the sensing element is completely transparent, and is used to obtain a completely removed area of the photoresist.
  • the forming a data line, the TFT switching element, and the light sensing element by one mask process includes: sequentially forming a gate insulating film on the substrate on which the gate electrode and the gate scan line are formed , active layer film, ohmic contact layer film, data line and source/drain metal layer film, amorphous silicon layer film, transparent electrode layer film, photoresist layer film; using the mask in the mask process
  • the photoresist layer is exposed and developed to obtain a photoresist pattern, including the photoresist completely removed region, the photoresist portion remaining region, and the photoresist completely reserved region; a transparent electrode layer film, an amorphous silicon layer film, a data line and a source/drain metal layer film, an ohmic contact layer film, and an active layer film in the removal region are removed by etching; and then the photoresist portion is reserved in the region
  • the photoresist is removed, the channel is exposed, and the transparent electrode layer film, the amorphous
  • a transparent electrode layer film, an amorphous silicon layer film, a data line, and a source/drain metal layer film in the exposed region are etched to form a TFT in the photoresist portion remaining region.
  • the method further comprises: etching and removing the data line of the TFT switching element and the amorphous silicon layer film on the source/drain metal layer.
  • the amorphous silicon layer includes an n-type amorphous silicon layer, an intrinsic amorphous silicon layer, and a p-type amorphous silicon layer which are sequentially laminated.
  • the gate and gate scan lines are molybdenum, aluminum, tungsten, titanium, copper or an alloy of any two of the foregoing metals, and are a single layer film or a multilayer film; for example, The gate and gate scan lines have a thickness of from 100 nm to 500 nm.
  • the gate insulating layer film is silicon nitride or silicon oxide, wherein The gate insulating layer film has a thickness of 250 nm to 600 nm;
  • the active layer film is n-type amorphous silicon, and the active layer film has a thickness of 30 nm to 300 nm.
  • the ohmic contact layer film has a thickness of 30 nm to 100 nm.
  • the thickness of the n-type amorphous silicon thin film layer in the amorphous silicon thin film is 30 nm to 100 nm, and the thickness of the intrinsic amorphous silicon thin film layer is 100 nm to 2000 nm.
  • the forming a passivation layer on the substrate on which the TFT switching element and the light sensing element are formed and the bias line include: passing a mask process on the substrate on which the TFT switching element and the light sensing element are formed A passivation layer is formed, wherein the mask of the mask process used is opaque except for the area of the light sensing element and the via area; a bias line is formed on the passivation layer.
  • the passivation layer film in the switching element is a non-photosensitive resin, silicon nitride or silicon oxide; for example, the passivation layer film has a thickness of 150 nm to 2500 nm.
  • the bias line layer film is indium tin oxide ITO or indium tin oxide IZO; for example, the bias line film has a thickness of 30 nm to 120 nm.
  • Embodiments of the present invention provide a method for fabricating an amorphous silicon flat panel X-ray sensor, which may, for example, be an active layer, an ohmic contact layer, a data line and a source/drain metal layer, or a p-type non-defective when preparing an X-ray sensor.
  • the crystalline silicon, intrinsic amorphous silicon, n-type amorphous silicon and transparent electrode layers are exposed to different degrees of exposure using the same mask, which reduces the number of masks used, simplifies the production process, and improves the yield.
  • FIG. 1 is a schematic circuit diagram of an amorphous silicon flat panel X-ray sensor after completion of a process flow according to an embodiment of the present invention
  • FIG. 3 is a top plan view of a pixel unit after a process flow of a specific embodiment of the present invention is completed;
  • FIG. 4A is an AA' of a gate scan line formed in a process flow according to an embodiment of the present invention (FIG. 4A) Schematic diagram of AA' in 3;
  • 4B is a cross-sectional view showing a BB' (BB' in FIG. 3) after a gate scan line is formed in a process flow according to an embodiment of the present invention
  • FIG. 5A is a schematic cross-sectional view of AA' (AA' in FIG. 3) after formation of a gate insulating layer in a process flow according to an embodiment of the present invention
  • 5B is a schematic cross-sectional view of BB' (BB' in FIG. 3) after formation of a gate insulating layer in a process flow according to an embodiment of the present invention
  • 6A is a cross-sectional view showing the AA' (AA' in FIG. 3) after deposition of each layer exposed by a mask in a process flow according to an embodiment of the present invention
  • 6B is a schematic cross-sectional view showing the BB' (BB' in FIG. 3) after deposition of each layer exposed by a mask in a process flow according to an embodiment of the present invention
  • FIG. 7A is a schematic cross-sectional view showing a photoresist AA' (AA' in FIG. 3) after deposition of each layer by a mask exposure process according to an embodiment of the present invention
  • FIG. 7B is a cross-sectional view showing a BB' (FIG. 3 BB') coated with a photoresist after deposition of each layer by a mask exposure process according to an embodiment of the present invention
  • FIG. 8A is a cross-sectional view showing the AA' (AA' in FIG. 3) of each layer exposed by a mask after exposure of a photoresist in a process flow according to an embodiment of the present invention
  • 8B is a cross-sectional view showing a BB' (BB' in FIG. 3) of each layer exposed by a mask after exposure of a photoresist in a process flow according to an embodiment of the present invention
  • FIG. 9A is a cross-sectional view showing the AA' (AA' in FIG. 3) after etching the exposed portions of each layer by a mask exposure process according to an embodiment of the present invention
  • FIG. 9B is a cross-sectional view showing a BB' (BB' in FIG. 3) after etching the exposed portions of each layer exposed by a mask in a process flow according to an embodiment of the present invention
  • FIG. 1 is a schematic cross-sectional view of the AA' (AA' in FIG. 3) after etching the exposed portions of each layer by a mask exposure process according to a specific embodiment of the present invention
  • FIG. 10B is a schematic cross-sectional view showing a BB' (BB' in FIG. 3) after etching the exposed portions of each layer by a mask exposure process according to an embodiment of the present invention
  • FIG. 11A is a schematic cross-sectional view showing the AA' (FIG. 3) after forming a channel of each layer of a mask using a mask according to a specific embodiment of the present invention
  • FIG. 11B is a flow chart showing the layers of each layer using a mask 3 ⁇ 4 light according to a specific embodiment of the present invention.
  • FIG. 12A is a schematic cross-sectional view of AA' (AA' in FIG. 3) after formation of a passivation layer in a process flow according to an embodiment of the present invention
  • FIG. 12B is a schematic cross-sectional view of BB' (BB' in FIG. 3) after formation of a passivation layer in a process flow according to an embodiment of the present invention
  • FIG. 13A is a schematic cross-sectional view of AA' (AA' in FIG. 3) after a bias line is formed in a process flow according to an embodiment of the present invention
  • Figure 13B is a cross-sectional view showing the BB' (BB' in Figure 3) after the formation of the bias line in the process flow of the embodiment of the present invention. detailed description
  • a flat panel X-ray sensor prepared in accordance with an embodiment of the present invention includes a matrix of a plurality of pixel units.
  • Each of the pixel units includes, for example, a photodiode for performing photoelectric conversion to generate photocharges and a thin film transistor (TFT) as a switching element.
  • TFT thin film transistor
  • Each thin film transistor is connected to its adjacent one of the gate scan lines, and each photodiode is connected to its adjacent one of the data lines via a thin film transistor in the pixel unit.
  • a gate of each thin film transistor in each row of pixel cells is connected to a gate scan line of the row, and a source is respectively connected to a corresponding one of the data lines, and the drain and the photoelectric
  • the cathode of the diode is connected.
  • the positive pole of the photodiode is connected to the bias line.
  • Each of the gate scan lines is connected to the gate control unit, and each of the data lines is connected to the source control unit.
  • the process flow of an embodiment of the present invention includes:
  • Step S201 forming a pattern including a gate electrode and a gate scan line on the substrate.
  • Step S202 forming a data line, a TFT switching element, and a light sensing element on the substrate on which the gate electrode and the gate scan line are formed.
  • Step S203 forming a passivation layer and a bias line on the substrate on which the data line, the TFT switching element, and the light sensing element are formed.
  • Each pixel unit includes a data line a, a switching element 1), a light sensing element c, and a gate scan line f.
  • the switching element b has a channel d and a source-drain region e.
  • a cross-sectional view in two directions of BB' illustrates a method of fabricating an amorphous silicon flat panel X-ray sensor according to an embodiment of the present invention, and the manufacturing method includes the following steps.
  • a gate electrode (not shown) and a gate scanning line 2 (shown in Fig. 3, located in the region f) are formed on the substrate.
  • a gate electrode and a gate scan line 2 are formed on the substrate 1 by a patterning process.
  • the mask in the patterning process used transmits light except for the gate electrode and the gate scanning line 2.
  • a film of the gate electrode and the gate scanning line 2 is formed on the entire substrate 1.
  • the substrate described in this embodiment may be a transparent substrate such as a glass substrate or a quartz substrate.
  • the film forming process used may be a process such as deposition, coating, sputtering, or the like.
  • a gate electrode (not shown) and a gate scan line 2 are formed by a patterning process. As shown in Fig. 4B, the BB' region does not retain the film for forming the gate electrode and the gate scan line 2.
  • the patterning process may include a process flow of masking, exposure, development, etching, and the like.
  • the material for forming the film of the gate electrode and the gate scan line may be molybdenum, aluminum, tungsten, titanium, copper
  • the multilayer film may, for example, comprise a first layer of molybdenum, a second layer of aluminum, which together form a thin film for forming a gate electrode and a gate scan line.
  • metals that can be used for the gate electrode and the gate scan line. However, in order to improve the stability and adhesion of the gate scan line, it is possible to select according to the metal characteristics in actual fabrication, or to use a metal alloy.
  • the gate electrode and the gate scan line film have a thickness of, for example, 100 nm to 500 nm. By controlling the thickness of the gate electrode and the gate scan line metal within a certain range, it is possible to avoid an excessive step in the production of the flat panel X-ray sensor.
  • the patterning process may not form a film of each film layer on the substrate first, and then perform a photolithography process, and directly form a pattern of each film layer on the substrate by a process such as printing or network printing.
  • a gate insulating layer, a TFT switching element, a data line, and a light sensing element are formed by a patterning process.
  • the mask used in the patterning process is a gray scale mask (for example, a two-tone or halftone mask), and the area corresponding to the channel of the TFT switching element on the mask is semi-transparent, and the data
  • the area corresponding to the channel in the line, the light sensing element, and the TFT switching element is opaque, except for the area corresponding to the channel of the TFT switching element, the area corresponding to the data line, the area corresponding to the light sensing element, and the trench of the TFT switching element. All areas outside the road are completely transparent.
  • the patterning process includes, for example, sequentially forming a gate insulating film, an active layer film, an ohmic contact film, a data line and a source/drain metal film, and amorphous silicon on a substrate on which a gate electrode and a gate scan line are formed.
  • a thin film, a thin film of a transparent electrode layer, and then a laminate of these films is patterned.
  • a gate insulating film 3 is formed to cover the entire substrate 1, as shown in Figs. 5A and 5B.
  • the film forming process may be a process such as deposition, coating or sputtering.
  • the gate insulating layer may be a film of silicon nitride or silicon oxide. Both silicon nitride and silicon oxide are good insulating films.
  • a layer of photoresist is formed on the substrate on which the transparent electrode layer film is formed. And setting a gray mask to expose the photoresist, the photoresist corresponding to the opaque region of the gray mask is not exposed, and the photoresist is semi-exposed corresponding to the semi-transmissive region of the gray mask And the photoresist corresponding to the all-transmissive region of the gray mask is completely exposed.
  • the half-exposure region of the mask is, for example, a semi-transmissive region, i.e., 50% exposure, and of course, 60% or 70% exposure, and the exposure of the half-exposure region of the mask is selected according to the process requirements.
  • the positive photoresist is still taken as an example for illustration. Developing the exposed photoresist, unexposed area The photoresist of the domain is completely retained, the photoresist portion of the half-exposed region remains, and the photoresist in the fully exposed region is completely removed. Please note that the "resistance of photoresist completely" as used herein only means that the majority of the photoresist is retained, without any loss.
  • the amorphous silicon layer film, the data line and the source/drain metal layer film, the ohmic contact layer film, the active layer film, and the transparent electrode layer film corresponding to the photoresist completely removed region are etched and completely removed.
  • the data lines and source and drain metal layers can be formed by wet or dry etching to remove portions of the stack that are not to be retained.
  • the photoresist of the photoresist partially reserved region ie, the photoresist semi-exposed region
  • the photoresist portion in the region is partially retained; then, the corresponding amorphous silicon layer film, the data line and the source/drain metal layer film in the photoresist portion remaining region are etched to form a TFT switching element channel.
  • the photoresist in the entire remaining area of the photoresist is removed, and the film film corresponding to the completely reserved area of the photoresist is patterned by a patterning process to finally form a data line, a TFT switching element, and a light sensing element.
  • the data lines, the TFT switching elements and the light sensing elements can be formed by one mask process.
  • the amorphous silicon layer includes, from bottom to top, an n-type amorphous silicon layer, an intrinsic amorphous silicon layer, and a p-type amorphous silicon layer, and the stacked layer is used to form a photoelectric conversion structure layer of the photodiode.
  • the film of the transparent electrode layer may be indium tin oxide (ITO), but it is not limited to ITO, and may be other transparent conductive films such as indium tin oxide (IZO) and tin oxide (SnO 2 ).
  • the data line and the source of the TFT switching element are connected to the data line and the source/drain metal layer, and the source and drain of the TFT switching element are turned on through the active layer and the ohmic contact layer at the channel.
  • the drain of the TFT switching element is connected to the light sensing element at the data line layer and the source and drain.
  • a gate insulating layer film 3, an active layer film 4, an ohmic contact layer film 5, a data line and a source/drain metal layer 6, and an n-type amorphous silicon film are sequentially formed on a substrate on which a gate electrode and a gate scan line are formed. 7.
  • a layer of photoresist 11 is formed on the transparent electrode layer film 10 as shown in Figs. 7A and 7B.
  • the photoresist 11 is exposed using a gray tone mask.
  • the channel d of the TFT switching element b The photoresist corresponding to the region is half-exposed, and after the developing process, the portion of the photoresist is partially retained; and the photoresist corresponding to the data line a, the light sensing element c, and the region other than the channel d portion of the TFT switching element b
  • the exposure process is not performed, and after the development process, the portion of the photoresist is completely retained; after the photoresist corresponding to the region other than the above region is subjected to the full exposure and development process, the portion of the photoresist is completely removed.
  • 8A and 8B are schematic views of the formed photoresist after exposure and development.
  • ⁇ using a patterning process to pattern the region corresponding to the completely removed region of the photoresist, that is, etching the exposed layer in the region to form a transparent electrode layer 10', a p-type amorphous silicon layer 9', and an intrinsic non- A crystalline silicon layer 8', an n-type amorphous silicon layer 7', a data line and a source/drain metal layer 6', an ohmic contact layer 5', and an active layer 4'.
  • 9A and 9B are schematic views of the substrate after the patterning process.
  • the photoresist in the remaining portion of the photoresist is ashed to remove the portion of the photoresist, while the photoresist in the fully-retained region of the photoresist is partially retained, as shown in Figs. 10A and 10B. Then, using a patterning process, the area corresponding to the remaining portion of the photoresist is patterned, and the newly exposed layer is etched to form a channel pattern.
  • 11A and 11B are schematic views of a substrate after channel formation.
  • the photoresist in the completely remaining area of the photoresist is removed.
  • the data lines, the TFT switching elements, and the light sensing elements are formed by a patterning process.
  • the source and drain electrodes of the TFT switching element and the amorphous silicon layer on the data line can be etched away. Since the production method deposits the active layer, the ohmic contact layer, the data line and the source/drain metal layer, and the amorphous silicon layer layer by layer, and then uses the gray tone mask to perform photolithography, using only one mask process, The amorphous silicon layer on the data line and the TFT switching element is still present although it is not necessary. The remaining amorphous silicon layer may be etched by a patterning process, or may be left on the data lines or TFT switching elements in order to save process and operation costs.
  • the active layer film is n-type amorphous silicon, but is not limited thereto, and may be, for example, an appropriate material such as an oxide semiconductor. Good conductivity can be achieved by using n-type amorphous silicon as the material of the active layer.
  • the active layer film has a thickness of 30 nm to 300 nm.
  • the ohmic contact layer film has a thickness of 30 nm to 100 nm.
  • the n-type amorphous silicon layer film has a thickness of 30 nm to 100 nm.
  • the p-type amorphous silicon has a thickness of 30 nm to 100 nm.
  • the intrinsic amorphous silicon layer film has a thickness of 100 nm to 2000 nm.
  • each layer of film By controlling the thickness of each layer of film within a certain range, it is possible to ensure that the functions of the layers are effective, and it is also possible to prevent the functions of the respective portions from being affected by the difference in thickness of the film layers in the respective regions.
  • a passivation layer 12 is formed on the substrate on which the above steps are completed.
  • 12A and 12B are schematic views after forming a passivation layer.
  • a passivation film 12 is formed on the entire substrate 1, as shown in Figs. 12A and 12B and in conjunction with Fig. 3; a photoresist (not shown) is formed on the passivation film 12.
  • the photoresist corresponding to the data line region a, the photo sensing element region c, and the via h region in the gate scanning line region f is exposed by a mask.
  • the passivation layer in the region corresponding to the data line region is removed by the patterning process, and the passivation layer film in the region corresponding to the portion of the light sensing element is removed, corresponding to the via hole h in the gate scan line region f
  • the passivation layer film in the area is removed.
  • the transparent electrode layer 10 in the via is exposed.
  • the passivation layer film in the switching element is preferably a resin or silicon nitride.
  • the passivation layer made of silicon nitride can perform good insulation.
  • the passivation layer made of resin can be more easily covered uniformly, and the surface is also more flat. It should be understood by those skilled in the art that any other material having the same function as the resin or silicon nitride can be used. Not limited.
  • the passivation layer film has a thickness of 150 nm to 2500 nm. Controlling the thickness of the passivation film in this interval ensures that the passivation layer can be effectively insulated, and that the thickness is too thick and the gap is too high.
  • a film of a bias line is formed on the substrate on which the above steps are completed, and the bias line is formed by a patterning process.
  • the patterning process includes, for example, mask, exposure, development, etching, etc.; or may not form a film of each film layer on the substrate and then perform photolithography, but directly prints, network prints, etc. directly on the substrate.
  • a pattern of each film layer is formed thereon.
  • 13A and 13B are schematic views showing the formation of the bias line 13.
  • the bias line is used to form a bias voltage.
  • the bias lines of the various sensors in the sensor array need to be connected to each other and to the periphery.
  • the bias line may be formed into a comb shape, or may be formed into a block shape (in which two block-shaped bias wires are connected to each other), or a large area coverage of the entire sensor array region.
  • the bias line will be in contact with the transparent electrode layer film 10 through the via h as shown in FIG. 13A. Connected.
  • the bias line near the pin area of the lead around the sensor must be etched away to avoid
  • the etching of the bias line near the pin area of the peripheral lead of the sensor may be performed in a process of masking, exposing, developing, etching, etc. forming the bias line, or may be separately removed by etching.
  • the bias line film may be a conductive transparent film such as ITO (Indium Tin Oxide) or IZO (Indium Tin Oxide).
  • the deposition mode of ITO is preferably a normal temperature amorphous mode; the high temperature polycrystalline mode deposition hardens and densifies the photoresist on the substrate.
  • the amorphous ITO is finally converted into a polycrystalline ITO with better conductivity and transparency through an annealing process.
  • the annealing process refers to the process of heating the ITO to a certain critical point temperature and cooling it for a certain period of time.
  • the bias line film has a thickness of 30 nm to 120 nm. Controlling the thickness of the bias line film in this interval allows both the bias line to be electrically conductive and the bias to be too high due to the thickness of the bias line being too thick.
  • amorphous silicon flat panel X-ray sensor manufactured by the manufacturing method of the present invention is shown in Figs. 3, 13A and 13B.
  • the amorphous silicon flat panel X-ray sensor includes a data line, a TFT switching element 1), a light sensing element c, and a gate scanning line f.
  • the TFT switching element includes: a gate electrode, an active layer, an ohmic contact layer, a source, and a drain.
  • the manufacturing method corresponding to the embodiment of the present invention forms the active layer, the ohmic contact layer, the data line and the source/drain metal layer, the amorphous silicon layer and the transparent electrode layer, layer by layer, and then light is performed by using a gray tone mask. Engraving, etching and patterning are performed using only one mask process. The amorphous silicon layer on the data line and the TFT switching element is still unnecessary, but the patterned amorphous silicon layer may be etched by a patterning process, or it may be saved in order to save process and operation costs. Continue to stay on the data line, TFT switching components.
  • the amorphous silicon layer includes a stack of an n-type amorphous silicon layer, an intrinsic amorphous silicon layer, and a p-type amorphous silicon layer.
  • the embodiment of the present invention only needs to use a mask process, and uses a gray tone mask to perform full exposure, half exposure and no exposure on the photoresist covered by different parts. deal with.
  • the data line, the TFT switching element, and the light sensing element can be formed by using only one mask exposure, which not only simplifies the production process but also saves production costs, and also improves the yield of the product.
  • the spirit and scope of the invention is intended to be included within the scope of the invention.

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Abstract

本发明的实施例提供一种非晶硅平板X射线传感器的制作方法，减少了掩膜板使用的次数，简化了生产工序还节约了生产成本，同时还能提高产品的良品率。该制作方法包括：在基板上形成栅极扫描线后，通过一次构图工艺形成数据线，TFT开关元件和光感应元件，其中，所述构图工艺中的掩膜板上与所述TFT开关元件的沟道对应的区域部分透光，与所述数据线、光感应元件，以及 TFT开关元件中除沟道分别对应的区域不透光；在形成了TFT 开关元件和光感应元件的基板上形成钝化层以及偏压线。

Description

非晶硅平板 X射线传感器的制作方法 技术领域
本发明的实施例涉及一种非晶硅平板 X射线传感器的制作方法。 背景技术
薄膜晶体管 （TFT )平板 X射线传感器是数字影像技术中至关重要的元 件， 应用于 X光胸透、 CT (计算机断层扫描）等领域中。
图 1示出了非晶硅 TFT平板 X射线传感器的电路结构图所示。 平板 X 射线传感器包括由多个像素单元组成的矩阵。 每个像素单元包括一个光电二 极管 15和一个场效应管 14。每个场效应管 14与其相邻的一条栅极扫描线 12 相连， 而每个光电二极管 15经由该像素单元内的场效应管 14与其相邻的一 条数据线 11相连。在多个像素单元组成的矩阵中，每一行像素单元中的各个 场效应管 14的栅极与该行的一条栅极扫描线 12相连， 源极分别与相应的一 条数据线 11相连，漏极与光电二极管 15的负极相连。光电二极管 15的正极 和偏压线 13相连。 各条栅极扫描线与栅极控制单元相连， 各条数据线 11与 源极控制单元相连。
在现有技术中 ,非晶硅平板 X射线传感器通常需要 10道掩模板工艺 (光 刻工艺）来制备。 使用多道掩模板工艺， 使得整个制备过程不仅成本高、 复 杂， 且因为工序多还会造成良品率下降， 设备产能下降。 发明内容
本发明的实施例提供了一种非晶硅平板 X射线传感器的制作方法，可以 在平板 X射线传感器生产时能够减少掩模板的使用数量， 简化生产工序， 提 高良品率。
本发明的一个方面提供了一种非晶硅平板 X射线传感器的制作方法， 包 括： 在基板上形成包括栅电极和栅极扫描线的图形； 在形成栅极线和栅极扫 描线的基板上形成数据线、 TFT开关元件和光感应元件； 在形成了数据线、 TFT开关元件和光感应元件的基板上形成钝化层以及偏压线。 在该制作方法之中， 例如， 在形成栅极线和栅极扫描线的基板上形成数 据线、 TFT开关元件和光感应元件的方法包括： 通过一次掩膜工艺形成数据 线、 TFT开关元件和光感应元件， 其中， 所述掩膜工艺中的掩膜板上， 与所 述 TFT开关元件的沟道对应的区域半透光， 用于得到光刻胶部分保留区域， 与所述数据线、光感应元件以及 TFT开关元件中除沟道以外的部分分别对应 的区域不透光， 用于得到光刻胶完全保留区域， 除了所述 TFT开关元件的沟 道对应的区域、 数据线对应的区域、 光感应元件对应的区域以外的其他区域 全透光， 用于得到光刻胶完全去除区域。
在该制作方法之中， 例如， 所述通过一次掩膜工艺形成数据线、 TFT开 关元件和光感应元件包括： 在形成了所述栅电极和栅极扫描线的基板上依次 形成栅极绝缘层薄膜， 有源层薄膜， 欧姆接触层薄膜、 数据线与源漏极金属 层薄膜、 非晶硅层薄膜、 透明电极层薄膜、 光刻胶层薄膜； 利用所述掩膜工 艺中的掩模板对所述光刻胶层进行曝光并显影得到光刻胶图案， 包括所述光 刻胶完全去除区域、 所述光刻胶部分保留区域和所述光刻胶完全保留区域； 将所述光刻胶完全去除区域中的透明电极层薄膜、 非晶硅层薄膜、 数据线与 源漏极金属层薄膜、 欧姆接触层薄膜、 有源层薄膜刻蚀去除； 然后， 将所述 光刻胶部分保留区域中的光刻胶去除， 暴露出所述沟道， 将暴露后的区域中 的透明电极层薄膜、 非晶硅层薄膜、 源漏极金属层薄膜刻蚀形成 TFT开关元 件沟道； 然后，去除所述光刻胶完全保留区域中的光刻胶，暴露数据线、 TFT 开关元件和光感应元件。
在该制作方法之中， 例如， 在所述光刻胶部分保留区域中将暴露后的区 域中的透明电极层薄膜、 非晶硅层薄膜、 数据线与源漏极金属层薄膜刻蚀形 成 TFT开关元件沟道后， 该方法进一步包括： 将 TFT开关元件的数据线与 源漏极金属层上的非晶硅层薄膜刻蚀去除。
在该制作方法之中，例如，所述非晶硅层包括依次层叠的 n型非晶硅层、 本征非晶娃层、 p型非晶娃层。
在该制作方法之中， 例如， 所述栅极和栅极扫描线为钼、 铝、 钨、 钛、 铜或者前述金属任意两种的合金， 为单层膜或多层膜； 例如， 所述栅极和栅 极扫描线厚度为 lOOnm ~ 500nm。
在该制作方法之中， 例如， 所述栅绝缘层薄膜为氮化硅或氧化硅， 其中， 所述栅绝缘层薄膜的厚度为 250nm ~ 600nm;
在该制作方法之中， 例如， 所述有源层薄膜为 n型非晶硅， 且所述有源 层薄膜厚度为 30nm ~ 300nm。
在该制作方法之中， 例如， 所述欧姆接触层薄膜厚度为 30nm ~ 100nm。 在该制作方法之中， 例如， 所述非晶硅薄膜中的 n型非晶硅薄膜层厚度 为 30nm ~ lOOnm, 所述本征非晶硅薄膜层厚度为 100nm ~ 2000nm。
在该制作方法之中， 例如， 所述在形成了 TFT开关元件和光感应元件的 基板上形成钝化层以及偏压线包括：在形成了 TFT开关元件和光感应元件的 基板上通过一次掩膜工艺形成钝化层， 其中， 所用掩膜工艺的掩模板在除光 感应元件区域、 过孔区域外不透光； 在钝化层上形成偏压线。
在该制作方法之中，例如，所述开关元件中的钝化层薄膜为非感光树脂、 氮化硅或者氧化硅； 例如， 所述钝化层薄膜的厚度为 150nm ~ 2500nm。
在该制作方法之中， 例如， 所述偏压线层薄膜为氧化铟锡 ITO或者铟锡 氧化物 IZO; 例如， 所述偏压线薄膜厚度为 30nm ~ 120nm。
本发明的实施例提供了一种非晶硅平板 X射线传感器的制作方法，可以 在制备 X射线传感器时， 将例如有源层、 欧姆接触层、 数据线与源漏极金属 层、 p型非晶硅、本征非晶硅、 n型非晶硅和透明电极层使用同一块掩模板进 行不同程度曝光后刻蚀， 减少掩模板的使用数量， 简化生产工序， 提高良品 率。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例工艺流程完成后的非晶硅平板 X射线传感器的电路 结构图示意图；
图 2为本发明的实施例的工艺流程图；
图 3 为本发明的具体实施例的工艺流程完成后的一个像素单元的俯视 图；
图 4A为本发明具体实施例的工艺流程中栅极扫描线形成后的 AA' (图 3中的 AA' )剖面示意图；
图 4B为本发明具体实施例的工艺流程中栅极扫描线形成后的 BB' (图 3 中的 BB' )剖面示意图；
图 5A为本发明具体实施例的工艺流程中栅绝缘层形成后的 AA' (图 3 中的 AA' )剖面示意图；
图 5B为本发明具体实施例的工艺流程中栅绝缘层形成后的 BB' (图 3 中的 BB' )剖面示意图；
图 6A为本发明具体实施例的工艺流程利用一次掩膜曝光的各层沉积后 的 AA' (图 3中的 AA' )剖面示意图；
图 6B为本发明具体实施例的工艺流程利用一次掩膜曝光的各层沉积后 的 BB' (图 3中的 BB' )剖面示意图；
图 7A为本发明具体实施例的工艺流程利用一次掩膜曝光的各层沉积后 涂上光刻胶的 AA' (图 3中的 AA' )剖面示意图；
图 7B为本发明具体实施例的工艺流程利用一次掩膜曝光的各层沉积后 涂上光刻胶的 BB' (图 3中的 BB' )剖面示意图；
图 8A为本发明具体实施例的工艺流程利用一次掩膜曝光的各层在光刻 胶曝光后的 AA' (图 3中的 AA' )剖面示意图；
图 8B为本发明具体实施例的工艺流程利用一次掩膜曝光的各层在光刻 胶曝光后的 BB' (图 3中的 BB' )剖面示意图；
图 9A为本发明具体实施例的工艺流程利用一次掩膜曝光的各层将曝光 部分刻蚀后的 AA' (图 3中的 AA' )剖面示意图；
图 9B为本发明具体实施例的工艺流程利用一次掩膜曝光的各层将曝光 部分刻蚀后的 BB' (图 3中的 BB' )剖面示意图；
图 1 OA为本发明具体实施例的工艺流程利用一次掩膜曝光的各层将曝光 部分刻蚀后的 AA' (图 3中的 AA' )剖面示意图；
图 10B为本发明具体实施例的工艺流程利用一次掩膜曝光的各层将曝光 部分刻蚀后的 BB' (图 3中的 BB' )剖面示意图；
图 11 A为本发明具体实施例的工艺流程利用一次掩膜¾ 光的各层沟道形 成后的 AA' (图 3中的 ΑΑ' )剖面示意图；
图 11B为本发明具体实施例的工艺流程利用一次掩膜¾ 光的各层沟道形 成后的 BB' (图 3中的 ΒΒ' )剖面示意图；
图 12A为本发明具体实施例的工艺流程中钝化层形成后的 AA' (图 3中 的 AA' )剖面示意图；
图 12B为本发明具体实施例的工艺流程中钝化层形成后的 BB' (图 3中 的 BB' )剖面示意图；
图 13A为本发明具体实施例的工艺流程中偏压线形成后的 AA' (图 3中 的 AA' )剖面示意图；
图 13B为本发明具体实施例的工艺流程中偏压线形成后的 BB' (图 3中 的 BB' )剖面示意图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
根据本发明实施例制备的平板 X射线传感器包括由多个像素单元组成的 矩阵。 每个像素单元例如包括用于进行光电转换以产生光电荷的光电二极管 和作为开关元件的薄膜晶体管 （TFT ) 。 每个薄膜晶体管与其相邻的一条栅 极扫描线相连， 而每个光电二极管经由该像素单元内的薄膜晶体管与其相邻 的一条数据线相连。 在多个像素单元组成的矩阵中， 例如， 每一行像素单元 中的各个薄膜晶体管的栅极与该行的一条栅极扫描线相连， 源极分别与相应 的一条数据线相连， 漏极与光电二极管的负极相连。 例如， 光电二极管的正 极和偏压线相连。 各条栅极扫描线与栅极控制单元相连， 各条数据线与源极 控制单元相连。
除非另作定义， 此处使用的技术术语或者科学术语应当为本发明所属领 域内具有一般技能的人士所理解的通常意义。 本发明专利申请说明书以及权 利要求书中使用的 "第一" 、 "第二" 以及类似的词语并不表示任何顺序、 数量或者重要性，而只是用来区分不同的组成部分。同样， "一个 "或者 "一" 等类似词语也不表示数量限制， 而是表示存在至少一个。 "连接" 或者 "相 连" 等类似的词语并非限定于物理的或者机械的连接， 而是可以包括电性的 连接， 不管是直接的还是间接的。 "上" 、 "下" 、 "左" 、 "右" 等仅用 于表示相对位置关系， 当被描述对象的绝对位置改变后， 则该相对位置关系 也相应地改变。
下面结合附图对本发明实施例的具体工艺流程进行说明。 如图 2所示， 本发明的实施例的工艺流程包括：
步骤 S201 , 在基板上形成包括栅电极和栅极扫描线的图形。
步骤 S202,在形成栅电极和栅极扫描线的基板上形成数据线、 TFT开关 元件和光感应元件。
步骤 S203 ,在形成了数据线、 TFT开关元件和光感应元件的基板上形成 钝化层以及偏压线。
如图 3所示， 为本实施例的工艺流程完成后的一个像素单元的俯视图。 每个像素单元包括数据线 a、 开关元件1)、 光感应元件 c, 栅极扫描线 f。 开 关元件 b中有沟道 d和源漏极区域 e。
为了更容易的说明本实施例的工艺流程， 从图 3所示的结构图沿 AA'、
BB'两个方向的剖面图对本发明实施例的非晶硅平板 X射线传感器的制作方 法进行说明， 该制作方法包括如下步骤。
首先， 如图 4A和 4B所示， 在基板上形成栅电极（图中未示出）和栅极 扫描线 2 (如图 3所示， 位于区域 f ) 。
在基板 1上通过构图工艺形成栅电极和栅极扫描线 2。 例如， 以使用正 性光刻胶为例， 所用构图工艺中的掩模板在除栅电极和栅极扫描线 2以外的 地方透光。
本步骤中， 将栅电极和栅极扫描线 2的薄膜形成在整块基板 1上。
本实施例所述的基板可以为玻璃基板、 石英基板等透明基板。 所使用的 薄膜形成工艺可以为沉积、 涂敷、 溅射等工艺。
釆用构图工艺形成栅电极（图中未示出）和栅极扫描线 2(如图 4A所示）。 如图 4B所示， BB'区域没有保留用于形成栅电极和栅极扫描线 2所用的薄 膜。
所述构图工艺可以包括掩膜、 曝光、 显影、 刻蚀等工艺流程。
用于形成栅电极和栅极扫描线的薄膜的材料可以为钼、 铝、 钨、 钛、 铜 等金属， 或者前述金属任意两种的合金， 或者可以为前述金属或其合金的单 层膜或多层膜。 多层膜例如可以包括为钼的第一层、 为铝的第二层， 两种不 同金属层共同形成用于形成栅电极和栅极扫描线的薄膜。 可用于栅电极和栅 极扫描线的金属种类较多。 但是， 为了提高栅极扫描线的稳定性和粘附性， 在实际制造时可根据金属特性进行选择， 或者釆用金属合金。
栅电极和栅极扫描线薄膜厚度例如为 100nm ~ 500nm。 将栅电极和栅极 扫描线金属的厚度控制在一定的范围内 ,可避免在制作平板 X射线传感器时 造成断差 （step )过高。
需要说明的是,所述构图工艺也可以不是在基板上先形成各膜层的薄膜， 然后进行光刻工艺， 而是釆用打印、 网络印刷等工艺直接在基板上形成各个 膜层的图案。
其次， 釆用构图工艺形成栅绝缘层、 TFT开关元件、 数据线和光感应元 件。 该构图工艺中所釆用的掩膜板为灰度掩膜板（例如双色调或半色调掩膜 板）， 该掩膜板上与 TFT开关元件的沟道对应的区域半透光， 与数据线、 光 感应元件以及 TFT开关元件中除沟道分别对应的区域不透光， 除 TFT开关 元件的沟道对应的区域、数据线对应的区域、光感应元件对应的区域以及 TFT 开关元件中沟道以外部分对应的区域外都是全透光的。
构图工艺过程例如包括： 在形成了栅电极和栅极扫描线的基板上依次形 成栅极绝缘层薄膜， 有源层薄膜， 欧姆接触层薄膜、 数据线与源漏极金属层 薄膜、 非晶硅层薄膜、 透明电极层薄膜， 然后对这些薄膜的叠层进行构图。
栅绝缘层薄膜 3形成来覆盖整块基板 1 , 如图 5A和图 5B所示。 该薄膜 形成工艺可以为沉积、 涂敷或溅射等工艺。 栅绝缘层可以为氮化硅或氧化硅 等薄膜。 氮化硅和氧化硅都是很好的绝缘薄膜。
在形成上述透明电极层薄膜的基板上形成一层光刻胶。 设置灰度掩模板 对该光刻胶进行曝光， 与该灰度掩膜板不透光区域对应的光刻胶未曝光， 与 该灰度掩膜板半透光区域对应的光刻胶半曝光， 而与该灰度掩膜板全透光区 域对应的光刻胶完全曝光。 这里， 该掩膜板半曝光区域例如为半透光区域， 即 50%曝光， 当然， 也可是 60%或 70%曝光， 根据工艺要求选择掩膜板半曝 光区域的曝光率。
仍以正性光刻胶为例进行说明。 对曝光后的光刻胶进行显影， 未曝光区 域的光刻胶完全保留， 半曝光区域的光刻胶部分保留， 完全曝光区域的光刻 胶被全部去除。 请注意这里所述的 "光刻胶完全保留" 仅表示光刻胶的绝大 部分被保留， 而非没有任何损耗。
将光刻胶完全去除区域中所对应的非晶硅层薄膜、 数据线与源漏极金属 层薄膜、 欧姆接触层薄膜、 有源层薄膜、 透明电极层薄膜进行刻蚀并全部去 除。
数据线与源漏极金属层可以通过湿法或干法工艺刻蚀去除无需保留的叠 层的部分后形成。
对光刻胶部分保留区域（即光刻胶半曝光区域） 的光刻胶进行灰化， 将 光刻胶部分保留区域的光刻胶全部去除， 暴露出沟道， 同时将光刻胶完全保 留区域中的光刻胶部分保留； 然后， 将光刻胶部分保留区域中对应的非晶硅 层薄膜、 数据线与源漏极金属层薄膜刻蚀形成 TFT开关元件沟道。
去除光刻胶全部保留区域的光刻胶， 釆用构图工艺将光刻胶完全保留区 域对应的膜层薄膜进行构图，最终形成数据线、 TFT开关元件和光感应元件。
通过上述过程即可通过一次掩膜工艺形成数据线， TFT开关元件和光感 应元件。
本发明实施例中， 非晶硅层由下至上包括： n型非晶硅层、 本征非晶硅 层、 p型非晶硅层， 该叠层用于形成光电二极管的光电转换结构层。 透明电 极层的薄膜可以为铟锡氧化物（ITO ) , 但不仅限于 ITO, 也可以为铟锡氧 化物（IZO ) 、 氧化锡（Sn02 )等其它透明导电薄膜。
数据线与 TFT开关元件的源极在数据线与源漏极金属层相连， TFT开关 元件的源漏极通过沟道处的有源层和欧姆接触层导通。 TFT开关元件的漏极 与光感应元件在数据线层与源漏极相连。
在本实施例中， 本步骤的一个具体的示例如下所述。
在形成有栅电极和栅极扫描线的基板上依次形成栅绝缘层薄膜 3、 有源 层薄膜 4、 欧姆接触层薄膜 5、 数据线与源漏极金属层 6、 n型非晶硅层薄膜 7, 本征非晶硅层薄膜 8、 p型非晶硅层薄膜 9、 透明电极层薄膜 10。 形成后 的叠层结构如图 6A和图 6B所示。
在透明电极层薄膜 10上形成一层光刻胶 11 , 如图 7A和图 7B所示。 利用灰色调掩模板对光刻胶 11进行曝光。 与 TFT开关元件 b的沟道 d 区域对应的光刻胶半曝光， 显影工艺后， 该部分光刻胶部分保留； 与数据线 a、光感应元件 c, 以及 TFT开关元件 b中除沟道 d部分以外的区域对应的光 刻胶不进行曝光处理， 显影工艺后， 该部分光刻胶被完全保留； 对上述区域 以外的区域所对应的光刻胶进行完全曝光和显影工艺后， 该部分光刻胶被完 全去除。
图 8A和图 8B为对形成的光刻胶曝光、 显影后的示意图。
釆用构图工艺， 对光刻胶完全去除区域所对应的区域进行构图， 即将该 区域中露出的叠层进行刻蚀， 形成透明电极层 10'、 p型非晶硅层 9'、 本征非 晶硅层 8'、 n型非晶硅层 7'、 数据线与源漏极金属层 6'、 欧姆接触层 5'、 有 源层 4'。
图 9A和图 9B为构图工艺后的基板示意图。
对光刻胶部分保留区域的光刻胶进行灰化， 去除该部分光刻胶， 同时光 刻胶完全保留区域的光刻胶被部分保留，如图 10A和图 10B所示。 然后釆用 构图工艺， 对光刻胶部分保留区域所对应的区域进行构图， 即将新露出的叠 层进行刻蚀， 形成沟道图案。 图 11A和 11B为沟道形成后的基板示意图。
最后去除光刻胶完全保留区域的光刻胶。 由此， 通过构图工艺形成数据 线、 TFT开关元件和光感应元件。
然后， 可以将 TFT开关元件的源漏极和数据线上的非晶硅层刻蚀去除。 由于本制作方法对有源层、 欧姆接触层、 数据线与源漏极金属层、 非晶硅层 釆用逐层沉积， 然后利用灰色调掩模板进行光刻， 只用一次掩膜工艺， 在数 据线、 TFT开关元件上的非晶硅层虽然非必要但仍然还存在。 可以选择釆用 构图工艺对留下的非晶硅层进行刻蚀， 或者， 为了节省工序和操作成本而将 其继续留在数据线、 TFT开关元件上。
例如， 有源层薄膜为 n型非晶硅， 但不限于此， 例如还可以为氧化物半 导体等适当的材料。 利用 n型非晶硅作为有源层的材料， 可达到良好的导电 性。
例如， 有源层薄膜厚度为 30nm ~ 300nm。
例如， 欧姆接触层薄膜厚度为 30nm ~ 100nm。
例如， n型非晶硅层薄膜厚度为 30nm ~ 100nm。
例如， p型非晶硅厚度为 30nm-100nm。 例如， 本征非晶硅层薄膜厚度为 100nm ~ 2000nm
将各层薄膜的厚度控制在一定范围内， 既可以保证各层功能有效， 还可 以避免因各区域膜层的厚度相差过大而影响各部分的功能。
然后， 在完成了上述步骤的基板上形成钝化层 12。 图 12A和 12B为形 成了钝化层之后的示意图。
本步骤的一个具体示例说明如下。
在整块基板 1上形成一层钝化层薄膜 12, 如图 12A和 12B所示并结合 图 3; 在钝化层薄膜 12上形成一层光刻胶（图中未示出） 。
利用掩模板对对应于数据线区域 a、 光感应元件区域 c和栅极扫描线区 域 f中的过孔 h区域的光刻胶进行曝光。
釆用构图工艺， 将与数据线区域对应的区域中的钝化层去除， 与光感应 元件部分对应的区域中的钝化层薄膜去除， 将与栅极扫描线区域 f 中的过孔 h对应的区域中的钝化层薄膜去除。 让过孔中的透明电极层 10暴露。
开关元件中的钝化层薄膜优选为树脂或氮化硅。 以氮化硅为原料的钝化 层能够很好的起到绝缘作用。 以树脂制成的钝化层， 能够更容易均匀覆盖， 表面也更易平坦， 本领域人员应该知道的是， 釆用其它任何与树脂或者氮化 硅具有相同功能的材料也可以， 本发明对此不做限定。
例如，钝化层薄膜的厚度为 150nm ~ 2500nm。 将钝化层薄膜的厚度控制 在此区间内， 既能保证钝化层能够有效的绝缘， 也不会因为厚度过厚而造成 断差过高。
最后， 在钝化层 12上形成偏压线。
在完成上述步骤的基板上形成一层偏压线薄膜， 再通过构图工艺使偏压 线成型。 该构图工艺例如包括掩膜、 曝光、 显影、 刻蚀等工艺流程； 也可以 不为在基板上先形成各膜层的薄膜然后进行光刻， 而是釆用打印、 网络印刷 等工艺直接在基板上形成各个膜层的图案。 图 13A和 13B为偏压线 13形成 后的示意图。
偏压线用于形成偏电压。 传感器阵列中的各个传感器的偏压线需要相互 连接并引至外围。 本实施例中可将偏压线制成梳状， 也可以制成块状（其中 任意相连两个块状偏压线互相连接） ， 或者也可以是整个传感器阵列区域大 面积覆盖。 偏压线会如图 13A所示， 经过过孔 h与透明电极层薄膜 10接触 连接。
传感器周边引线的引脚区域附近的偏压线是必须要刻蚀掉的， 以免与各
？ I脚短接。 传感器周边引线的引脚区域附近的偏压线的刻蚀可在形成偏压线 的掩膜、 曝光、 显影、 刻蚀等工艺流程中进行， 也可单独进行刻蚀去除。
偏压线层薄膜可以为 ITO (铟锡氧化物）或者 IZO (铟锡氧化物）等导 电透明薄膜。
此处 ITO的沉积方式优选是常温非晶模式； 高温多晶模式沉积会将基板 上的光刻胶固化变性难以剥离。 非晶 ITO最后经退火工艺转为导电性、 透光 性更好的多晶 ITO。 退火工艺是指将 ITO加热到一定临界点温度， 保持一定 时间后， 緩慢冷却的过程。
例如， 所述偏压线薄膜厚度为 30nm ~ 120nm。 将偏压线薄膜的厚度控制 在此区间， 可以既使得偏压线能够起到导电作用， 又不会因为偏压线厚度太 厚而导致断差过高。
利用本发明的制作方法制造出的一种非晶硅平板 X射线传感器如图 3、 图 13A和 13B所示。
非晶硅平板 X射线传感器包括数据线 、 TFT开关元件1)、光感应元件 c 和栅极扫描线 f。 TFT开关元件包括： 栅电极、 有源层、 欧姆接触层、 源极、 漏极。
由于本发明实施例对应的制作方法对有源层、 欧姆接触层、 数据线与源 漏极金属层、 非晶硅层和透明电极层， 釆用逐层形成， 然后利用灰色调掩模 板进行光刻， 只用一次掩膜工艺进行刻蚀、 构图。 在数据线、 TFT开关元件 的上的非晶硅层虽然非必要但仍然还存在， 可以釆用构图工艺对留下的非晶 硅层进行刻蚀，或者，为了节省工序和操作成本而将其继续留在数据线、 TFT 开关元件上。
非晶硅层包括 n型非晶硅层、 本征非晶硅层和 p型非晶硅层的叠层。 本发明的实施例在形成数据线、 TFT开关元件和光感应元件时， 只需使 用一次掩膜工艺，利用灰色调掩膜板，对不同部位覆盖的光刻胶进行全曝光、 半曝光和不曝光处理。 这样可以只使用一次掩模板曝光形成数据线、 TFT开 关元件和光感应元件， 这不仅简化了生产工序还节约了生产成本， 同时也提 高产品的良品率。 发明的精神和范围， 则本发明的保护范围也意图包含这些改动和变型在内。

Claims

权利要求书
1、 一种非晶硅平板 X射线传感器的制作方法， 包括：
在基板上形成包括栅电极和栅极扫描线的图形；
在形成栅极线和栅极扫描线的基板上形成数据线、 薄膜晶体管 （TFT ) 开关元件和光感应元件；
在形成了数据线、 TFT开关元件和光感应元件的基板上形成钝化层以及 偏压线。
2、 根据权利要求 1所述的非晶硅平板 X射线传感器的制作方法， 其中， 在形成栅极线和栅极扫描线的基板上形成数据线、 TFT开关元件和光感应元 件的方法包括：
通过一次掩膜工艺形成数据线、 TFT开关元件和光感应元件，
其中， 所述掩膜工艺中的掩膜板上， 与所述 TFT开关元件的沟道对应的 区域半透光， 用于得到光刻胶部分保留区域， 与所述数据线、 光感应元件以 及 TFT开关元件中除沟道以外的部分分别对应的区域不透光，用于得到光刻 胶完全保留区域， 除了所述 TFT开关元件的沟道对应的区域、数据线对应的 区域、 光感应元件对应的区域以外的其他区域全透光， 用于得到光刻胶完全 去除区域。
3、 根据权利要求 2所述的非晶硅平板 X射线传感器的制作方法， 其中， 所述通过一次掩膜工艺形成数据线、 TFT开关元件和光感应元件包括：
在形成了所述栅电极和栅极扫描线的基板上依次形成栅极绝缘层薄膜， 有源层薄膜， 欧姆接触层薄膜、数据线与源漏极金属层薄膜、非晶硅层薄膜、 透明电极层薄膜、 光刻胶层薄膜；
利用所述掩膜工艺中的掩模板对所述光刻胶层进行曝光并显影得到光刻 胶图案， 包括所述光刻胶完全去除区域、 所述光刻胶部分保留区域和所述光 刻胶完全保留区域；
将所述光刻胶完全去除区域中的透明电极层薄膜、 非晶硅层薄膜、 数据 线与源漏极金属层薄膜、 欧姆接触层薄膜、 有源层薄膜刻蚀去除； 然后， 将 所述光刻胶部分保留区域中的光刻胶去除， 暴露出所述沟道， 将暴露后的区 域中的透明电极层薄膜、 非晶硅层薄膜、 源漏极金属层薄膜刻蚀形成 TFT开 关元件沟道； 然后， 去除所述光刻胶完全保留区域中的光刻胶，暴露数据线、
TFT开关元件和光感应元件。
4、 根据权利要求 3所述的非晶硅平板 X射线传感器的制作方法， 其中， 在所述光刻胶部分保留区域中将暴露后的区域中的透明电极层薄膜、 非晶硅 层薄膜、数据线与源漏极金属层薄膜刻蚀形成 TFT开关元件沟道后， 该方法 进一步包括：
将 TFT开关元件的数据线与源漏极金属层上的非晶硅层薄膜刻蚀去除。
5、 根据权利要求 3或 4所述的非晶硅平板 X射线传感器的制作方法， 其中， 所述非晶硅层包括依次层叠的 n型非晶硅层、 本征非晶硅层、 p型非 晶娃层。
6、 根据权利要求 1-5任一所述的非晶硅平板 X射线传感器的制作方法， 其中， 所述栅极和栅极扫描线为钼、 铝、 钨、 钛、 铜或者前述金属任意两种 的合金， 为单层膜或多层膜， 其中， 所述栅极和栅极扫描线厚度为 100nm ~ 500匪。
7、 根据权利要求 3-5任一所述的非晶硅平板 X射线传感器的制作方法， 其中， 所述栅绝缘层薄膜为氮化硅或氧化硅， 其中， 所述栅绝缘层薄膜的厚 度为 250匪 ~ 600匪；
8、 根据权利要求 3-5任一所述的非晶硅平板 X射线传感器的制作方法， 其中， 所述有源层薄膜为 n型非晶硅， 且所述有源层薄膜厚度为 30nm ~ 300匪。
9、 根据权利要求 3-5任一所述的非晶硅平板 X射线传感器的制作方法， 其中， 所述欧姆接触层薄膜厚度为 30nm ~ 100nm。
10、根据权利要求 3-5任一所述的非晶硅平板 X射线传感器的制作方法， 其中， 所述非晶硅薄膜中的 n型非晶硅薄膜层厚度为 30nm ~ 100nm, 所述本 征非晶硅薄膜层厚度为 100匪 ~ 2000nm。
11、 根据权利要求 1-10任一所述的非晶硅平板 X射线传感器的制作方 法， 其中， 所述在形成了 TFT开关元件和光感应元件的基板上形成钝化层以 及偏压线包括：
在形成了 TFT 开关元件和光感应元件的基板上通过一次掩膜工艺形成 钝化层， 其中， 所用掩膜工艺的掩模板在除光感应元件区域、 过孔区域外不 透光；
在钝化层上形成偏压线。
12、 根据权利要求 11所述的非晶硅平板 X射线传感器的制作方法， 其 中， 所述开关元件中的钝化层薄膜为非感光树脂、 氮化硅或者氧化硅， 其中， 所述钝化层薄膜的厚度为 150nm ~ 2500nm。
13、根据权利要求 11或 12所述的非晶硅平板 X射线传感器的制作方法， 其中， 所述偏压线层薄膜为氧化铟锡 ITO或者铟锡氧化物 IZO, 其中， 所述 偏压线薄膜厚度为 30nm ~ 120nm。
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