WO2013164348A1 - Verfahren zum herstellen keramischer leiterplatten aus keramiksubstraten mit metallgefüllten vias - Google Patents
Verfahren zum herstellen keramischer leiterplatten aus keramiksubstraten mit metallgefüllten vias Download PDFInfo
- Publication number
- WO2013164348A1 WO2013164348A1 PCT/EP2013/059012 EP2013059012W WO2013164348A1 WO 2013164348 A1 WO2013164348 A1 WO 2013164348A1 EP 2013059012 W EP2013059012 W EP 2013059012W WO 2013164348 A1 WO2013164348 A1 WO 2013164348A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- vias
- copper
- ceramic
- filled
- μιτι
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/027—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0723—Electroplating, e.g. finish plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
- H05K3/043—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by using a moving tool for milling or cutting the conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
Definitions
- the invention relates to a method for producing ceramic circuit boards of ceramic substrates with metal-filled vias.
- Ceramic circuit boards with completely metal-filled vias can be prepared in the prior art by repeatedly filling the vias in the ceramic substrate with templates and structure of a surface metallization by a first screen printing, baking and galvanic amplification to over 100 ⁇ . Through a single filling process (Viafilivorgang) you can not completely fill vias with copper pastes.
- the invention has for its object to improve a method according to the preamble of claim 1 so that the vias can be filled with a single filling.
- a voltage can be applied. It should be noted that the Kupfernetallmaschine or the copper foil covering the vias unilaterally.
- a voltage is applied to the copper metallization or to the copper foil in the copper bath and the vias are filled from the ceramic side.
- ceramic side is meant the side opposite to the side of the copper metallization or the copper foil.
- the copper metallization is partially covered by a galvano resist and then the vias are filled by the electrogalvanic process in a copper bath and at the same time the exposed (not under the Galvano Resist) games to layer thicknesses of 50- Reinforced 100 ⁇ and then the electroplating Resist again chemically removed and provided with screen printed thinner unreinforced parts that were previously under the Galvano Resist dissolved. It can be made as any metallization with any thicknesses.
- the vias are completely filled with copper.
- a possibly protruding copper ridge is mechanically by z.
- brushing, lapping or grinding removed and then the ceramic substrates in the DCB / DBC process are completed. Even with these process steps, any metallization can be made with any thicknesses.
- the vias are completely filled with copper.
- the areas provided with screen printing are dissolved with a mixture of HCl + FeCl 3 .
- the vias preferably have a diameter of 50 to 5000 ⁇ and are preferably introduced by lasers.
- the ceramic substrate is rotated in the copper bath with the ceramic side to the anode mounted in the electroplating process in the electroplating process and rinsed with electrolyte. This greatly improves the filling of the vias. Through the use of vibration and / or ultrasound in the electroplating tank mass transfer can be improved.
- a copper metallization is thus applied by screen printing on the ceramic substrate, with the vias previously introduced, for example by lasers, on one side, but at the same time it is pressed uncontrollably into the vias.
- the coating thickness is usually after the firing at 6-12 ⁇ , the vias are border metallized, but not hermetically closed.
- the copper metallization is partially covered by a Galvano Resist.
- Galvao Resist is meant materials that are applied to the metallization or copper foil to prevent electrodeposition where it covers the surface.
- the ceramic substrate After application of the Galvano Resist, the ceramic substrate is immersed in a copper bath. There, the vias are grown by an electrogalvanic process by deposition of copper and the exposed (not under the Galvano Resist) games are amplified to layer thicknesses of 50-100 ⁇ . Then the Galvano Resist is chemically removed (dissolved) again.
- the thin screen-printed sections are made with, for example, a mixture HCI + FeCl 3 dissolved. The thicker parts of the metallization are thinned only slightly. For higher quality products, the galvanized layout can be protected by tinning or photoresist before stripping the resist.
- the second Möglickeit or inventive variant is to laser in the ceramic substrates of any type and thickness vias and coated on one side with copper foil of 100 -300 ⁇ in the DCB / DBC process.
- the vias (diameter 50-5000 ⁇ ) can then be filled with the previously described method.
- the supernatant copper burr is mechanically broken, e.g. removed by brushing, lapping or sanding.
- the thus treated semi-substrates can then be completed in the DCB / DBC process and have a reliable via.
- the ceramic substrate is turned in the copper bath with the ceramic side towards the anode mounted in the galvanic basin and rinsed with electrolyte.
- the vias are therefore filled from the ceramic side.
- Through the use of vibration and / or ultrasound is a further improvement of the mass transfer possible. Due to the more intensive mass transfer the vias grow especially fast with copper.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Electroplating Methods And Accessories (AREA)
- ing And Chemical Polishing (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP13721642.0A EP2845454A1 (de) | 2012-05-02 | 2013-04-30 | Verfahren zum herstellen keramischer leiterplatten aus keramiksubstraten mit metallgefüllten vias |
CN201380023208.9A CN104412720A (zh) | 2012-05-02 | 2013-04-30 | 由具有金属填充的过孔的陶瓷基底制造陶瓷电路板的方法 |
US14/397,675 US20150108003A1 (en) | 2012-05-02 | 2013-04-30 | Method for producing ceramic circuit boards from ceramic substrates having metal-filled vias |
JP2015509420A JP6231079B2 (ja) | 2012-05-02 | 2013-04-30 | 金属が充填されたビアを有するセラミック基板からなるセラミックプリント基板を製造する方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102012207283 | 2012-05-02 | ||
DE102012207283.7 | 2012-05-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2013164348A1 true WO2013164348A1 (de) | 2013-11-07 |
Family
ID=48407468
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2013/059012 WO2013164348A1 (de) | 2012-05-02 | 2013-04-30 | Verfahren zum herstellen keramischer leiterplatten aus keramiksubstraten mit metallgefüllten vias |
Country Status (7)
Country | Link |
---|---|
US (1) | US20150108003A1 (de) |
EP (1) | EP2845454A1 (de) |
JP (1) | JP6231079B2 (de) |
CN (1) | CN104412720A (de) |
DE (1) | DE102013207942A1 (de) |
TW (1) | TW201410085A (de) |
WO (1) | WO2013164348A1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105491795A (zh) * | 2014-09-18 | 2016-04-13 | 浙江德汇电子陶瓷有限公司 | 一种陶瓷金属化基板的制造方法和由该方法制造的陶瓷金属化基板 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3318566B1 (de) | 2012-09-20 | 2020-06-24 | UDC Ireland Limited | Azadibenzofurane für elektronische anwendungen |
CN108133886A (zh) * | 2017-12-11 | 2018-06-08 | 上海申和热磁电子有限公司 | 一种dbc基板背面研磨的方法 |
CN109037079B (zh) * | 2018-07-13 | 2020-06-16 | 无锡天杨电子有限公司 | 一种轨道交通芯片用氮化物陶瓷覆铜板的图形化方法 |
CN109618505B (zh) * | 2018-10-30 | 2020-01-03 | 华中科技大学 | 一种直接敷铜陶瓷基板的高厚径比通孔互连的方法 |
CN111834324A (zh) * | 2019-04-15 | 2020-10-27 | 谭祖荣 | 适用于覆晶及共晶元件封装的抛光厚膜基板及其制造方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4964923A (en) * | 1985-07-26 | 1990-10-23 | Ngk Insulators, Ltd. | Method of forming a copper film on a ceramic body |
US5298687A (en) * | 1990-12-27 | 1994-03-29 | Remtec, Inc. | High-density multilayer interconnection system on a ceramic substrate for high current applications and method of manufacture |
US6093443A (en) * | 1997-11-12 | 2000-07-25 | Curamik Electronics Gmbh | Process for producing a ceramic-metal substrate |
US20070186413A1 (en) * | 2006-02-08 | 2007-08-16 | Shih-Ping Hsu | Circuit board structure and method for fabricating the same |
US20090029037A1 (en) * | 2006-02-22 | 2009-01-29 | Ibiden Co., Ltd | Plating apparatus and method of plating |
DE102009033029A1 (de) * | 2009-07-02 | 2011-01-05 | Electrovac Ag | Elektronische Vorrichtung |
US20110035939A1 (en) * | 2002-12-11 | 2011-02-17 | Dai Nippon Printing Co., Ltd. | Multilayer wiring board and manufacture method thereof |
Family Cites Families (12)
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DE2147573C2 (de) * | 1971-09-23 | 1974-06-12 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zur Herstellung von mikroelektronischen Schaltungen |
US5340947A (en) * | 1992-06-22 | 1994-08-23 | Cirqon Technologies Corporation | Ceramic substrates with highly conductive metal vias |
US6159853A (en) * | 1999-08-04 | 2000-12-12 | Industrial Technology Research Institute | Method for using ultrasound for assisting forming conductive layers on semiconductor devices |
DE60044974D1 (de) * | 1999-08-12 | 2010-10-28 | Ibiden Co Ltd | Mehrschichtige leiterplatte und leiterplatten-herstellungsmethode |
US20030146102A1 (en) * | 2002-02-05 | 2003-08-07 | Applied Materials, Inc. | Method for forming copper interconnects |
JP2004103798A (ja) * | 2002-09-09 | 2004-04-02 | Shinko Electric Ind Co Ltd | 2メタルテープの製造方法および配線基板の製造方法 |
JP4153328B2 (ja) * | 2003-02-25 | 2008-09-24 | 日本シイエムケイ株式会社 | 多層プリント配線板の製造方法 |
JP2004300462A (ja) * | 2003-03-28 | 2004-10-28 | Ebara Corp | めっき方法及びめっき装置 |
JP4626254B2 (ja) * | 2004-10-12 | 2011-02-02 | パナソニック電工株式会社 | 貫通孔へのメッキ埋め込み方法及びメッキ装置 |
US8663484B2 (en) * | 2007-07-09 | 2014-03-04 | Sumitomo Metal Mining Co., Ltd. | Method for manufacturing a printed circuit board and a printed circuit board obtained by the manufacturing method |
JP5191331B2 (ja) * | 2008-09-26 | 2013-05-08 | 新日本無線株式会社 | スルーホールフィリング方法 |
JP5621311B2 (ja) * | 2010-05-11 | 2014-11-12 | 富士通株式会社 | 回路基板の製造方法 |
-
2013
- 2013-04-26 TW TW102114943A patent/TW201410085A/zh unknown
- 2013-04-30 CN CN201380023208.9A patent/CN104412720A/zh active Pending
- 2013-04-30 JP JP2015509420A patent/JP6231079B2/ja not_active Expired - Fee Related
- 2013-04-30 DE DE201310207942 patent/DE102013207942A1/de not_active Withdrawn
- 2013-04-30 US US14/397,675 patent/US20150108003A1/en not_active Abandoned
- 2013-04-30 EP EP13721642.0A patent/EP2845454A1/de not_active Withdrawn
- 2013-04-30 WO PCT/EP2013/059012 patent/WO2013164348A1/de active Application Filing
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4964923A (en) * | 1985-07-26 | 1990-10-23 | Ngk Insulators, Ltd. | Method of forming a copper film on a ceramic body |
US5298687A (en) * | 1990-12-27 | 1994-03-29 | Remtec, Inc. | High-density multilayer interconnection system on a ceramic substrate for high current applications and method of manufacture |
US6093443A (en) * | 1997-11-12 | 2000-07-25 | Curamik Electronics Gmbh | Process for producing a ceramic-metal substrate |
US20110035939A1 (en) * | 2002-12-11 | 2011-02-17 | Dai Nippon Printing Co., Ltd. | Multilayer wiring board and manufacture method thereof |
US20070186413A1 (en) * | 2006-02-08 | 2007-08-16 | Shih-Ping Hsu | Circuit board structure and method for fabricating the same |
US20090029037A1 (en) * | 2006-02-22 | 2009-01-29 | Ibiden Co., Ltd | Plating apparatus and method of plating |
DE102009033029A1 (de) * | 2009-07-02 | 2011-01-05 | Electrovac Ag | Elektronische Vorrichtung |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105491795A (zh) * | 2014-09-18 | 2016-04-13 | 浙江德汇电子陶瓷有限公司 | 一种陶瓷金属化基板的制造方法和由该方法制造的陶瓷金属化基板 |
Also Published As
Publication number | Publication date |
---|---|
JP2015520944A (ja) | 2015-07-23 |
CN104412720A (zh) | 2015-03-11 |
TW201410085A (zh) | 2014-03-01 |
JP6231079B2 (ja) | 2017-11-15 |
US20150108003A1 (en) | 2015-04-23 |
DE102013207942A1 (de) | 2013-11-07 |
EP2845454A1 (de) | 2015-03-11 |
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