WO2013155746A1 - 一种液晶面板、液晶显示装置及其阵列基板的制作方法 - Google Patents

一种液晶面板、液晶显示装置及其阵列基板的制作方法 Download PDF

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WO2013155746A1
WO2013155746A1 PCT/CN2012/075424 CN2012075424W WO2013155746A1 WO 2013155746 A1 WO2013155746 A1 WO 2013155746A1 CN 2012075424 W CN2012075424 W CN 2012075424W WO 2013155746 A1 WO2013155746 A1 WO 2013155746A1
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Prior art keywords
hole
liquid crystal
auxiliary hole
region
array substrate
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PCT/CN2012/075424
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English (en)
French (fr)
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郑扬霖
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深圳市华星光电技术有限公司
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Priority to US13/522,293 priority Critical patent/US8958036B2/en
Publication of WO2013155746A1 publication Critical patent/WO2013155746A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133707—Structures for producing distorted electric fields, e.g. bumps, protrusions, recesses, slits in pixel electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/133753—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers with different alignment orientations or pretilt angles on a same surface, e.g. for grey scale or improved viewing angle
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/137—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering
    • G02F1/139—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering based on orientation effects in which the liquid crystal remains transparent
    • G02F1/1393—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells characterised by the electro-optical or magneto-optical effect, e.g. field-induced phase transition, orientation effect, guest-host interaction or dynamic scattering based on orientation effects in which the liquid crystal remains transparent the birefringence of the liquid crystal being electrically controlled, e.g. ECB-, DAP-, HAN-, PI-LC cells

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a liquid crystal panel, a liquid crystal display device, and a method for fabricating the same.
  • liquid crystal displays are increasingly becoming the mainstream of display products on the market, and liquid crystal panels are the main components of liquid crystal displays.
  • a gate metal layer, an active layer, a source metal layer, a through hole (VIA), and a pixel electrode layer are sequentially formed on the array substrate.
  • the through hole is formed by an etching method.
  • the time control of forming the through hole by etching has a great influence on the manufacturing precision.
  • the through hole is formed by giving a certain etching time in advance.
  • the actual etching time required for the formation of the through holes is affected by the film thickness obtained in the previous process.
  • the film thickness of the pre-process is difficult to control, and thus the actual etching time required for the formation of the through holes is difficult to be predetermined. In this case, there is a problem that the predetermined etching time is too short or too long.
  • the technical problem to be solved by the present invention is to provide a liquid crystal panel, a liquid crystal display device and a method for fabricating the same, which can detect the etching end point (End In the Point Detector mode (EPD) technology, the amplification detection voltage can further monitor the formation process of the through holes more accurately and reliably, and ensure the quality of the through holes.
  • EPD etching end point
  • the amplification detection voltage can further monitor the formation process of the through holes more accurately and reliably, and ensure the quality of the through holes.
  • a technical solution adopted by the present invention is to provide a liquid crystal panel, wherein the liquid crystal panel includes a color filter substrate and an array substrate which are spaced apart, and the array substrate is an array substrate of a pixel-divided vertical alignment liquid crystal display; A plurality of pixel units are disposed on the surface of the array substrate adjacent to the color filter substrate, and the pixel unit includes a thin film transistor, a pixel electrode, and a through hole electrically connecting the thin film transistor and the pixel electrode; wherein at least one and the through hole are disposed between the pixel units or in the pixel unit
  • the auxiliary hole formed by the etch end point mode etching method is disposed together, and the auxiliary hole is disposed adjacent to one end of the pixel electrode; and the color filter substrate is disposed with a black matrix adjacent to the surface of the array substrate, and the black matrix blocks the auxiliary hole.
  • the area of the auxiliary hole is larger than the area of the through hole.
  • the auxiliary hole is disposed adjacent to the position of the data line of the pixel electrode.
  • a liquid crystal display device including a liquid crystal panel and a backlight module, wherein: the liquid crystal panel includes a color filter substrate and an array substrate which are spaced apart; A plurality of pixel units are disposed on the surface of the array substrate adjacent to the color filter substrate, and the pixel unit includes a thin film transistor, a pixel electrode, and a through hole electrically connecting the thin film transistor and the pixel electrode; wherein at least one and the through hole are disposed between the pixel units or in the pixel unit Auxiliary holes formed by the etch end point mode etching method are used together.
  • the color filter substrate is disposed with a black matrix adjacent to the surface of the array substrate, and the black matrix blocks the auxiliary holes.
  • the array substrate is an array substrate of a pixel-divided vertical alignment liquid crystal display, and the auxiliary hole is disposed adjacent to one end of the pixel electrode.
  • the auxiliary hole is disposed adjacent to the position of the data line of the pixel electrode.
  • the area of the auxiliary hole is larger than the area of the through hole.
  • another technical solution adopted by the present invention is to provide a method for fabricating an array substrate, comprising: forming a thin film transistor as a part of a pixel unit on a glass substrate, and forming a pixel unit on the glass substrate In a region, the first region corresponds to a minimum cutting panel unit of the glass substrate, the glass substrate defines at least two spaced apart first regions, and the region between the first regions on the glass substrate is defined as a second region, the glass substrate The peripheral area outside all the first areas above is defined as the third area; A through hole is formed on the glass substrate by using a etch end point mode etching method, and the through hole is electrically connected to the thin film transistor and the pixel electrode formed in the subsequent etching process, in the process of detecting the etching end mode etching, and simultaneously in the first region, An auxiliary hole is formed in at least one of the second region and the third region, and the etchant and the concentration of the product in the dry etching environment when the through
  • the step of forming the auxiliary holes includes: forming the auxiliary holes on the glass substrate at positions corresponding to the black matrix of the color filter substrate.
  • the step of forming the auxiliary hole comprises: forming the auxiliary hole, and causing the auxiliary hole to be disposed adjacent to one end of the pixel electrode.
  • the step of forming the auxiliary hole comprises: setting the position of the auxiliary hole adjacent to the data line of the pixel electrode.
  • the step of forming the auxiliary hole comprises: setting the auxiliary hole at a position where the electronic circuit of the second region or the third region is relatively less.
  • the array substrate includes a fourth region in which only the insulating layer exists and the remaining fifth region, and the step of forming the auxiliary hole includes: setting the auxiliary hole in the fourth region.
  • the step of forming the auxiliary hole comprises: forming the auxiliary hole, and making the area of the auxiliary hole larger than the area of the through hole.
  • the present invention provides an auxiliary hole formed in the pixel unit together with the through hole, and the addition of the non-functional auxiliary hole is equivalent to the addition of the EPD mode etching method.
  • the detected object can effectively amplify the detection voltage change corresponding to the detection data, so that the formation process of the through hole can be monitored more accurately and reliably, and the quality of the through hole can be ensured.
  • FIG. 1 is a schematic cross-sectional view showing an embodiment of a liquid crystal panel of the present invention
  • FIG. 2 is a plan view showing a pixel unit of the present invention as shown in FIG. 1;
  • Figure 3 is a schematic cross-sectional view of the auxiliary hole shown in Figure 2 in the AB direction;
  • FIG. 4 is a flow chart showing a first embodiment of a method for fabricating an array substrate of the present invention
  • Figure 5 is a plan view showing the array substrate produced in the auxiliary hole forming step shown in Figure 4;
  • FIG. 6 is a flow chart of a second embodiment of a method for fabricating an array substrate of the present invention.
  • FIG. 7 is a diagram showing a relationship between a detection voltage and a dry etching time in an EPD mode etching method in the prior art
  • FIG. 8 is a diagram showing the relationship between the detection voltage and the dry etching time using the EPD mode etching method in the embodiment of the method for fabricating the array substrate of the present invention.
  • the liquid crystal panel embodiment includes an array substrate 1 and a color filter substrate 2 .
  • the array substrate 1 includes a glass substrate 10 and a pixel unit 20, and the color filter substrate 2 includes a black matrix 30 and a glass substrate 40.
  • the array substrate 1 and the color filter substrate 2 are spaced apart.
  • the glass substrate 10 is disposed adjacent to the surface of the color filter substrate 2 with a plurality of pixel units 20, and the pixel units 20 may be arranged in a matrix.
  • the pixel unit 20 includes a thin film transistor 200, a pixel electrode 201, and a through hole 202 electrically connecting the thin film transistor 200 and the pixel electrode 201.
  • the pixel unit 20 is provided with at least one auxiliary hole 203 formed by the EPD mode etching method together with the through hole 202.
  • the black matrix 30 is disposed on the surface of the color filter substrate 2 adjacent to the array substrate 1.
  • the black matrix 30 blocks the auxiliary holes 203 so as not to affect the display area of the pixel unit 20.
  • the array substrate 1 is an array substrate of a pixel-divided vertical alignment liquid crystal display, and the auxiliary hole 203 is disposed adjacent to one end of the pixel electrode 201, for example, the position of the auxiliary hole 203 adjacent to the data line of the pixel electrode 201.
  • FIG. 3 is a schematic cross-sectional view of the auxiliary hole shown in FIG. 2 along the AB direction.
  • the formation of the auxiliary holes 203 is performed in synchronization with the formation of the through holes 202, and the film layer on the glass substrate 10 is etched until etching to the surface of the glass substrate 10.
  • the insulating layer 1001 on the surface of the glass substrate 10 and the protective layer 1002 are etched out of the auxiliary hole 203, and the bottom of the auxiliary hole 203 is the upper surface of the glass substrate 10.
  • the area of the auxiliary hole 203 is generally larger than the area 202 of the through hole.
  • the area of the auxiliary hole 203 may also be smaller than or equal to the area 202 of the through hole according to actual conditions.
  • the auxiliary hole 203 formed in the pixel unit 20 together with the through hole 202 is provided, and the addition of the non-functional auxiliary hole 203 is equivalent to the object of detecting the EPD mode etching method, thereby being effective.
  • the detection voltage change corresponding to the amplification detection data makes it possible to more accurately and reliably monitor the formation process of the through hole and ensure the quality of the through hole.
  • the present invention further provides a liquid crystal display device including a backlight module (not shown) and a liquid crystal panel as described in the above embodiments, the backlight module providing a light source for the liquid crystal panel.
  • the present invention also provides an embodiment of a method for fabricating an array substrate.
  • the first embodiment of the method for fabricating an array substrate of the present invention includes the following steps:
  • Step S401 forming a thin film transistor 200 as a part of the pixel unit 20 on the glass substrate 10, the pixel unit 20 being formed in the first region 100 of the glass substrate 10, the first region 100 corresponding to the minimum cutting panel unit of the glass substrate 10, At least two spaced-apart first regions 100 are defined on the glass substrate 10, and a region between the first regions 100 on the glass substrate 10 is defined as a second region 101, and a periphery other than all the first regions 100 on the glass substrate 10. The area is defined as the third area 102;
  • Step S402 forming a through hole 202 on the glass substrate 10 by using an EPD mode etching method, the through hole 202 electrically connecting the thin film transistor 200 and the pixel electrode 201 formed in a subsequent etching process, in the EPD mode etching process, simultaneously in the first region 100, an auxiliary hole 203 is formed in at least one of the second region 101 and the third region 102, and an etchant in a dry etching environment when the through hole 202 and the auxiliary hole 203 are formed by using a test method of an EPD mode etching method and The concentration of the generated product is detected to form detection data; after the detection data is formed, the detected data is converted into a detection voltage.
  • FIG. 6 is a flowchart of a second embodiment of a method for fabricating an array substrate according to the present invention.
  • the steps described in FIG. 4 may specifically include the following steps. Several substeps:
  • step S601 a thin film transistor 200 as a part of the pixel unit 20 is formed on the glass substrate 10.
  • the glass substrate 10 includes a first region 100, a second region 101, and a third region 102.
  • the number of liquid crystal panels corresponding to the glass substrate 10 can be exposed one or more at a time.
  • a plurality of pixel units 20 are included on the array substrate 1 corresponding to each liquid crystal panel to achieve the purpose of display.
  • Step S602 forming a through hole 202 for electrically connecting the thin film transistor 200 and the pixel electrode 201 on the pixel electrode 201 by using an EPD mode etching method, while forming an auxiliary hole 203 in the second region 101, the third region 102, and the pixel unit 20. .
  • Each of the pixel units 20 includes a thin film transistor 200, a pixel electrode 201, and a through hole 202.
  • the thin film transistor 200 serves as a switch of the pixel unit 20, and controls whether or not the pixel electrode 201 generates an electric field and generates an electric field.
  • the through hole 202 functions to electrically connect the thin film transistor 200 and the pixel electrode 201.
  • the pixel unit 20 of the panel 103 is formed with an auxiliary hole 203.
  • the auxiliary hole 203 and the through hole 202 are simultaneously formed in the glass substrate 10 by an EPD mode etching method.
  • the auxiliary hole 203 is formed on the glass substrate 10 at a position corresponding to the black matrix 30 of the color filter substrate 2; in addition, when the auxiliary hole 203 is formed, the auxiliary hole 203 is adjacent to the pixel electrode 201.
  • One end is provided, for example, the position of the auxiliary hole 203 adjacent to the data line of the pixel electrode 201.
  • the auxiliary hole 203 is disposed at a relatively small position of the second region 101 or the third region 102.
  • the black matrix 30 can be shielded from the auxiliary holes 203 to prevent the auxiliary holes 203 from affecting the display quality of the pixel unit 20.
  • the number of the auxiliary holes 203 provided in the pixel unit 20 is one.
  • the auxiliary holes 203 can also be set to multiple according to actual conditions, and the number of the auxiliary holes 203 is increased to increase the detection voltage 300 signal.
  • the second area 101 is located between the two first areas 100.
  • the second area 101 may be provided with a test electronic circuit as needed, or may be provided without a test electronic circuit as needed.
  • the auxiliary hole 203 is also formed in the second region 101.
  • the auxiliary hole 203 is provided in a place where the test electronic circuit is sparse to prevent the influence and destruction of the auxiliary hole 203 on the test line.
  • the number of the auxiliary holes 203 may be plural in the second region 101, and increasing the number of the auxiliary holes 203 may increase the detection voltage 300 signal.
  • a peripheral region other than all of the first regions 100 of the glass substrate 10 is formed as the third region 102.
  • the third region 102 may also be provided with test electronic circuits as needed.
  • the auxiliary holes 203 may be disposed in a place where the test electronic circuits are sparse to prevent the influence and destruction of the auxiliary holes 203 on the test lines.
  • the number of the auxiliary holes 203 may be set in the third region 102. Increasing the number of the auxiliary holes 203 may increase the detection voltage 300 signal.
  • the glass substrate 10 can be defined to include a fourth region in which only an insulating layer is present and a remaining fifth region.
  • the second region 101, the third region 102, and the auxiliary holes 203 provided in the pixel unit 20 may be disposed in the fourth region. In order to prevent the influence and destruction of the auxiliary hole 203 on the display quality of the circuit and the pixel unit 20 in the liquid crystal panel 103.
  • the auxiliary hole 203 may be simultaneously disposed in the second area 101, the third area 102, and the pixel unit 20, or may be provided in one of the second area 101, the third area 102, or the first area 100 or any two places or more
  • the hole 203 is used for the purpose of increasing the intensity of the detection voltage 300.
  • the area of each of the auxiliary holes 203 may be made larger than the area of the through holes 202 to more effectively change the concentration of the etchant and the reaction product.
  • step S603 when the auxiliary hole 203 on the glass substrate 10 is formed, the concentration of the etchant and the product in the dry etching environment when the through hole 202 and the auxiliary hole 203 are formed is detected by the test method for detecting the etching end point mode. Form detection data.
  • the detection data can reflect the concentration of the etchant and the product to facilitate a more realistic and objective reflection of the formation of the through hole 202 and the auxiliary hole 203.
  • step S604 after the detection data is formed, the detection data is converted into the detection voltage 300.
  • the detection voltage 300 can intuitively reflect the process of forming the through holes 202 and the auxiliary holes 203.
  • FIG. 7 is a diagram showing relationship between the detection voltage 300 and the dry etching time in the prior art using the EPD mode etching method
  • FIG. 8 is an EPD mode etching method in the embodiment of the method for fabricating the array substrate of the present invention.
  • the method of detecting the voltage 300' and the dry etching time is shown in conjunction with FIG. 5.
  • the intensity of the detection voltage 300' signal is much greater than the second region 101, the third The detection voltage 300 when the auxiliary hole is not provided in the area 102 and the pixel.
  • the voltage change after the detection data is converted into the reference voltage by the EPD mode etching method is used.
  • the amount is small, and the voltage does not reflect the change in the product and the concentration of the reactant in the vacuum dry etching environment, which makes the fabrication quality of the through hole 202 difficult to ensure.
  • the embodiment of the present invention designs the auxiliary hole 203 which is formed simultaneously with the through hole 202, that is, when the auxiliary hole 203 is disposed in the second region 101, the third region 102, and/or the pixel unit 20, resulting in the total of the through hole 202 and the auxiliary hole 203.
  • the number is getting bigger. As the total number of the through holes 202 and the auxiliary holes 203 becomes larger, the concentration of the etching liquid and the reaction product after the etching is completed will also become large during the dry etching.
  • the EPD mode etching method can convert the detected data of the concentration change into the detection voltage 300', thereby enhancing the intensity of the detection voltage 300', thereby facilitating more intuitive, accurate and reliable monitoring of the formation process of the through hole 202.
  • the auxiliary hole 203 formed in the pixel unit 20 together with the through hole 202, by adding the non-functional auxiliary hole 203, it is equivalent to increasing the detection object of the EPD mode etching method. Furthermore, the detection voltage change corresponding to the detection data can be effectively amplified, so that the formation process of the through hole can be monitored more accurately and reliably, and the quality of the through hole can be ensured.

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Abstract

一种液晶面板、液晶显示装置及其阵列基板的制作方法，所述液晶面板包括间隔设置的彩色滤光基板（2）和阵列基板（1）；阵列基板（1）邻近彩色滤光基板（2）的表面设置有若干像素单元（20），像素单元（20）包括薄膜晶体管（200）、像素电极（201）以及电连接薄膜晶体管（200）和像素电极（201）的贯穿孔（202）；像素单元（20）之间或像素单元（20）内设置至少一个与贯穿孔（202）一同采用侦测蚀刻终点模式蚀刻法形成的辅助孔（203），通过上述方式，能够放大侦测电压进而可以更加精确可靠地监测贯穿孔（202）的形成过程，保证贯穿孔（202）的制作质量。

Description

一种液晶面板、液晶显示装置及其阵列基板的制作方法
【技术领域】
本发明涉及显示技术领域，特别是涉及一种液晶面板、液晶显示装置及其阵列基板的制作方法。
【背景技术】
目前，液晶显示器日益成为市场上显示产品的主流，液晶面板是液晶显示器的主要组成部分。在液晶面板的工艺制程中，需要在阵列基板上依次形成栅极金属层、有源层、源极金属层、贯穿孔（VIA）以及像素电极层。
在连接薄膜晶体管的源极与像素电极的贯穿孔的制程中，是通过刻蚀方法形成贯穿孔。而刻蚀形成贯穿孔的时间控制对制作精度的影响较大，现有技术采用预先给出一定刻蚀时间的方式来形成贯穿孔。
但是贯穿孔形成所需要的真实蚀刻时间，受前期制程得到的膜厚影响。前期制程的膜厚难以控制，进而使得贯穿孔形成所需要的真实蚀刻时间难以预定精确。在这种情况下，就存在预先给出的刻蚀时间过短或过长的问题。
【发明内容】
本发明主要解决的技术问题是提供一种液晶面板、液晶显示装置及其阵列基板的制作方法，能够在侦测蚀刻终点（End Point Detector mode，EPD）技术中，放大侦测电压进而可以更加精确可靠地监测贯穿孔的形成过程，保证贯穿孔的制作质量。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种液晶面板，其中，液晶面板包括间隔设置的彩色滤光基板和阵列基板，阵列基板是像素分割垂直配向液晶显示器的阵列基板；阵列基板邻近彩色滤光基板的表面设置有若干像素单元，像素单元包括薄膜晶体管、像素电极以及电连接薄膜晶体管和像素电极的贯穿孔；其中，像素单元之间或像素单元内设置至少一个与贯穿孔一同采用侦测蚀刻终点模式蚀刻法形成的辅助孔，辅助孔邻近像素电极的一端设置；并且，彩色滤光基板邻近阵列基板的表面设置有黑色矩阵，黑色矩阵遮挡辅助孔。
其中，辅助孔的面积大于贯穿孔的面积。
其中，辅助孔邻近像素电极的数据线的位置设置。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示装置，液晶显示装置包括液晶面板和背光模组，其中：液晶面板包括间隔设置的彩色滤光基板和阵列基板；阵列基板邻近彩色滤光基板的表面设置有若干像素单元，像素单元包括薄膜晶体管、像素电极以及电连接薄膜晶体管和像素电极的贯穿孔；其中，像素单元之间或像素单元内设置至少一个与贯穿孔一同采用侦测蚀刻终点模式蚀刻法形成的辅助孔。
其中，彩色滤光基板邻近阵列基板的表面设置有黑色矩阵，黑色矩阵遮挡辅助孔。
其中，阵列基板是像素分割垂直配向液晶显示器的阵列基板，辅助孔邻近像素电极的一端设置。
其中，辅助孔邻近像素电极的数据线的位置设置。
其中，辅助孔的面积大于贯穿孔的面积。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板的制作方法，其中，包括：在玻璃基板上形成作为像素单元一部分的薄膜晶体管，像素单元形成于玻璃基板的第一区域内，第一区域对应于玻璃基板的最小切割面板单元，玻璃基板上定义有至少两个间隔设置的第一区域，玻璃基板上的第一区域之间区域定义为第二区域，玻璃基板上的所有第一区域之外的周边区域定义为第三区域； 采用侦测蚀刻终点模式蚀刻法在玻璃基板上形成贯穿孔，贯穿孔电连接薄膜晶体管和后续蚀刻制程中所形成的像素电极，在侦测蚀刻终点模式蚀刻过程中，同时在第一区域、第二区域和第三区域中的至少一区域内形成辅助孔，并且利用侦测蚀刻终点模式的测试方法对形成贯穿孔和辅助孔时的干蚀刻环境中的蚀刻剂以及生成物的浓度进行侦测，形成侦测数据；在形成侦测数据之后，将侦测数据转变为侦测电压。
其中，形成辅助孔的步骤，包括：将辅助孔形成于玻璃基板上对应彩色滤光基板的黑色矩阵的位置。
其中，形成辅助孔的步骤包括：形成辅助孔，并使得辅助孔邻近像素电极的一端设置。
其中，形成辅助孔的步骤包括：将辅助孔邻近像素电极的数据线的位置设置。
其中，形成辅助孔的步骤包括：将辅助孔设置于第二区域或第三区域的电子线路相对较少的位置。
其中，阵列基板上包括只存在绝缘层的第四区域和剩余的第五区域，形成辅助孔的步骤包括：将辅助孔设置于第四区域。
其中，形成辅助孔的步骤包括：形成辅助孔，并使得辅助孔的面积大于贯穿孔的面积。
本发明的有益效果是：区别于现有技术的情况，本发明在像素单元内设置与贯穿孔一同形成的辅助孔，通过增设无功能的辅助孔的方式，等同于增加了EPD模式蚀刻法的侦测的对象，进而可以有效放大侦测数据对应的侦测电压变化，使得可以更加精确可靠地监测贯穿孔的形成过程，保证贯穿孔的制作质量。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图，其中：
图1是本发明液晶面板实施例的截面示意图；
图2是本发明如图1所示一个像素单元的平面示意图；
图3是图2所示辅助孔的沿AB方向的截面示意图；
图4是本发明阵列基板的制作方法第一实施例的流程图；
图5是图4所示辅助孔形成步骤中所产生阵列基板的平面示意图；
图6是本发明阵列基板的制作方法第二实施例的流程图
图7是现有技术中使用EPD模式蚀刻法的侦测电压与干刻蚀时间关系图；
图8是本发明阵列基板制作方法实施例中使用EPD模式蚀刻法的侦测电压与干刻蚀时间关系图。
【具体实施方式】
下面，对本发明阵列基板及其测试方法实施例进行具体描述，以更清楚公开本发明的细节和精神。
请参阅图1和图2，液晶面板实施例包括阵列基板1和彩色滤光基板2。其中，阵列基板1包括玻璃基板10和像素单元20，彩色滤光基板2包括黑色矩阵30和玻璃基板40。
该阵列基板1和彩色滤光基板2间隔设置，玻璃基板10邻近彩色滤光基板2的表面设置有若干像素单元20，像素单元20可以为矩阵排列。
像素单元20包括薄膜晶体管200、像素电极201以及电连接薄膜晶体管200和像素电极201的贯穿孔202。其中，像素单元20内设置至少一个与贯穿孔202一同采用EPD模式蚀刻法形成的辅助孔203。在一应用例中，该黑色矩阵30设置于彩色滤光基板2邻近阵列基板1的表面，该黑色矩阵30遮挡辅助孔203，使其不影响像素单元20的显示区域。当然，也可以另外设计使黑色矩阵30不遮挡辅助孔203。
阵列基板1是像素分割垂直配向液晶显示器的阵列基板，辅助孔203邻近像素电极201的一端设置，比如辅助孔203邻近像素电极201的数据线的位置设置。
请参阅图3，图3是图2所示辅助孔的沿AB方向的截面示意图。辅助孔203的形成与贯穿孔202的形成同步进行，对玻璃基板10上的膜层进行蚀刻，直至蚀刻到玻璃基板10表面。例如，将玻璃基板10表面的绝缘层1001以及保护层1002蚀刻出辅助孔203，辅助孔203的孔底即为玻璃基板10的上表面。值得注意的是，在实际应用中，辅助孔203的面积一般大于贯穿孔的面积202，当然，根据实际情况，辅助孔203的面积也可以小于或等于贯穿孔的面积202。
本发明实施例，在像素单元20内设置与贯穿孔202一同形成的辅助孔203，通过增设无功能的辅助孔203的方式，等同于增加了EPD模式蚀刻法的侦测的对象，进而可以有效放大侦测数据对应的侦测电压变化，使得可以更加精确可靠地监测贯穿孔的形成过程，保证贯穿孔的制作质量。
此外，本发明还提供一种液晶显示装置，所述液晶显示装置包括背光模组（图未示）和如上述实施例所述的液晶面板，该背光模组为液晶面板提供光源。
本发明还提供一种阵列基板的制作方法实施例，如图4所示，并请结合图1、图2和图5，本发明阵列基板的制作方法第一实施例包括如下步骤：
步骤S401，在玻璃基板10上形成作为像素单元20一部分的薄膜晶体管200，像素单元20形成于玻璃基板10的第一区域内100，该第一区域100对应于玻璃基板10的最小切割面板单元，玻璃基板10上定义有至少两个间隔设置的第一区域100，玻璃基板10上的第一区域100之间区域定义为第二区域101，玻璃基板10上的所有第一区域100之外的周边区域定义为第三区域102；
步骤S402，采用EPD模式蚀刻法在玻璃基板10上形成贯穿孔202，该贯穿孔202电连接薄膜晶体管200和后续蚀刻制程中形成的像素电极201，在EPD模式蚀刻过程中，同时在第一区域100、第二区域101和第三区域102中的至少一区域内形成辅助孔203，并且利用EPD模式蚀刻法的测试方法对形成贯穿孔202和辅助孔203时的干蚀刻环境中的蚀刻剂以及生成物的浓度进行侦测，形成侦测数据；在形成侦测数据之后，将侦测数据转变为侦测电压。
具体而言，参阅图6，图6是本发明阵列基板的制作方法第二实施例的流程图，并请结合图1、图2和图5，上述如图4所述的步骤可以具体包括以下几个子步骤：
步骤S601，在玻璃基板10上形成作为像素单元20一部分的薄膜晶体管200。
该玻璃基板10包括：第一区域100、第二区域101以及第三区域102。
在玻璃基板10上一次可以曝光所对应的液晶面板个数为一个或者多个。形成阵列基板1后，对应每个液晶面板的阵列基板1上包括若干个像素单元20，以实现显示的目的。
步骤S602：采用EPD模式蚀刻法在像素电极201上形成用于电连接薄膜晶体管200和像素电极201的贯穿孔202，同时在第二区域101、第三区域102和像素单元20内形成辅助孔203。
每个像素单元20包括薄膜晶体管200、像素电极201以及贯穿孔202。薄膜晶体管200作为像素单元20的开关，控制像素电极201是否产生电场、如何产生电场。贯穿孔202的作用为电连接薄膜晶体管200和像素电极201。在面板103的像素单元20中除了形成贯穿孔202外，还形成有辅助孔203。辅助孔203与贯穿孔202同时采用EPD模式蚀刻法形成在玻璃基板10中。
同时，在步骤S602中，还包括：将辅助孔203形成于玻璃基板10上对应彩色滤光基板2的黑色矩阵30的位置；另外，在形成辅助孔203时，该辅助孔203邻近像素电极201的一端设置，比如，将辅助孔203邻近像素电极201的数据线的位置设置。在一应用实施例中，将该辅助孔203设置于第二区域101或第三区域102的电子线路相对较少的位置。
采用该方法形成的结构，可以使得黑色矩阵30遮挡辅助孔203以防止辅助孔203对像素单元20的显示品质产生影响。
辅助孔203在像素单元20中设置的数量为一个。当然，辅助孔203也可以根据实际情况设置为多个，增加辅助孔203的数量以提高侦测电压300信号。
第二区域101位于所述两个第一区域100之间。第二区域101可以根据需要设置测试用电子线路，也可以根据需要不设置测试用电子线路。当第二区域101没有设置测试用电子线路时，在第二区域101同样形成有辅助孔203。当第二区域101设置有测试用电子线路时，辅助孔203设置在测试用电子线路较为稀疏的地方以防止辅助孔203对测试用线路的影响与破坏。
辅助孔203在第二区域101设置的数量可以为多个，增加辅助孔203的数量可以提高侦测电压300信号。
玻璃基板10的所有第一区域100之外的周边区域形成为第三区域102。第三区域102也可以根据需要设置测试用电子线路，进一步地也可以将辅助孔203设置在测试用电子线路较为稀疏的地方，以防止辅助孔203对测试用线路的影响与破坏。
辅助孔203在第三区域102设置的数量可以为多个，增加辅助孔203的数量可以提高侦测电压300信号。
从另一方面看，玻璃基板10可以定义为包括只存在绝缘层的第四区域和剩余的第五区域。在一应用实施例中，可以将第二区域101、第三区域102以及像素单元20中设置的辅助孔203均设置在第四区域。以防止辅助孔203对液晶面板103中电路以及像素单元20显示质量的影响与破坏。
第二区域101、第三区域102以及像素单元20中可以同时设置辅助孔203，也可以在第二区域101、第三区域102或第一区域100中的一个地方或者任意两个地方以上设置辅助孔203，以实现提高侦测电压300强度的目的。
在一应用实施例中，在形成辅助孔203时，使得每个辅助孔203的面积可以比贯穿孔202的面积都大，以更有效改变刻蚀剂以及反应生成物的浓度。
步骤S603，在形成玻璃基板10上的辅助孔203时，利用侦测蚀刻终点模式的测试方法对形成贯穿孔202和辅助孔203时的干蚀刻环境中蚀刻剂以及生成物的浓度进行侦测，形成侦测数据。
侦测数据可以反映蚀刻剂以及生成物的浓度，以利于更真实客观的反映贯穿孔202和辅助孔203形成的过程。
步骤S604，在形成侦测数据之后，将侦测数据转变为侦测电压300。
侦测电压300可以直观的反映贯穿孔202和辅助孔203形成的过程。
如图7和图8所示，图7为现有技术中使用EPD模式蚀刻法的侦测电压300与干刻蚀时间关系图，图8为本发明阵列基板制作方法实施例中使用EPD模式蚀刻法的侦测电压300’与干刻蚀时间关系图，并请结合图5。从图中可以看到，当第二区域101、第三区域102以及像素单元20中任何一个或以上设置辅助孔203时，侦测电压300’信号的强度远远大于第二区域101、第三区域102以及像素中没有设置辅助孔时的侦测电压300。
可以理解，在薄膜晶体管的工艺制程中，因为贯穿孔202的数量有限，并且每个贯穿孔202的面积很小，因此，使用EPD模式蚀刻法将侦测数据转变为参考电压的后的电压变化量很小，该电压不能很好地反映真空干刻蚀环境中生成物以及反应物浓度变化，导致贯穿孔202的制作质量难以保证。本发明实施例设计与贯穿孔202同时制作的辅助孔203，即在第二区域101、第三区域102和/或像素单元20中设置辅助孔203时，导致贯穿孔202和辅助孔203的总体数量变大。随着贯穿孔202和辅助孔203的总体数量变大，在干刻蚀的过程中刻蚀液以及刻蚀完成后的反应生成物的浓度也将变大。EPD模式蚀刻法可以将浓度变化的侦测数据转化为侦测电压300’，进而可以加强侦测电压300’的强度，以利于更加直观精确可靠地监测贯穿孔202的形成过程。
综上，本发明实施例通过在像素单元20内设置与贯穿孔202一同形成的辅助孔203，通过增设无功能的辅助孔203的方式，等同于增加了EPD模式蚀刻法的侦测的对象，进而可以有效放大侦测数据对应的侦测电压变化，使得可以更加精确可靠地监测贯穿孔的形成过程，保证贯穿孔的制作质量。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种液晶面板，其中：
    所述液晶面板包括间隔设置的彩色滤光基板和阵列基板，所述阵列基板是像素分割垂直配向液晶显示器的阵列基板；
    所述阵列基板邻近彩色滤光基板的表面设置有若干像素单元，所述像素单元包括薄膜晶体管、像素电极以及电连接薄膜晶体管和像素电极的贯穿孔；
    其中，所述像素单元之间或像素单元内设置至少一个与贯穿孔一同采用侦测蚀刻终点模式蚀刻法形成的辅助孔，所述辅助孔邻近像素电极的一端设置；
    并且，所述彩色滤光基板邻近阵列基板的表面设置有黑色矩阵，所述黑色矩阵遮挡辅助孔。
  2. 根据权利要求1所述的液晶面板，其中，
    所述辅助孔的面积大于贯穿孔的面积。
  3. 根据权利要求1所述的液晶面板，其中，
    所述辅助孔邻近像素电极的数据线的位置设置。
  4. 一种液晶显示装置，所述液晶显示装置包括液晶面板和背光模组，所述背光模组为液晶面板提供光源，其中：
    所述液晶面板包括间隔设置的彩色滤光基板和阵列基板；
    所述阵列基板邻近彩色滤光基板的表面设置有若干像素单元，所述像素单元包括薄膜晶体管、像素电极以及电连接薄膜晶体管和像素电极的贯穿孔；
    其中，所述像素单元之间或像素单元内设置至少一个与贯穿孔一同采用侦测蚀刻终点模式蚀刻法形成的辅助孔。
  5. 根据权利要求4所述的液晶显示装置，其中：
    所述彩色滤光基板邻近阵列基板的表面设置有黑色矩阵，所述黑色矩阵遮挡辅助孔。
  6. 根据权利要求4所述的液晶显示装置，其中：
    所述阵列基板是像素分割垂直配向液晶显示器的阵列基板，所述辅助孔邻近像素电极的一端设置。
  7. 根据权利要求6所述的液晶显示装置，其中：
    所述辅助孔邻近像素电极的数据线的位置设置。
  8. 根据权利要求4所述的液晶显示装置，其中：
    所述辅助孔的面积大于贯穿孔的面积。
  9. 一种阵列基板的制作方法，其中，包括：
    在玻璃基板上形成作为像素单元一部分的薄膜晶体管，所述像素单元形成于玻璃基板的第一区域内，所述第一区域对应于玻璃基板的最小切割面板单元，所述玻璃基板上定义有至少两个间隔设置的第一区域，所述玻璃基板上的第一区域之间区域定义为第二区域，所述玻璃基板上的所有第一区域之外的周边区域定义为第三区域；
    采用侦测蚀刻终点模式蚀刻法在所述玻璃基板上形成贯穿孔，所述贯穿孔电连接薄膜晶体管和后续蚀刻制程中所形成的像素电极，在所述侦测蚀刻终点模式蚀刻过程中，同时在所述第一区域、第二区域和第三区域中的至少一区域内形成辅助孔，并且利用侦测蚀刻终点模式的测试方法对形成贯穿孔和辅助孔时的干蚀刻环境中的蚀刻剂以及生成物的浓度进行侦测，形成侦测数据；在形成侦测数据之后，将所述侦测数据转变为侦测电压。
  10. 根据权利要求9所述的方法，其中：
    所述形成辅助孔的步骤，包括：将所述辅助孔形成于玻璃基板上对应彩色滤光基板的黑色矩阵的位置。
  11. 根据权利要求9所述的方法，其中：
    所述形成辅助孔的步骤包括：形成所述辅助孔，并使得所述辅助孔邻近像素电极的一端设置。
  12. 根据权利要求11所述的方法，其中：
    所述形成辅助孔的步骤包括：将所述辅助孔邻近像素电极的数据线的位置设置。
  13. 根据权利要求9所述的方法，其中：
    所述形成辅助孔的步骤包括：将所述辅助孔设置于第二区域或第三区域的电子线路相对较少的位置。
  14. 根据权利要求13所述的方法，其中：
    所述阵列基板上包括只存在绝缘层的第四区域和剩余的第五区域，所述形成辅助孔的步骤包括：将所述辅助孔设置于第四区域。
  15. 根据权利要求9所述的方法，其中：
    所述形成辅助孔的步骤包括：形成辅助孔，并使得所述辅助孔的面积大于贯穿孔的面积。
PCT/CN2012/075424 2012-04-20 2012-05-14 一种液晶面板、液晶显示装置及其阵列基板的制作方法 WO2013155746A1 (zh)

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