WO2013149463A1 - 导电结构及制造方法、薄膜晶体管、阵列基板和显示装置 - Google Patents

导电结构及制造方法、薄膜晶体管、阵列基板和显示装置 Download PDF

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WO2013149463A1
WO2013149463A1 PCT/CN2012/083106 CN2012083106W WO2013149463A1 WO 2013149463 A1 WO2013149463 A1 WO 2013149463A1 CN 2012083106 W CN2012083106 W CN 2012083106W WO 2013149463 A1 WO2013149463 A1 WO 2013149463A1
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Prior art keywords
layer
copper
conductive structure
diffusion
barrier layer
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PCT/CN2012/083106
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English (en)
French (fr)
Inventor
郑在纹
黄秋平
林盛实
金童燮
徐朝焕
徐华伟
陈正伟
薛建设
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US13/877,745 priority Critical patent/US9553158B2/en
Publication of WO2013149463A1 publication Critical patent/WO2013149463A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4421—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12771—Transition metal-base component
    • Y10T428/12806—Refractory [Group IVB, VB, or VIB] metal-base component
    • Y10T428/12826—Group VIB metal-base component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/26—Web or sheet containing structurally defined element or component, the element or component having a specified physical dimension
    • Y10T428/263—Coating layer not in excess of 5 mils thick or equivalent
    • Y10T428/264—Up to 3 mils
    • Y10T428/265—1 mil or less
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/31504—Composite [nonstructural laminate]
    • Y10T428/31678—Of metal

Definitions

  • Embodiments of the present invention relate to a conductive structure and a method of fabricating the same, a thin film transistor, an array substrate, and a display device. Background technique
  • Thin film transistor (TFT) array substrates can be used in liquid crystal displays (LCDs) and organic light emitting displays (OLEDs).
  • a liquid crystal display generally includes a thin film transistor array substrate and a color filter film substrate, and a liquid crystal layer disposed between the two substrates. When an electric field is applied between the two substrates, the alignment of the liquid crystal molecules is changed, so that the transmittance of the light can be changed for display.
  • Organic light-emitting displays display images by using organic electroluminescent materials.
  • the pixels of an organic light emitting display typically include a driving thin film transistor that supplies current to the organic electroluminescent material and a switching thin film transistor that controls the driving of the thin film transistor to be turned on or off.
  • These display devices may include gate lines and data lines to drive the pixel cells.
  • gate and data lines are required to have lower resistance.
  • the mainstream aluminum wiring has been unable to meet the display performance requirements due to the high resistivity.
  • the resistivity of copper is much lower than that of aluminum, so the use of copper as the gate line and data line will be the mainstream choice in the future.
  • copper ions have a strong permeability and are easily diffused into, for example, an amorphous silicon or silicon layer for an active layer of a thin film transistor.
  • copper ions generated during etching of the metal conductive layer or during the stripping of the photoresist may also penetrate into the amorphous silicon layer, thereby affecting the performance of the amorphous silicon layer (e.g., thin film transistor).
  • silicon ions and other metal ions are also easily diffused into the copper conductive structure, thereby increasing the resistivity of the copper conductive structure and reducing its chemical corrosion resistance. Summary of the invention
  • Embodiments of the present invention provide a conductive structure capable of preventing external ions from diffusing into the copper layer and outward diffusion of copper ions in the copper layer, thereby reducing adverse effects caused by ion diffusion.
  • an embodiment of the present invention provides a conductive structure, including: a copper layer formed of copper or a copper alloy; a barrier layer for blocking outward diffusion of copper ions of the copper layer; a diffusion preventing layer for blocking diffusion of external ions to the copper layer, the anti-diffusion layer being disposed at Between the copper layer and the barrier layer.
  • the material of the barrier layer is a molybdenum alloy
  • the material of the diffusion prevention layer is molybdenum
  • the molybdenum alloy is any one or a mixture of two or more of Mo b, MoW, MoTi, and MoZr.
  • the atomic percentage of the element other than Mo in the molybdenum alloy is between 0.001 ⁇ and 50 at%.
  • the barrier layer has a thickness of 50A to 1000A, and the anti-diffusion layer has a thickness of 30A to 200A.
  • the embodiment of the invention further provides a thin film transistor including a gate electrode, a source electrode and a drain electrode, and at least one of the gate electrode, the source electrode and the drain electrode uses the conductive structure described above.
  • an embodiment of the present invention further provides a thin film transistor array substrate, including: a substrate; a thin film transistor array, a gate line, and a data line formed on the substrate, wherein the thin film transistor array includes a plurality of thin film transistors including a gate electrode, a source electrode, and a drain electrode; a pixel electrode is further formed in a pixel region defined by the intersection of the gate line and the data line; wherein, the data At least one of the line, the source electrode, the gate line, the gate electrode, and the drain electrode uses the conductive structure described above.
  • Embodiments of the present invention also provide a display device including the thin film transistor array substrate described above.
  • Embodiments of the present invention also provide a method of fabricating a conductive structure, comprising: forming a barrier layer on a substrate for blocking diffusion of copper ions to the substrate; forming a barrier layer on the barrier layer An anti-diffusion layer of ions that diffuse upwardly from the barrier layer; a copper layer is formed on the anti-diffusion layer, and the material of the copper layer is copper or a copper alloy.
  • the molybdenum alloy is further used as a sputtering source, and the barrier layer is formed by a sputtering process; further, molybdenum is used as a sputtering source, and the anti-diffusion layer is formed by a sputtering process;
  • the copper layer is formed by a sputtering process using copper or a copper alloy as a sputtering source.
  • the material of the molybdenum alloy is any one or a mixture of two or more of Mo b, MoW, MoTi, and MoZr.
  • the conductive structure and the manufacturing method thereof provided by the embodiments of the present invention, wherein the conductive structure has a multi-layer structure, and the multi-layer structure is used to prevent external ions from diffusing into the copper layer and outward diffusion of copper ions in the copper layer, thereby reducing ion diffusion.
  • the barrier layer in the conductive structure has good adhesion to a substrate or a semiconductor layer such as a glass substrate The ability to improve the adhesion stability of the conductive structure; and, each layer of the multilayer conductive structure has similar etch selectivity, which facilitates etching/patterning of the multilayer conductive structure.
  • the thin film transistor, the array substrate, and the display device provided by the embodiments of the present invention have the above-mentioned advantageous effects because the above-described conductive structure is used.
  • FIG. 1 is a schematic structural view of a conductive structure according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a thin film transistor array substrate according to an embodiment of the present invention.
  • Reference numeral 1 is a schematic structural diagram of a thin film transistor array substrate according to an embodiment of the present invention.
  • 1 a substrate; 2a - barrier layer; 2b - anti-diffusion layer;
  • 2c copper layer
  • 5 gate
  • 6 gate insulating layer
  • a protective layer 11 one pixel electrode; 12-via;
  • a substrate substrate A substrate substrate. detailed description
  • Embodiments of the present invention discard the use of copper conductive structures alone due to the easy diffusion characteristics of copper ions Instead, multiple layers of conductive structures are used to reduce or avoid the outward diffusion of copper ions from the copper layer and to reduce or avoid the diffusion of external ions into the copper layer. Moreover, the multilayer conductive structure of the embodiment of the present invention can overcome the problem that the conventional copper conductive structure has low adhesion to an insulating substrate (for example, a glass substrate or a semiconductor layer) and is likely to fall off of the film.
  • an insulating substrate for example, a glass substrate or a semiconductor layer
  • One embodiment of the present invention provides a multilayered electrically conductive structure that can be reliably patterned when patterned to form a good side profile.
  • the conductive structure comprises: a copper layer 2c formed of copper or a copper alloy; a barrier layer 2a for blocking outward diffusion of copper ions of the copper layer 2c; and blocking diffusion of external ions to the
  • the diffusion prevention layer 2b of the copper layer 2c, the diffusion prevention layer 2b is disposed between the copper layer 2c and the barrier layer 2a.
  • the barrier layer 2a may be formed on a substrate 1.
  • the substrate 1 may be a substrate such as a glass substrate, a quartz substrate, or a plastic substrate, or may be one or a plurality of film layers on the electronic component, such as a gate insulating layer of a thin film transistor, a semiconductor layer, a passivation layer, or the like. Other intermediate film layers such as a buffer layer may also be formed between the substrate 1 and the barrier layer 2a.
  • the substrate 1 may have a single layer structure or a structure of two or more layers. Moreover, the substrate 1 can simultaneously contain different regions of the electronic device.
  • the barrier layer 2a can be simultaneously formed on the active layer and the gate insulating layer ( That is, at this time, the active layer and the gate insulating layer simultaneously constitute the substrate 1).
  • the thickness of each layer is determined by the required interface condition and etching condition.
  • the barrier layer 2a may have a thickness of 50A to 1000A
  • the diffusion prevention layer 2b may have a thickness of 30A to 200A
  • the copper layer 2c may have a thickness of 1000A to 5000A.
  • the anti-diffusion layer 2b can block external ions (such as ions in the barrier layer 2a or ions in the substrate 1) from diffusing into the copper layer 2c to ensure the electrical conductivity and chemical corrosion resistance of the copper layer;
  • the copper ions in the copper layer 2c will also be blocked by the barrier layer 2a, and it is difficult to diffuse into the substrate 1, so that the influence on the substrate 1 can be reduced or avoided.
  • the material of the barrier layer 2a is a molybdenum alloy.
  • the molybdenum alloy may be any one of MoNb, MoW, MoTi, and MoZr, or may be a mixture of two or more of the above various types.
  • the barrier layer 2a of the molybdenum alloy and the substrate 1 (such as a base substrate or a semiconductor layer) Good adhesion, which can enhance adhesion between the substrate 1 and the conductive structure, thereby improving the stability of bonding between the conductive structure and the substrate 1; the barrier layer 2a can also prevent copper ions from diffusing into the substrate 1 and present Etching selectivity similar to that of the diffusion prevention layer 2b and the copper layer 2c is facilitated to simultaneously etch them in the etching/patterning process of the multilayer structure.
  • the atomic percentage of the element other than Mo in the molybdenum alloy is, for example, between 0.001 & 1% and 50 at%.
  • the molybdenum alloy is MoNb
  • the atomic percentage of Nb in the molybdenum alloy is between 0.001 at% and 50 at%;
  • the molybdenum alloy is made of MoNb and MoTi, both b and Ti in the molybdenum alloy
  • the sum of the atomic percentages is between 0. OOlat % and 50 at %.
  • the above structure deposits a diffusion preventing layer 2b between the barrier layer 2a and the copper layer 2c.
  • the diffusion prevention layer 2b has a crystal structure material similar to the barrier layer 2a and the copper layer 2c, and can ensure the interface between the barrier layer 2a and the diffusion prevention layer 2b and the interface between the diffusion prevention layer 2b and the copper layer 2c. It also has an etching selectivity similar to that of the barrier layer 2a and the copper layer 2c.
  • the diffusion-proof material is molybdenum (Mo)
  • molybdenum (Mo) is a body-centered cubic crystal structure, and has a similar crystal structure with a molybdenum alloy (for example, MoNb), and copper having a face-centered cubic crystal structure belongs to a cubic crystal system. , thus ensuring good interface performance.
  • the conductive structure formed by the above method has good interfacial properties and etching properties; the multilayered conductive structure can be reliably patterned to form a good side profile when patterned.
  • the diffusion preventing layer 2b can also prevent metal ions in the other layers in contact with the barrier layer from diffusing into the copper layer 2c.
  • the conductive structure of the embodiment can reduce or avoid corrosion and oxidation by the copper layer 2c, and can closely adhere to the substrate while effectively overcoming the electrical properties of the copper layer caused by diffusion of metal ions or other impurities to the copper layer and The problem of chemical corrosion resistance is reduced.
  • the present embodiment also provides a method of manufacturing the conductive structure shown in Fig. 1, the method comprising the following steps.
  • a barrier layer 2a for blocking diffusion of copper ions to the substrate is formed on the substrate 1.
  • a diffusion prevention layer 2b is formed on the barrier layer 2a, and the diffusion prevention layer 2b is used for The ions diffused upward through the barrier layer are blocked; thereafter, a copper layer 2c is formed on the diffusion prevention layer 2b, and the material of the copper layer 2c is copper or a copper alloy.
  • the barrier layer 2a, the diffusion prevention layer 2b, and the copper layer 2c may each be formed by a sputtering process.
  • the barrier layer 2a is made of a molybdenum alloy as a sputtering source
  • the anti-diffusion layer 2b is made of molybdenum as a sputtering source
  • the copper layer 2c is made of copper or a copper alloy as a sputtering source.
  • the material of the molybdenum alloy may be, for example, any one or a mixture of two or more of MoNb, MoW, MoTi, and MoZr.
  • the above layers may also be formed by other methods, such as chemical vapor deposition or physical deposition, and are not described herein.
  • the present embodiment can further perform a patterning process on the above structure, such as photoresist coating, exposure development, and etching, to obtain a final desired pattern.
  • a patterning process such as photoresist coating, exposure development, and etching
  • an embodiment of the present invention further provides a thin film transistor, which may generally include a gate electrode, a source electrode, and a drain electrode, wherein at least one of the gate electrode, the source electrode, and the drain electrode is as described above Conductive structure.
  • the thin film transistor uses other portions than the above-described conductive structure and the entire structure of the thin film transistor, and the present invention is not limited.
  • the embodiment of the present invention further provides a thin film transistor array substrate, which generally includes: a substrate; a thin film transistor array, a gate line, and a data line formed on the substrate, the thin film transistor array including a plurality of thin films a transistor, the thin film transistor includes a gate electrode, a source electrode, and a drain electrode; a pixel electrode is further formed in a pixel region defined by the intersection of the gate line and the data line; wherein, on the array substrate, At least one of the data line, the source electrode, the gate line, the gate electrode, and the drain electrode uses the conductive structure described above. For example, the gate line is connected to a corresponding gate electrode, the data line is connected to a corresponding source electrode, and the pixel electrode is connected to a corresponding drain electrode.
  • the gate line and the gate electrode constitute a gate conductive structure
  • the data line, the source electrode and the drain electrode constitute a data conductive structure.
  • a gate line is formed on the substrate and extends in the first direction
  • the data line is formed over the gate insulating layer and extends in the second direction.
  • the first direction may be perpendicular to the second direction.
  • the drain electrode is spaced apart from the source electrode.
  • the pixel electrode is formed in a pixel region defined by the intersection of the gate line and the data line, and is electrically connected to the drain electrode.
  • any of the gate conductive structure and the data conductive structure such as a gate electrode, a gate line or a drain electrode, may use the conductive structure shown in FIG.
  • a thin film transistor array substrate according to an embodiment of the present invention will be described in more detail below with reference to FIG.
  • the array substrate shown in FIG. 2 can be applied to a liquid crystal display or an organic light emitting display, the array
  • the substrate includes a base substrate 13 and at least one gate conductive structure 5 disposed on the base substrate 13.
  • the gate conductive structure 5 includes a gate electrode and a gate line, and the gate electrode and/or the gate line may use the conductive structure shown in FIG. 1, that is, include a barrier layer, a diffusion prevention layer, and a copper layer.
  • the barrier layer is formed on the base substrate 13, and the barrier layer material may be a molybdenum alloy (for example, one or more of Mo b, MoW, MoTi, MoZr, etc.); Nb (or W, in the alloy)
  • the atomic percentage of Ti, Zr, etc. is, for example, in the range of 0.001 at% to 50 at%.
  • the thickness of the barrier layer is determined by the desired interface condition and etching conditions, and may be, for example, between 50A and 1000A.
  • the diffusion prevention layer is formed on the barrier layer, and the diffusion prevention layer material is molybdenum (Mo).
  • the thickness of the diffusion prevention layer is determined by the required interface condition and etching condition, and may be, for example, between 30A and 200A.
  • the copper layer is formed on the diffusion prevention layer, and the material may be copper metal or copper alloy.
  • the above-mentioned gate conductive structure composed of the barrier layer, the anti-diffusion layer and the copper layer can overcome the problem of poor adhesion between the copper wire and the substrate in the prior art, and the barrier layer composed of the molybdenum alloy can improve the copper layer.
  • Adhesion to the substrate, while preventing diffusion of copper ions to the substrate; and, the anti-diffusion layer material formed of molybdenum (Mo) material can prevent Nb (or W, Ti, Zr, etc.) The diffusion of ions into the copper layer, thereby preventing the problem of lowering the electrical properties and chemical corrosion resistance of the copper metal layer caused by the above ion diffusion, and ensuring the low resistance value characteristics of the copper metal layer.
  • the barrier layer, the anti-diffusion layer and the copper layer have similar etched characteristics during the etching process, so that the etching is easy to form a good pattern and the process cost is reduced.
  • the array substrate shown in FIG. 2 further includes a gate insulating layer 6 disposed on the base substrate 13, and the gate insulating layer 6 covers the gate conductive structure 5.
  • a channel element i.e., an active layer
  • the ohmic contact semiconductor layer 8 is disposed on the intrinsic semiconductor layer 7.
  • the active layer may also include an organic semiconductor, or a metal oxide semiconductor such as IGZO or the like.
  • the array substrate shown in FIG. 2 further includes at least one data conductive structure, and the data conductive structure is disposed on the channel element.
  • the data conductive structure includes a data line 9a, a source electrode 9b, and a drain electrode 9c.
  • the data line 9a is disposed on the gate insulating layer 6.
  • the source electrode 9b and the drain electrode 9c are disposed on the channel element, and the source electrode 9b is electrically connected to the data line 9a, and the drain electrode 9c is spaced apart from the source electrode 9b.
  • Any one or more of the data line 9a, the source electrode 9b, and the drain electrode 9c may employ the conductive structure shown in FIG. 1, that is, include a barrier layer, a diffusion prevention layer, and a copper layer.
  • the barrier layer is formed on the gate insulating layer 6 or the channel element, and the barrier layer material may be a molybdenum alloy (for example)
  • the barrier layer material may be a molybdenum alloy (for example)
  • the atomic percentage of Nb (or W, Ti, Zr, etc.) in the alloy is, for example, in the range of 0.001 1% to 50 1%.
  • the thickness of the barrier layer is determined by the desired interface conditions and etching conditions, for example, between 50A and 1000A.
  • the diffusion prevention layer is formed on the barrier layer, and the diffusion prevention layer material is molybdenum (Mo). The thickness of the diffusion prevention is determined by the required interface condition and etching condition, for example, between 30A and 200A.
  • the copper layer is formed on the diffusion prevention layer, and the material may be a copper metal layer or a copper alloy layer.
  • the above-mentioned data conductive structure composed of the barrier layer, the diffusion prevention layer and the copper layer can overcome the problem of poor interface adhesion between the copper wire and the semiconductor layer.
  • the barrier layer composed of a molybdenum alloy can overcome the problem of poor interface adhesion between the copper wire and the semiconductor layer, and can prevent interdiffusion of copper atoms and silicon atoms between the copper metal layer and the semiconductor, and reduce or avoid ion diffusion. Adverse effects on the electrical properties of the semiconductor layer and the copper layer.
  • the anti-diffusion layer formed of molybdenum (Mo) can prevent the diffusion of Nb (or W, Ti, Zr, etc.) ions in the barrier layer to the copper layer, thereby preventing the electrical properties and chemical corrosion resistance of the copper metal layer from being lowered, and ensuring copper.
  • the barrier layer, the anti-diffusion layer and the copper layer have similar etched characteristics during the etching process, so that the etching is easy to form a good pattern and the process cost is reduced.
  • the array substrate shown in FIG. 2 further includes a protective layer 10 disposed on the data line 9a, the source electrode 9b and the drain electrode 9c, and the gate insulating layer 6.
  • the pixel electrode 11 is disposed on the protective layer 10. And can be electrically connected to the drain electrode 9c through a via hole 12.
  • the array substrate according to the embodiment of the present invention, the other portion except the conductive structure and the overall structure of the thin film transistor array substrate are not limited to the above-mentioned solutions.
  • a common electrode may be added to form an ADS type array substrate. It can also be used as an array substrate in the form of Color Filter on Array (COA), which will not be described here.
  • COA Color Filter on Array
  • the embodiment of the invention further provides a display device using any of the thin film transistor array substrates as described in the above embodiments.
  • the display device may be a liquid crystal device, an electronic paper display device, or an OLED display device, etc., for example, a product or a component having a display function for a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like.

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  • Thin Film Transistor (AREA)

Abstract

提供了一种导电结构及制造方法、薄膜晶体管、阵列基板和显示装置。导电结构包括：由铜或铜合金形成的铜层（2c）；用于阻挡铜层的铜离子向外扩散的阻挡层（2a）；用于阻挡外部离子扩散至铜层的防扩散层（2b），防扩散层设置在铜层和阻挡层之间。导电结构阻止外部离子扩散进入铜层以及铜层铜离子向外扩散，从而减少离子扩散对铜金属层的电学性能和化学耐腐蚀性能的不良影响，同时能够提高导电结构的粘合稳固程度；有利于对多层导电结构的刻蚀/图案化处理。

Description

导电结构及制造方法、 薄膜晶体管、 阵列基板和显示装置 技术领域
本发明的实施例涉及一种导电结构及其制造方法、 薄膜晶体管、 阵列基 板和显示装置。 背景技术
薄膜晶体管 （TFT ) 阵列基板可以用于液晶显示器（LCD )和有机发光 显示器（OLED ) 中。 液晶显示器通常包括薄膜晶体管阵列基板和彩色滤光 膜基板， 以及设置在这两个基板之间的液晶层。 当在两个基板之间施加电场 时， 液晶分子排列发生改变， 从而可以改变光线的透射比以进行显示。 有机 发光显示器则通过使用有机场致发光材料来显示图像。 有机发光显示器的像 素通常包括向有机场致发光材料提供电流的驱动薄膜晶体管和控制驱动薄膜 晶体管开启或关闭的开关薄膜晶体管。
这些显示器件可以包括栅线和数据线以对像素单元进行驱动。 随着显示 器件尺寸的增大以及显示性能要求的提高， 要求栅极线和数据线具有更低的 电阻。 目前主流的铝配线由于电阻系数较高， 已经不能满足显示性能的要求。 而铜的电阻系数比铝的电阻系数低得多， 因此使用铜作为栅极线和数据线将 成为今后的主流选择。
然而， 铜离子具有较强的渗透性， 很容易扩散到例如用于薄膜晶体管的 有源层的非晶硅或硅层中。 另外， 在对金属导电层进行刻蚀或在剥离光刻胶 过程中产生的铜离子， 也可能渗入到非晶硅层， 从而影响非晶硅层（如薄膜 晶体管）的性能。此外，硅离子和其他金属离子也容易扩散到铜导电结构内， 从而使铜导电结构的电阻系数增大并降低其化学耐腐蚀性。 发明内容
本发明的实施例提供了一种导电结构， 能够阻止外部离子扩散进入铜层 以及铜层铜离子的向外扩散， 从而减少离子扩散带来的不良影响。
根据本发明的一个方面， 本发明实施例提供了一种导电结构， 包括： 由 铜或铜合金形成的铜层； 用于阻挡所述铜层的铜离子向外扩散的阻挡层； 用 于阻挡外部离子扩散至所述铜层的防扩散层， 所述防扩散层设置在所述铜层 与所述阻挡层之间。
例如， 上述导电结构中， 所述阻挡层的材料为钼合金， 所述防扩散层的 材料为钼。
例如， 上述导电结构中， 所述钼合金为 Mo b、 MoW、 MoTi和 MoZr 中的任意一种或两种以上的混合物。
例如， 上述导电结构中， 所述钼合金中除 Mo以外的元素的原子百分比 在 O.OOlat %至 50at %之间。
例如， 上述导电结构中， 所述阻挡层的厚度为 50A至 1000A, 所述防扩 散层的厚度为 30A至 200A。
本发明实施例还提供了一种薄膜晶体管， 包括栅电极、源电极和漏电极， 所述栅电极、 源电极和漏电极中的至少一者釆用以上所述的导电结构。
根据本发明的另一个方面， 本发明实施例还提供了一种薄膜晶体管阵列 基板， 包括： 基板； 形成在所述基板上的薄膜晶体管阵列、栅极线和数据线， 所述薄膜晶体管阵列包括多个薄膜晶体管， 所述薄膜晶体管包括栅电极、 源 电极和漏电极； 在由所述栅极线和所述数据线交叉界定出的像素区域之中还 形成有像素电极； 其中， 所述数据线、 源电极、 栅极线、 栅电极和漏电极中 的至少一者釆用以上所述的导电结构。
本发明的实施例还提供了一种显示装置， 包括以上所述的薄膜晶体管阵 列基板。
本发明的实施例还提供了一种导电结构的制造方法， 包括： 在基底上形 成一用于阻挡铜离子向所述基底扩散的阻挡层； 在所述阻挡层上形成一用于 阻挡经由所述阻挡层向上扩散的离子的防扩散层； 在所述防扩散层上形成一 铜层， 所述铜层的材料为铜或铜合金。
例如， 上述方法中， 进一步釆用钼合金作溅射源， 通过溅射工艺， 形成 所述阻挡层； 进一步釆用钼作为溅射源，通过溅射工艺， 形成所述防扩散层； 进一步釆用铜或铜合金作为溅射源， 通过溅射工艺， 形成所述铜层。
例如， 所述钼合金的材料为 Mo b、 MoW、 MoTi和 MoZr中的任意一 种或两种以上的混合物。 本发明实施例提供的导电结构及其制造方法， 其中所述导电结构具有多 层结构， 利用该多层结构阻止外部离子扩散进入铜层以及铜层中铜离子的向 外扩散， 从而减少离子扩散对铜金属层的电学性能和化学耐腐蚀性能的不良 影响以及铜离子扩散对基底等的影响； 该导电结构中的阻挡层， 与玻璃基板 等衬底基板或半导体层之间具有良好的粘附性， 能够提高导电结构的粘合稳 固程度； 并且， 该多层导电结构中的各个层都具有类似的刻蚀选择性， 有利 于对多层导电结构的刻蚀 /图案化处理。 本发明实施例提供的薄膜晶体管、 阵 列基板和显示装置， 由于釆用了上述的导电结构， 因而也具有上述有益效果。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为本发明实施例提供的一种导电结构的结构示意图；
图 2为本发明实施例提供的一种薄膜晶体管阵列基板的结构示意图。 附图标记
1一基底 ； 2a—阻挡层; 2b—防扩散层；
2c—铜层； 5—栅极； 6—栅极绝缘层；
7—本征半导体层； 8—欧姆接触半导体层;
一数据线； 9b—源电极； 9c一漏电极；
一保护层； 11一像素电极; 12—过孔；
一衬底基板。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
由于铜离子的易扩散特性， 本发明的实施例抛弃了单独使用铜导电结构 的 法， 而是使用多层导电结构， 以减少或避免铜层的铜离子的向外扩散， 以及减少或避免外部离子向铜层的扩散。 并且， 本发明实施例的多层导电结 构，还能够克服现有的铜导电结构对于绝缘基板（例如玻璃基板或半导体层） 具有较低粘附性而容易发生膜的脱落的问题。
本发明的一个实施例提供了一种多层导电结构， 该多层导电结构在被图 案化时能被可靠的图案化从而形成良好的侧部轮廓。
如图 1所示， 该导电结构包括： 由铜或铜合金形成的铜层 2c; 用于阻挡 所述铜层 2c的铜离子向外扩散的阻挡层 2a; 用于阻挡外部离子扩散至所述 铜层 2c的防扩散层 2b, 所述防扩散层 2b设置在所述铜层 2c与所述阻挡层 2a之间。
上述结构中，所述阻挡层 2a可以形成在一基底 1之上。基底 1可以为玻 璃基板、 石英基板、 塑料基板等衬底基板， 也可以为电子元器件上的某一或 某几个膜层， 比如薄膜晶体管的栅绝缘层、 半导体层、 钝化层等。 在基底 1 和阻挡层 2a之间还可以形成有比如緩冲层等其他中间膜层。所述基底 1可以 为单层结构， 也可以为两层及两层以上的结构。 并且， 所述衬底 1可以同时 包含电子器件的不同区域，比如在釆用该导电结构制作阵列基板的漏电极时， 所述阻挡层 2a可以同时形成在有源层和栅绝缘层之上（即此时有源层和栅绝 缘层同时构成了基底 1 )。
在上述导电结构应用于薄膜晶体管时， 各层厚度由所需要的界面情况和 刻蚀情况来决定。 例如， 所述阻挡层 2a的厚度可以为 50A至 1000A, 所述 防扩散层 2b的厚度可以为 30A至 200A,所述铜层 2c的厚度可以为 1000 A至 5000 A。
通过以上结构， 所述防扩散层 2b能够阻挡外部离子（如阻挡层 2a中的 离子或基底 1中的离子）扩散进入铜层 2c, 以保证铜层的导电性能及化学耐 腐蚀性； 同时， 铜层 2c中的铜离子也将被阻挡层 2a所阻挡， 难以扩散至基 底 1中， 从而能够减少或避免对基底 1的影响。
作为一种优选实施方式， 本实施例中， 所述阻挡层 2a的材料为钼合金。 所述钼合金可以从 MoNb、 MoW、 MoTi和 MoZr中的任意一种， 还可以是 从以上多种中的两种以上的物质所组成的混合物。
釆用钼合金的阻挡层 2a, 与基底 1 (如衬底基板或半导体层）之间具有 良好的粘附性， 能够加强基底 1与导电结构之间的粘附， 从而能够提高导电 结构与基底 1之间结合的稳固性； 阻挡层 2a还能够防止铜离子扩散到基底 1 内， 并且呈现出与防扩散层 2b、 铜层 2c相类似的刻蚀选择性， 从而有利于 在多层结构的刻蚀 /图案化过程中对它们同时进行蚀刻处理。
本实施例中， 在釆用钼合金形成所述阻挡层 2a时， 所述钼合金中除 Mo 以外的元素的原子百分比例如在 0.001&1 %至 50at %之间。 例如， 在所述钼合 金为 MoNb时， 则钼合金中 Nb的原子百分比在 0.001at %至 50at %之间； 在 所述钼合金釆用 MoNb和 MoTi时， 则钼合金中 b和 Ti二者的原子百分比 之和在 O.OOlat %至 50at %之间。
为了防止阻挡层 2a中的金属离子扩散到铜层 2c中，导致铜层 2c电学性 能和化学耐腐蚀性能的下降， 上述结构在阻挡层 2a和铜层 2c之间沉积一层 防扩散层 2b。 防扩散层 2b为具有和阻挡层 2a、铜层 2c相类似的晶体结构材 料， 能够保证阻挡层 2a与防扩散层 2b之间界面、 防扩散层 2b与铜层 2c之 间界面的粘附性， 同时还具有与阻挡层 2a和铜层 2c类似的刻蚀选择性。 例 如， 防扩散材料为钼（Mo ), 钼（Mo )为体心立方的晶体结构， 和钼合金 (例 如 MoNb)具有相似的晶体结构，和具有面心立方晶体结构的铜同属于立方晶 系， 从而能够保证良好的界面性能。 釆用上述方法形成的导电结构， 具有良 好的界面特性和刻蚀性能； 该多层导电结构在被图案化时， 能够被可靠的图 案化从而形成良好的侧部轮廓。并且， 当该导电结构应用于具体电子器件时， 阻挡层会与其他膜层发生接触，此时防扩散层 2b也可以防止与阻挡层接触的 其他层中的金属离子扩散到铜层 2c中。
本实施例的导电结构， 能减少或避免被铜层 2c被腐蚀和氧化，且能够紧 密地附着在基底上， 同时有效克服金属离子或其他杂质对铜层的扩散所导致 的铜层电学性能和化学耐腐蚀性能的下降问题。
相应的， 本实施例还提供了一种制造图 1所示导电结构的方法， 该方法 包括如下步骤。
首先， 在基底 1上形成一阻挡层 2a, 该阻挡层 2a用于阻挡铜离子向所 述基底扩散； 然后， 在所述阻挡层 2a上形成一防扩散层 2b, 该防扩散层 2b 用于阻挡经由所述阻挡层向上扩散的离子；之后，再在所述防扩散层 2b上形 成一铜层 2c, 所述铜层 2c的材料为铜或铜合金。 这里，所述阻挡层 2a、防扩散层 2b和铜层 2c均可以通过溅射工艺形成。 例如， 所述阻挡层 2a釆用钼合金作溅射源， 所述防扩散层 2b釆用钼作溅射 源，铜层 2c釆用铜或铜合金作溅射源。所述钼合金的材料例如可以是 MoNb、 MoW、 MoTi和 MoZr中的任意一种或两种以上的混合物。 以上各层也可以 釆用其他方式形成， 如化学蒸镀方式或物理沉积方式等， 此处不再赘述。
在形成以上结构后， 本实施例还可以对上述结构做进一步图案化处理， 例如光刻胶涂布、 曝光显影以及刻蚀等处理， 得到最终所需要的图案。
上述导电结构， 可以应用于薄膜晶体管、薄膜晶体管阵列基板中。 因此， 本发明实施例还提供了一种薄膜晶体管，该薄膜晶体管通常可以包括栅电极、 源电极和漏电极， 其中所述栅电极、 源电极和漏电极中的至少一者釆用以上 所述的导电结构。 所述薄膜晶体管釆用上述导电结构外的其他部分以及薄膜 晶体管的整体结构， 本发明不作限制。
本发明实施例还提供了一种薄膜晶体管阵列基板， 该阵列基板通常可以 包括： 基板； 形成在所述基板上的薄膜晶体管阵列、 栅极线和数据线， 所述 薄膜晶体管阵列包括多个薄膜晶体管， 所述薄膜晶体管包括栅电极、 源电极 和漏电极； 在由所述栅极线和所述数据线交叉界定出的像素区域中还形成有 像素电极； 其中， 在该阵列基板上， 所述数据线、 源电极、 栅极线、 栅电极 和漏电极中的至少一者釆用以上所述的导电结构。 例如， 所述栅极线与对应 的栅电极连接， 所述数据线与对应的源电极连接， 所述像素电极与对应的漏 电极连接。
本实施例中， 薄膜晶体管阵列基板中， 栅极线和栅电极组成栅极导电结 构， 数据线、 源电极和漏电极组成数据导电结构。 栅极线形成于基板上并沿 着第一方向延伸，数据线形成在栅极绝缘层之上并沿着第二方向延伸。这里， 第一方向可以与第二方向垂直。 漏电极与源电极间隔设置。 像素电极形成在 由栅极线和数据线交叉界定出的像素区域中， 并电连接至漏电极。
本实施例中， 栅极导电结构和数据导电结构中的任一元件， 如栅电极、 栅极线或漏电极等， 都可以釆用图 1所示的导电结构。
以下将结合附图 2, 对本发明实施例的一种薄膜晶体管阵列基板作更为 详细的说明。
图 2所示的阵列基板可以应用于液晶显示器或有机发光显示器， 该阵列 基板包括一衬底基板 13, 配置在该衬底基板 13上的至少一栅极导电结构 5。 这里， 该栅极导电结构 5包括栅电极和栅极线， 栅电极和 /或栅极线可以釆用 图 1所示的导电结构， 即包括阻挡层、 防扩散层和铜层。 此时， 该阻挡层形 成于该衬底基板 13上，该阻挡层材质可为钼合金（例如 Mo b、 MoW、 MoTi、 MoZr等中的一种或多种）； 合金中 Nb (或者 W、 Ti、 Zr等） 的原子百分比 例如在 0.001at %至 50at%的范围内。该阻挡层的厚度由所需要的界面情况和 刻蚀情况来决定， 例如， 可以为 50A至 1000A之间。 该防扩散层形成于该阻 挡层上， 防扩散层材料为钼 （Mo ), 防扩散层的厚度由所需要的界面情况和 刻蚀情况来决定， 例如， 可以为 30A至 200A之间。 该铜层形成在该防扩散 层上， 材料可以是铜金属或者铜合金。
上述由阻挡层、 防扩散层和铜层组成的栅极导电结构可以克服现有技术 中铜导线与衬底基板之间粘附性不佳的问题， 由钼合金构成的阻挡层可以提 高铜层与衬底基板之间的粘附性， 同时阻止铜离子向衬底基板的扩散； 并且， 釆用钼 （Mo )材料形成的防扩散层材料， 可以阻止阻挡层中 Nb (或者 W、 Ti、 Zr等） 离子向铜层的扩散， 从而防止由上述离子扩散所造成铜金属层的 电学性能和化学耐腐蚀性能下降的问题， 保证铜金属层的低电阻值特性。 同 时， 该阻挡层、 防扩散层和铜层在进行刻蚀制程时具有类似的被刻蚀特性， 使得刻蚀易形成良好的图形， 减少制程成本。
图 2所示的阵列基板， 还包括配置于该衬底基板 13上的栅极绝缘层 6, 该栅极绝缘层 6覆盖该栅极导电结构 5。 沟道元件（即有源层 )配置于该栅 极绝缘层 6上， 包括本征半导体层 7和欧姆接触半导体层 8。 该欧姆接触半 导体层 8配置于该本征半导体层 7上。 当然， 所述有源层也可以包括有机半 导体， 或金属氧化物半导体（如 IGZO )等。
图 2所示的阵列基板， 还包括至少一数据导电结构， 该数据导电结构配 置在该沟道元件上。该数据导电结构包含数据线 9a、 源电极 9b和漏电极 9c。 该数据线 9a配置在栅极绝缘层 6上。该源电极 9b和漏电极 9c配置在该沟道 元件上， 并且该源电极 9b电连接至数据线 9a, 漏电极 9c与源电极 9b间隔 设置。 该数据线 9a、 源电极 9b和漏电极 9c中的任一者或两者以上均可以釆 用图 1中所示的导电结构， 即包括阻挡层、 防扩散层和铜层。 此时， 该阻挡 层形成于栅极绝缘层 6或所述沟道元件上， 该阻挡层材质可以为钼合金（例 如 MoNb、 MoW、 MoTi、 MoZr等中的一种或多种）； 合金中 Nb (或者 W、 Ti、 Zr等）的原子百分比例如在 0.001 1%至50 1%的范围内。 阻挡层的厚度 由所需要的界面情况和刻蚀情况来决定， 例如， 为 50A至 1000A之间。 该防 扩散层形成与该阻挡层上， 防扩散层材料为钼 （Mo ), 防扩散的厚度由所需 要的界面情况和刻蚀情况来决定， 例如， 为 30A至 200A之间。 该铜层形成 在该防扩散层上， 材料可以是铜金属层或者铜合金层。
上述由阻挡层、 防扩散层和铜层组成的数据导电结构可以克服铜导线与 半导体层之间界面粘附性不佳的问题。 由钼合金构成的阻挡层， 可以克服铜 导线与半导体层之间界面粘附性不佳的问题， 并且可以阻止铜金属层与半导 体之间铜原子与硅原子的相互扩散， 减少或避免离子扩散对半导体层和铜层 的电学性能的不良影响。 并且， 釆用钼（Mo )形成的防扩散层能够阻止阻挡 层中 Nb (或者 W、 Ti、 Zr等） 离子向铜层扩散， 防止降低铜金属层的电学 性能和化学耐腐蚀性能， 保证铜金属层的低电阻值。 同时， 该阻挡层、 防扩 散层和铜层在进行刻蚀制程时具有类似的被刻蚀特性， 使得刻蚀易形成良好 的图形， 减少制程成本。
图 2所示的阵列基板， 还包括保护层 10, 该保护层 10配置在该数据线 9a、 源电极 9b和漏电极 9c及栅极绝缘层 6上； 像素电极 11配置于该保护层 10上， 并可以通过一过孔 12电性连接至该漏电极 9c。
本发明实施例所述的阵列基板， 釆用上述导电结构外的其他部分以及薄 膜晶体管阵列基板的整体结构， 并不局限于上述所述的方案， 比如还可以加 入公共电极形成 ADS型的阵列基板，还可以制成 Color Filter on Array ( COA ) 形式的阵列基板等， 此处不赘述。
本发明实施例还提供一种显示装置， 该显示装置使用了如上述实施例所 述的任意一种薄膜晶体管阵列基板。 所述显示装置可以为液晶装置、 电子纸 显示装置或 OLED显示装置等， 例如用于手机、平板电脑、 电视机、显示器、 笔记本电脑、 数码相框、 导航仪等任何具有显示功能的产品或部件。
以上所述仅是本发明的实施方式， 应当指出， 对于本技术领域的普通技 术人员来说， 在不脱离本发明原理的前提下， 还可以作出若干改进和润饰， 这些改进和润饰也应视为属于本发明的保护范围。

Claims

权利要求书
1. 一种导电结构， 包括：
由铜或铜合金形成的铜层；
用于阻挡所述铜层的铜离子向外扩散的阻挡层；
用于阻挡外部离子扩散至所述铜层的防扩散层， 所述防扩散层设置在所 述铜层与所述阻挡层之间。
2. 如权利要求 1所述的导电结构， 其中， 所述阻挡层的材料为钼合金， 所述防扩散层的材料为钼。
3. 如权利要求 1 或 2所述的导电结构， 其中， 所述钼合金为 Mo b、
MoW、 MoTi和 MoZr中的任意一种或两种以上的混合物。
4. 如权利要求 3所述的导电结构， 其中，
所述钼合金中除 Mo 以外的元素的原子百分比在 0.001&1 %至 5(^ %之 间。
5. 如权利要求 1或 2所述的导电结构， 其中， 所述阻挡层的厚度为 50A 至 1000A, 所述防扩散层的厚度为 30A至 200A。
6. 一种薄膜晶体管， 包括栅电极、 源电极和漏电极， 所述栅电极、 源电 极和漏电极中的至少一者釆用权利要求 1至 5任一项所述的导电结构。
7. 一种薄膜晶体管阵列基板， 包括：
基板；
形成在所述基板上的薄膜晶体管阵列、 栅极线和数据线， 所述薄膜晶体 管阵列包括多个薄膜晶体管，所述薄膜晶体管包括栅电极、源电极和漏电极； 在由所述栅极线和所述数据线交叉界定出的像素区域之中还形成有像素 电极；
其中， 所述数据线、 源电极、 栅极线、 栅电极和漏电极中的至少一者釆 用权利要求 1至 5任一项所述的导电结构。
8. 一种显示装置， 包括权利要求 7所述的薄膜晶体管阵列基板。
9. 根据权利要求 8的显示装置， 其中， 该显示装置包括液晶显示装置、 电子纸显示装置或有机发光显示装置。
10. 一种导电结构的制造方法， 包括： 在基底上形成一用于阻挡铜离子向所述基底扩散的阻挡层； 在所述阻挡层上形成一用于阻挡经由所述阻挡层向上扩散的离子的防扩 散层；
在所述防扩散层上形成一铜层， 所述铜层的材料为铜或铜合金。
11. 如权利要求 10所述的方法， 其中，
进一步釆用钼合金作溅射源， 通过溅射工艺， 形成所述阻挡层； 进一步釆用钼作为溅射源， 通过溅射工艺， 形成所述防扩散层； 进一步釆用铜或铜合金作为溅射源， 通过溅射工艺， 形成所述铜层。
12. 如权利要求 11 所述的方法， 其中， 所述钼合金的材料为 MoNb、 MoW、 MoTi和 MoZr中的任意一种或两种以上的混合物。
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