WO2013143157A1 - 显示器的闸极驱动电路 - Google Patents

显示器的闸极驱动电路 Download PDF

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Publication number
WO2013143157A1
WO2013143157A1 PCT/CN2012/073516 CN2012073516W WO2013143157A1 WO 2013143157 A1 WO2013143157 A1 WO 2013143157A1 CN 2012073516 W CN2012073516 W CN 2012073516W WO 2013143157 A1 WO2013143157 A1 WO 2013143157A1
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Prior art keywords
transistor
node
gate
driving circuit
reference voltage
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PCT/CN2012/073516
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English (en)
French (fr)
Inventor
陈世烽
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/511,684 priority Critical patent/US20150028933A1/en
Publication of WO2013143157A1 publication Critical patent/WO2013143157A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation

Definitions

  • the invention relates to a gate driving circuit of a display, in particular to a display gate driving circuit capable of effectively reducing leakage current of a transistor.
  • Liquid crystal display LCD uses an electric field to control liquid crystal molecules having dielectric anisotropy to change the transmittance of light, thereby displaying an image.
  • a liquid crystal display generally includes a display panel having pixels arranged in a matrix and a driving circuit for driving the display panel.
  • the above driving circuit is generally divided into a source driving circuit and a gate driving circuit, wherein the source driving circuit converts the input data into a data signal, and the gate driving circuit generates a scanning signal for driving the pixel to display the corresponding input. Image of the data.
  • the source driving circuit and the gate driving circuit can operate according to timing determined by a control signal generated by the timing controller.
  • amorphous silicon (Amorphous-Si) thin film transistor technology to design the gate drive circuit of the liquid crystal display has gradually become the mainstream trend.
  • the amorphous germanium thin film transistor device may cause a problem of threshold voltage drift due to long-term use or high bias application, thereby affecting the stability of the driving circuit and degrading the display quality of the screen.
  • the gate driving circuit is configured to generate a pulse signal according to a predetermined timing, and the pulse signal is sent to the gate line, thereby controlling the switching of the thin film transistor in the pixel of the display panel.
  • the transistor T11 serves as a start switch, and the transistor T12 functions as a pulse switch.
  • the start pulse signal ST turns on the transistor T11, the storage capacitor Cb is charged, and when the pulse signal CLK is at a high potential, the memory is stored.
  • the capacitor Cb is discharged, thereby providing a voltage signal VN to the Nth gate line of the display panel as the output signal OUT(N).
  • Transistor T12 is usually called a pull-up transistor. Because the entire gate line needs to be charged, the pull-up transistor T12 must supply a high current. If the pull-up transistor T12 cannot provide enough current, the pixel corresponding to the gate line will be can not work normally.
  • Transistor T13 and transistor T14 act as pull-down transistors that pull the signal to the gate line to a voltage level close to the reference voltage signal Vss. Specifically, when the transistor T13 and the transistor T14 are turned on by the reset signal RESET, the transistor T14 can pull down the voltage of the node Q1 to a voltage level close to the reference voltage signal Vss, and the transistor T13 can pull the voltage of the node Q2 to near the reference. The voltage level of the voltage signal Vss.
  • the gate driving circuit is prone to generate noise, so that other auxiliary noise suppression circuits need to be added.
  • transistors are used to suppress noise by digital signal processing.
  • a large layout area is occupied, and for a narrow frame product in the display, it is impossible to achieve due to insufficient area.
  • FIG. 2 is a partial circuit diagram showing a gate driving circuit of a conventional display for suppressing noise.
  • the existing gate drive circuit uses capacitive coupling to control noise.
  • a coupling capacitor Cp is inserted between the connection node P1 between the transistor T21 and the transistor T22 and the clock signal CLK, so that fewer transistor elements can be used to suppress the noise.
  • the relative wiring area is also reduced, which is beneficial to the development of narrow frame products in the display.
  • An object of the present invention is to provide a gate driving circuit for a display to solve the problem that a transistor in a gate driving circuit is prone to leakage current.
  • Another object of the present invention is to provide a gate driving circuit for a display to improve the stability of the driving voltage of the gate driving circuit and improve the reliability of the gate driving circuit.
  • An aspect of the present invention provides a gate driving circuit for a display, comprising: a first node having a voltage level when the start signal passes together; a first transistor coupled to the first node and a reference voltage a signal input end, when the first transistor is turned on, the voltage of the first node is pulled down to a voltage close to the reference voltage signal; a second transistor has one end electrically connected to the first transistor, and the other end The reference voltage signal input end is electrically connected; a second node is located at a connection end of the first transistor and the second transistor; a capacitor is disposed at the second node and a clock signal input end, the capacitor is used for suppressing impurities And generating a third transistor disposed between the first transistor and the input of the reference voltage signal, the third transistor being connected in series with the first transistor for sharing the first node with the first transistor The voltage difference from the input of the reference voltage signal.
  • the gate of the first transistor is electrically connected to the gate of the third transistor.
  • the circuit further includes a fourth transistor disposed between the third transistor and the input of the reference voltage signal, wherein the fourth transistor is connected in series with the third transistor. And a voltage difference between the first node and the input of the reference voltage signal is shared with the first transistor and the third transistor.
  • the gate of the third transistor is electrically connected to the gate of the fourth transistor.
  • the gate of the second transistor is electrically connected to the first node.
  • a gate driving circuit for a display comprising: a first transistor, a first end of the first transistor coupled to a first node providing a high potential, and a first transistor The second end is coupled to a reference voltage signal input terminal; a second transistor, the first end of the second transistor is electrically connected to the third end of the first transistor and forms a second node therebetween, the second transistor The second end is coupled to the reference voltage signal input end, and the third end of the second transistor is coupled to the first node; a capacitor, one end of the first transistor and the second transistor The two nodes are electrically connected, and the other end is electrically coupled to a clock signal input terminal; and at least one transistor is disposed between the first transistor and the reference voltage signal input end, and the at least one transistor is connected in series with the first transistor connection.
  • the third end of the first transistor is a gate electrically connected to the gate of the at least one transistor.
  • the voltage of the first node is pulled down to a voltage close to the reference voltage signal.
  • the third end of the first transistor is a gate
  • the first end of the second transistor is a source or a drain.
  • the first transistor, the second transistor, and the at least one transistor are amorphous silicon transistors.
  • a further aspect of the present invention provides a gate driving circuit for a display, comprising: a first node, which transmits a driving signal of a high voltage level to an output terminal according to a start signal and a clock signal, the output end Electrically connected to a gate line; a first transistor, the first end of the first transistor is coupled to the first node, and the second end of the first transistor is coupled to a reference voltage signal input end; a second transistor, the first end of the second transistor is electrically connected to the third end of the first transistor, the second end of the second transistor is coupled to the reference voltage signal input end, and the second transistor is The three ends are coupled to the first node; and at least one transistor is disposed between the first transistor and the reference voltage signal input end, and the at least one transistor is connected in series with the first transistor.
  • the gate driving circuit of the display of the present invention further comprising a start transistor disposed between the input end of the start signal and the first node; and a clock transistor disposed at the input end of the clock signal and Between the first nodes.
  • a storage capacitor is further disposed between the first node and the output terminal.
  • the gate driving circuit of the display of the present invention further comprising a first pull-down transistor disposed between the first node and the reference voltage signal input terminal; and a second pull-down transistor disposed at the output terminal and Between the reference voltage signal input terminals, when the first pull-down transistor and the second pull-down transistor are turned on based on a reset signal, the voltage of the first node and the output terminal is pulled down to the reference voltage signal The voltage at the input.
  • the third end of the first transistor is a gate electrically connected to the gate of the at least one transistor.
  • the present invention by integrating at least one transistor between the first transistor and the reference voltage signal input terminal, the voltage load between the source and the drain of the first transistor is distributed to the at least one transistor, whereby the first transistor The leakage current is not affected by the high voltage on the first node, so that the voltage on the first node is lowered, resulting in insufficient pixel driving voltage. Therefore, the present invention can effectively solve the problem of driving voltage stability of the gate driving circuit and improve the problem. The reliability of the gate drive circuit further improves the display quality of the display panel.
  • FIG. 1 shows a partial circuit diagram of a gate drive circuit of a conventional display.
  • FIG. 2 is a partial circuit diagram showing a gate driving circuit of a conventional display for suppressing noise.
  • FIG. 3 is a circuit diagram showing a display gate driving circuit according to a first embodiment of the present invention.
  • FIG. 4 is a circuit diagram showing a display gate driving circuit in accordance with a second embodiment of the present invention.
  • the display may be a liquid crystal display or an active liquid crystal display (AMOLCD), and the display includes a display panel in which pixels are arranged in a matrix and a driving circuit for driving the display panel.
  • the driving circuit is divided into a source driving circuit and a gate driving circuit, and the source driving circuit is used for converting the input image data into a data signal, and the gate driving circuit is generated according to the timing generated by the clock controller.
  • the scan signal of the pixel is driven to display an image corresponding to the data signal.
  • the invention focuses on the improvement of the gate driving circuit to reduce the leakage current of the transistors inside the gate driving circuit, thereby improving the stability of the gate driving circuit and improving the picture display quality of the display panel.
  • the solution for preventing leakage current of the transistor provided by the present invention has an effect more. good.
  • FIG. 3 is a circuit diagram showing a display gate driving circuit according to a first embodiment of the present invention. Although only one stage of the circuit is illustrated in FIG. 3, those skilled in the art can understand that the integrated gate driving circuit is formed by connecting a plurality of stages of circuits, and each stage of the circuit corresponds to one of the driving display panels. Multiple gate lines, in addition to providing a scan signal to the corresponding gate line, the circuit of this stage also provides an output signal as an input to the next stage circuit.
  • the gate driving circuit includes a first transistor T31, a second transistor T32, a third transistor T33, and a capacitor Cp.
  • the electrical coupling between one end of the first transistor T31 and the second transistor T32 is shown.
  • the contact has a first node Q1, and the other end of the first transistor T31 and the second transistor T32 are coupled to a second node P1.
  • the start signal ST turns on the transistor Ts1 at a high voltage level, and then charges the storage capacitor Cb.
  • the clock signal CLK is in a high potential state, and the transistor Ts2 is turned off, so that the storage capacitor Cb starts to discharge, thereby providing a voltage signal to the Nth gate line of the display panel as an output signal OUT(N).
  • the transistor Td1 and the transistor Td2 are turned on by the reset signal RESET, the transistor Td1 can pull down the voltage of the node Q1 to a voltage level close to the reference voltage signal Vss, and the transistor Td2 can pull down the voltage of the output signal OUT(N). To the voltage level close to the reference voltage signal Vss, the voltage output to the Nth gate line is kept low.
  • the first node Q1 maintains a high voltage level for a period of time and a low voltage level for another period of time according to the timing of the start signal.
  • the storage capacitor Cb is charged, and the high voltage when the storage capacitor Cb is discharged is input to the corresponding scan line of the stage, as a scan signal to drive the scan line of the stage. Pixels.
  • the start signal ST when the start signal ST is at a low voltage level, the voltage of the node Q1 is easily affected by the clock signal CLK and exhibits a slight fluctuation, so a noise suppression circuit is needed to reduce the influence of the noise on the overall circuit. .
  • the micro-amplitude is still insufficient to turn on the second transistor T32, but the clock signal The high potential of CLK turns on the first transistor T31 and the third transistor T33, so the micro-high potential of the node Q1 is pulled to the reference voltage Vss, that is, the ground potential.
  • the start signal ST is at a high voltage level
  • the high potential on the node Q1 turns on the second transistor T32, and the ground potential of the reference voltage Vss is transmitted to the node P1, at which time the first transistor T31 and the third transistor T33 In the ideal case of the off state, the high potential on node Q1 can thus charge capacitor Q1.
  • the transistor in the gate driving circuit such as the first transistor T31.
  • the high voltage on the first node Q1 is decreased, which may cause a problem that the driving voltage of the pixel is insufficient, so that the pixel corresponding to the scan line cannot work normally.
  • the leakage current of the first transistor T31 can be effectively reduced, thereby effectively solving the problem of the driving voltage stability of the gate driving circuit.
  • the first transistor T31 is coupled between the first node Q1 and a reference voltage signal Vss, and one end of the second transistor T32 is electrically connected to the first transistor T31, and the other end is electrically connected to the input end of the reference voltage signal Vss.
  • the first end 311 of the first transistor T31 is coupled to the first node Q1
  • the second end 312 of the first transistor T31 is coupled to the input end of the reference voltage signal Vss
  • the second end 322 of the second transistor T32 is 322.
  • the third terminal 323 of the second transistor T32 is coupled to the first node Q1.
  • the third end 313 of the first transistor T31 is electrically connected to the first end 321 of the second transistor T32. That is, in a specific circuit configuration, the gate 313 of the first transistor T31 is electrically connected to the source or the drain of the second transistor T32, and the gate of the second transistor T32 is electrically connected to the first node. Q1.
  • the first node Q1 maintains a high voltage level for a period of time according to the timing of the start signal, and maintains a low voltage level for another period of time, the high voltage level being passed through the charge and discharge of the storage capacitor Cb.
  • the driving voltage of the pixel which requires a relatively high voltage.
  • the third end 313 of the first transistor T31 is electrically connected to the first end 321 of the second transistor T32 tube and forms a second node P1 therebetween. That is, in a specific circuit configuration, the gate of the first transistor T31 and the source or drain of the second transistor T32 have a second node P1.
  • the capacitor Cp is provided at the input terminal of the second node P1 and the clock signal CLK from the clock controller. Specifically, one end of the capacitor Cp is electrically connected to the second node P1 between the first transistor T31 and the second transistor T32, and the other end of the capacitor Cp is electrically coupled to the input end of the clock signal CLK.
  • the gate driving circuit has at least one transistor, as shown in FIG. 3, a third transistor T33 disposed between the first transistor T31 and the input terminal of the reference voltage signal Vss, the at least one transistor (or the third The transistor T33) is connected in series with the first transistor T31.
  • the first end 331 of the third transistor T33 is electrically connected to the second end 312 of the first transistor T31
  • the second end 332 of the third transistor T33 is electrically coupled to the input end of the reference voltage signal Vss.
  • the third end 333 of the three transistor T33 is electrically connected to the third end 313 of the first transistor T31. That is, in a specific circuit configuration, the gate of the first transistor T31 is electrically connected to the gate of the third transistor T33 such that the first transistor T31 and the third transistor T33 form a connection structure in series.
  • the third transistor T33 is configured such that the third transistor T33 can share the voltage difference between the first node Q1 and the input terminal of the reference voltage signal Vss together with the first transistor T31. That is, the configuration of the third transistor T33 can alleviate the voltage load of the voltage Vds between the source and the drain of the first transistor T31 to reduce the leakage current of the first transistor T31.
  • the gate driving circuit further includes a fourth transistor T34 disposed at the third transistor T33 and the reference voltage signal Vss input. Between the terminals, the fourth transistor T34 is connected in series with the third transistor T33.
  • the gate of the fourth transistor T34 is electrically coupled to the gate of the third transistor T33 such that the fourth transistor T34 and the third transistor T33 form a connection structure in series.
  • the first transistor T31, the third transistor T33, and the fourth transistor T34 are all connected in series to each other.
  • the configuration of the fourth transistor T34 is increased such that the third transistor T33 and the fourth transistor T34 can be shared with the first transistor T31 between the first node Q1 and the reference voltage signal Vss input terminal.
  • the voltage difference That is, the configuration of the third transistor T33 and the fourth transistor T34 can alleviate the voltage load of the voltage Vds between the source and the drain of the first transistor T31 to reduce the leakage current of the first transistor T31.
  • two transistors, that is, the third transistor T33 and the fourth transistor T34 are disposed, which is more effective for reducing the voltage load of the voltage Vds between the source and the drain of the first transistor T31, and is more effective. The chance of leakage current of the first transistor T31 is reduced, ensuring that the high voltage on the first node Q1 is not affected.
  • the present invention connects at least one transistor, such as a third transistor and a fourth transistor, between the first transistor and the reference voltage signal input terminal to connect the source and the drain of the first transistor.
  • the voltage load is distributed to the at least one transistor, so that when the first node is in a high voltage state, the first transistor is not affected by the leakage current, so that the voltage on the first node is lowered, thereby causing the pixel driving voltage to be insufficient. Therefore, the present invention can effectively solve the problem of the driving voltage stability of the gate driving circuit, improve the reliability of the gate driving circuit, and further improve the picture display quality of the display panel.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Description

显示器的闸极驱动电路 技术领域
本发明涉及一种显示器的闸极驱动电路，特别涉及一种可有效减少晶体管发生漏电流的显示器闸极驱动电路。
 背景技术
液晶显示器（liquid crystal display, LCD）是利用电场来控制具有介电异向性的液晶分子，以改变光的穿透性，依此来显示影像。液晶显示器通常包含一显示面板具有矩阵排列的像素以及一驱动电路用来驱动该显示面板。
上述的驱动电路一般分为源极驱动电路和闸极驱动电路，源极驱动电路是将输入资料转换成资料信号，而闸极驱动电路会产生用于驱动像素的扫描信号，以显示对应该输入资料的影像。源极驱动电路和闸极驱动电路可根据由时序控制器产生之控制信号所决定的时序来进行操作。
现今，为了降低显示器的成本，采用非晶硅（amorphous-Si）薄膜晶体管技术来设计液晶显示器的闸极驱动电路已逐渐成为主流的趋势。然而，非晶矽薄膜晶体管元件会因为长时间的使用，或者是高偏压施加而产生临界电压漂移的问题，进而影响到驱动电路的稳定度，造成画面的显示品质下降。
现有的闸极驱动电路中，一般是由多级的移位暂存器（shift register）串联而成，移位暂存器输出的闸极脉冲讯号也会提供给下一级的移位暂存器作为一个输入信号，相关专利可参考US 7,825,887和TW 200813920。
图1显示一种现有的显示器的闸极驱动电路的部分电路示意图。闸极驱动电路用来根据预定的时序产生脉冲信号，脉冲信号会送到闸极线，藉此来控制显示面板之像素内的薄膜电晶体的开关。如图1所示，晶体管T11作为起始的开关，晶体管T12作为脉冲开关，当起始脉冲信号ST将晶体管T11打开时，会对存储电容Cb进行充电，当时脉信号CLK处于高电位时，存储电容Cb进行放电，藉此提供电压信号VN给显示面板的第N条闸极线，作为输出信号OUT(N)。
晶体管T12通常称为上拉晶体管，因为需对整条闸极线充电，所以上拉晶体管T12必须提供高电流，若上拉晶体管T12无法提供足够的电流，则对应该条闸极线的像素将无法正常工作。
晶体管T13和晶体管T14作为下拉晶体管，其能将送到闸极线的信号下拉到接近参考电压信号Vss的电压水平。具体来说，通过重置信号RESET将晶体管T13和晶体管T14开启时，晶体管T14可将节点Q1的电压下拉到接近参考电压信号Vss的电压水平，而晶体管T13可将节点Q2的电压下拉到接近参考电压信号Vss的电压水平。
然而，由于需在上拉晶体管T12提供高电压，因此闸极驱动电路容易产生杂讯，故需再增加其他辅助的杂讯抑制电路，一般有采用晶体管以数位讯号处理的方式来抑制杂讯，但因需要的晶体管元件较多，占用了较大的布线（layout）面积，对于显示器中窄边框的产品来说，因面积不足而无法达成。
图2显示现有的显示器的闸极驱动电路用来抑制杂讯的部分电路示意图。为了降低杂讯，现有的闸极驱动电路采用电容耦合的方式来控制杂讯。如图2所示的等效电路中，在晶体管T21和晶体管T22间的连接节点P1与时脉信号CLK之间插入一耦合电容Cp，如此可以使用较少的晶体管元件来达到抑制杂讯的效果，相对的布线面积也会减少，从而有利于显示器中窄边框产品的开发。
然而，在图2所示的电路中，由于节点Q1的电压会被拉到两倍于时脉信号CLK的电压水平，因此晶体管T21的源极和汲极间的电压Vds过高，导致漏电流增大，而节点Q1的电压也会因晶体管T21产生漏电流的现象而跟着下降，致使闸极驱动电路驱动的能力下降，容易造成相应闸极线之像素无法正常工作的情况。
 技术问题
本发明之一目的在于提供一种显示器的闸极驱动电路，以解决闸极驱动电路内之晶体管容易产生漏电流的问题。
本发明之另一目的在于提供一种显示器的闸极驱动电路，以提升闸极驱动电路之驱动电压的稳定性，提高闸极驱动电路的可靠度。
 技术解决方案
本发明一方面提供一种显示器的闸极驱动电路，包含：一第一节点，其在一起始信号通过时具有一电压水平；一第一晶体管，其耦接于该第一节点和一参考电压信号输入端，当该第一晶体管开启时，该第一节点的电压会被下拉到接近该参考电压信号的电压；一第二晶体管，其一端与该第一晶体管电性连接，另一端与该参考电压信号输入端电性连接；一第二节点，位于该第一晶体管和该第二晶体管的连接端；一电容，设置于该第二节点和一时脉信号输入端，该电容用于抑制杂讯的产生；以及一第三晶体管，设置於该第一晶体管和该参考电压信号输入端之间，该第三晶体管与该第一晶体管串联连接，用于与该第一晶体管分摊该第一节点与该参考电压信号输入端之间的电压差。
在本发明之显示器的闸极驱动电路中，该第一晶体管的闸极与该第三晶体管的闸极电性连接。
在本发明之显示器的闸极驱动电路中，所述电路更包含一第四晶体管，设置於该第三晶体管和该参考电压信号输入端之间，该第四晶体管与该第三晶体管串联连接，用于与第一晶体管和该第三晶体管分摊该第一节点与该参考电压信号输入端之间的电压差。
在本发明之显示器的闸极驱动电路中，该第三晶体管的闸极与该第四晶体管的闸极电性连接。
在本发明之显示器的闸极驱动电路中，该第二晶体管的闸极电性连接至该第一节点。
本发明另一方面提供一种显示器的闸极驱动电路，包含：一第一晶体管，该第一晶体管的第一端耦接至提供一高电位的一第一节点，而该第一晶体管的第二端耦接至一参考电压信号输入端；一第二晶体管，该第二晶体管的第一端与该第一晶体管的第三端电性连接并在其间形成一第二节点，该第二晶体管的第二端耦接至该参考电压信号输入端，而该第二晶体管的第三端耦接至该第一节点；一电容，其一端与该第一晶体管和该第二晶体管间的该第二节点电性连接，另一端与一时脉信号输入端电性耦接；以及至少一晶体管，设置在该第一晶体管和该参考电压信号输入端之间，该至少一晶体管与该第一晶体管串联连接。
在本发明之显示器的闸极驱动电路中，该第一晶体管的第三端为闸极，其与该至少一晶体管的闸极电性连接。
在本发明之显示器的闸极驱动电路中，当该第一晶体管和该至少一晶体管开启时，该第一节点的电压会被下拉到接近该参考电压信号的电压。
在本发明之显示器的闸极驱动电路中，该第一晶体管的第三端为闸极，而该第二晶体管的第一端为源极或汲极。
在本发明之显示器的闸极驱动电路中，该第一晶体管、该第二晶体管和该至少一晶体管为非晶硅晶体管。
本发明再一方面提供一种显示器的闸极驱动电路，包含：一第一节点，其会根据一起始信号和一时脉信号，将一高电压水平的驱动信号传送到一输出端，该输出端电性连接至一闸极线；一第一晶体管，该第一晶体管的第一端耦接至该第一节点，而该第一晶体管的第二端耦接至一参考电压信号输入端；一第二晶体管，该第二晶体管的第一端与该第一晶体管的第三端电性连接，该第二晶体管的第二端耦接至该参考电压信号输入端，而该第二晶体管的第三端耦接至该第一节点；以及至少一晶体管，设置于该第一晶体管和该参考电压信号输入端之间，该至少一晶体管与该第一晶体管串联连接。
在本发明之显示器的闸极驱动电路中，更包含一起始晶体管，设置于该起始信号之输入端和该第一节点之间；以及一时脉晶体管，设置于该时脉信号之输入端和该第一节点之间。
在本发明之显示器的闸极驱动电路中，更包含一存储电容，设置于该第一节点和该输出端之间。
在本发明之显示器的闸极驱动电路中，更包含一第一下拉晶体管，设置于该第一节点和该参考电压信号输入端之间；以及一第二下拉晶体管，设置于该输出端和该参考电压信号输入端之间，其中当该第一下拉晶体管和该第二下拉晶体管基于一重置信号而导通时，会将该第一节点和该输出端的电压下拉至该参考电压信号输入端的电压。
在本发明之显示器的闸极驱动电路中，该第一晶体管的第三端为闸极，其与该至少一晶体管的闸极电性连接。
 有益效果
在本发明中，通过在第一晶体管和参考电压信号输入端之间串联至少一晶体管，以将第一晶体管源极和汲极间的电压负荷分摊到该至少一晶体管上，藉此第一晶体管不致受第一节点上高电压的影响而产生漏电流使得第一节点上之电压降低所导致像素驱动电压不足的情形，因此本发明能够有效解决闸极驱动电路之驱动电压稳定性的问题，提高闸极驱动电路的可靠度，进一步提升显示面板的画面显示品质。
 附图说明
图1显示一种现有的显示器的闸极驱动电路的部分电路示意图。
图2显示现有的显示器的闸极驱动电路用来抑制杂讯的部分电路示意图。
图3显示根据本发明第一实施例的显示器闸极驱动电路的电路示意图。
图4显示根据本发明第二实施例的显示器闸极驱动电路的电路示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。
在本发明说明书及权利要求当中使用了某些词汇来指称特定的元件，本领域技术人员应可理解，硬件制造商可能会用不同的名词来称呼同一个元件。
在通篇说明书及权利请求当中所提及的「包含」为一开放式的用语，故应解释成「包含但不限定于」。此外，「耦接」一词在此包含任何直接及间接的电性连接手段，因此若本说明书文中描述第一元件耦接于第二元件，则代表第一元件可直接电性连接于第二元件，或通过其他元件或连接手段间接地电性连接至第二元件。并且，在说明书和附图中，结构相似的单元是以相同标号表示。
在本发明中，显示器可为液晶显示器或主动式液晶显示器（AMOLCD），显示器包含像素呈矩阵排列的一显示面板以及用来驱动该显示面板的一驱动电路。该驱动电路分为源极驱动电路和闸极驱动电路，源极驱动电路用来将输入的影像资料转换成资料信号，而闸极驱动电路会根据时脉控制器产生的时序，来产生用于驱动像素的扫描信号，以显示对应该资料信号的影像。
本发明着重在闸极驱动电路的改良，以减少闸极驱动电路内部之晶体管发生漏电流的情形，藉此提升闸极驱动电路的稳定性，从而提升显示面板的画面显示品质。此外，特别是在闸极驱动电路内部之晶体管实现为采用非晶硅（amorphous-Si）薄膜晶体管技术而制成的晶体管时，本发明所提供之防止晶体管发生漏电流的解决方案，其效果更佳。
图3显示根据本发明第一实施例的显示器闸极驱动电路的电路示意图。虽然图3中仅例示了一级的电路，但本领域技术人员可以理解到，整合的闸极驱动电路是由若干级的电路串联而成，每一级的电路对应驱动显示面板中的一或多条闸极线，本级的电路除了提供扫描信号给对应的闸极线之外，也会提供一个输出信号作为下一级电路的一个输入。
如图3所示，闸极驱动电路中包含一第一晶体管T31、一第二晶体管T32、一第三晶体管T33和一电容Cp，第一晶体管T31的一端与第二晶体管T32耦接的电性接点上具有一第一节点Q1，而第一晶体管T31的另一端与第二晶体管T32耦接的电性接点上具有一第二节点P1。
首先，当接收到一起始信号ST，起始信号ST在高电压水平时会将晶体管Ts1开启，並接着对存储电容Cb充电。而当电容充电完成时，时脉信号CLK处于高电位状态，晶体管Ts2关闭，使得存储电容Cb开始放电，藉此提供电压信号给显示面板的第N条闸极线，作为输出信号OUT(N)。此外，在通过重置信号RESET将晶体管Td1和晶体管Td2开启时，晶体管Td1可将节点Q1的电压下拉到接近参考电压信号Vss的电压水平，而晶体管Td2可将输出信号OUT(N)的电压下拉到接近参考电压信号Vss的电压水平，此时输出至第N条闸极线的电压保持低电位。
具体来说，第一节点Q1会根据该起始信号的时序，在一段时间内保持高电压水平，而在另一段时间内保持低电压水平。当第一节点Q1在高电压水平时，会对存储电容Cb进行充电，而存储电容Cb放电时的高电压会输入对应该级的扫描线，作为扫描信号，以驱动该级之扫描线所对应的像素。
另外，当起始信号ST在低电压水平时，节点Q1的电压容易受到时脉信号CLK的影响而呈现微幅高低起伏的情形，因此需要杂讯抑制电路来减低此杂讯对整体电路的影响。如图3所示，当起始信号ST在低电压水平，而节点Q1受时脉信号CLK影响处于微幅高电位时，此微幅高电位仍不足将第二晶体管T32开启，但时脉信号CLK的高电位会将第一晶体管T31和第三晶体管T33导通，因此节点Q1的微幅高电位会被拉至参考电压Vss，即接地电位。
再者，当起始信号ST在高电压水平时，节点Q1上的高电位会将第二晶体管T32开启，参考电压Vss的接地电位传递到节点P1，此时第一晶体管T31和第三晶体管T33在理想情况下为关闭状态，节点Q1上的高电位因而能对电容Q1进行充电。
由于驱动扫描线上对应之像素需要相当高的电流，也就是说，在第一节点Q1上的高电压需要的电压相当大，这就容易使得闸极驱动电路中的晶体管，如第一晶体管T31，产生漏电流，而第一晶体管T31发生漏电流现象时，第一节点Q1上的高电压会跟着降低，进而容易导致像素之驱动电压不足的问题，使得该扫描线所对应的像素无法正常工作。
本发明通过在第一晶体管T31串联至少一晶体管，如第三晶体管T33，藉此能够有效减少第一晶体管T31发生漏电流的情况，进而有效解决闸极驱动电路之驱动电压稳定性的问题。
以下将详细说明根据本发明实现的第一实施例的闸极驱动电路的电路配置示意图。
第一晶体管T31耦接于第一节点Q1和一参考电压信号Vss输入端之间，第二晶体管T32的一端与第一晶体管T31电性连接，另一端与参考电压信号Vss输入端电性连接。具体来说，第一晶体管T31的第一端311耦接至第一节点Q1，第一晶体管T31的第二端312耦接至参考电压信号Vss输入端；而第二晶体管T32的第二端322耦接至参考电压信号Vss输入端，第二晶体管T32的第三端323耦接至第一节点Q1。第一晶体管T31的第三端313与第二晶体管T32的第一端321电性连接。也就是说，在具体的电路配置中，第一晶体管T31的闸极313是与第二晶体管T32的源极或汲极电性连接，而第二晶体管T32的闸极电性连接至第一节点Q1。
在上述电路配置中，当第一晶体管T31开启而第三晶体管T33也随着开启时，第一节点Q1的电压会被下拉到接近参考电压信号Vss的电压。
如前所述，第一节点Q1会根据起始信号的时序，在一段时间内保持高电压水平，而在另一段时间内保持低电压水平，该高电压水平透过存储电容Cb的充放电作为像素的驱动电压，其所需的电压相当高。当第一节点Q1处于高电压状态，而第一晶体管T31关闭时，容易导致第一晶体管T31发生漏电流的现象，进而使得第一节点Q1上的驱动电压电压不足。关于此点，本发明提出的具体解决方案将于后文详细描述。
在第一晶体管T31和第二晶体管T32的连接端具有第二节点P1。具体来说，第一晶体管T31的第三端313与第二晶体T32管的第一端321电性连接并在其间形成第二节点P1。也就是说，在具体的电路配置中，第一晶体管T31的闸极与第二晶体管T32的源极或汲极的连接端具有第二节点P1。
电容Cp设置于第二节点P1和来自时脉控制器的时脉信号CLK的输入端。具体来说，电容Cp的一端是与第一晶体管T31和第二晶体管T32间的第二节点P1电性连接，而电容Cp的另一端是与该时脉信号CLK输入端电性耦接。
通过在第二节点P1和时脉信号CLK输入端之间插入耦合电容Cp，藉此可使用较少的晶体管元件来抑制闸极驱动电路中因高驱动电压所容易引起的杂讯，避免了节点Q1受时脉信号CLK影响而导致的微幅电压变动，也因此闸极驱动电路在显示面板上的布线面积可以减少，非常有利于显示器中窄边框产品的开发。
本发明中，闸极驱动电路中具有至少一晶体管，如图3所示的第三晶体管T33，其设置在第一晶体管T31和参考电压信号Vss输入端之间，该至少一晶体管（或第三晶体管T33）与第一晶体管T31串联连接。具体来说，第三晶体管T33的第一端331与第一晶体管T31的第二端312电性连接，第三晶体管T33的第二端332与参考电压信号Vss输入端电性耦接，而第三晶体管T33的第三端333与第一晶体管T31的第三端313电性连接。也就是说，在具体的电路配置中，第一晶体管T31的闸极与第三晶体管T33的闸极电性连接，以使得第一晶体管T31和第三晶体管T33形成串联的连接架构。
在本发明第一实施例中，上述第三晶体管T33的配置，使得第三晶体管T33可以与第一晶体管T31一起分摊第一节点Q1与参考电压信号Vss输入端之间的电压差。也就是说，第三晶体管T33的配置可以减轻第一晶体管T31源极和汲极间的电压Vds的电压负荷，以减少第一晶体管T31发生漏电流的现象。
图4显示根据本发明第二实施例的显示器闸极驱动电路的电路示意图。与图3所示的第一实施例相较，在图4所示的第二实施例中，闸极驱动电路更包含一第四晶体管T34，其设置在第三晶体管T33和参考电压信号Vss输入端之间，第四晶体管T34与第三晶体管T33串联连接。在具体的电路配置中，第四晶体管T34的闸极与第三晶体管T33的闸极电性连接，以使得第四晶体管T34和第三晶体管T33形成串联的连接架构。进一步来说，第一晶体管T31、第三晶体管T33和第四晶体管T34都是相互串联连接的。
在本发明第二实施例中，增加了上述第四晶体管T34的配置，使得第三晶体管T33和第四晶体管T34可以与第一晶体管T31一起分摊第一节点Q1与参考电压信号Vss输入端之间的电压差。也就是说，第三晶体管T33和第四晶体管T34的配置可以减轻第一晶体管T31源极和汲极间的电压Vds的电压负荷，以减少第一晶体管T31发生漏电流的现象。而且，本实施例中配置了两个晶体管，即第三晶体管T33和第四晶体管T34，对于减轻第一晶体管T31源极和汲极间的电压Vds之电压负荷的效果更为显著，更能有效降低第一晶体管T31发生漏电流的机会，确保第一节点Q1上之高电压不受影响。
藉由本发明上述实施例可以理解到，本发明通过在第一晶体管和参考电压信号输入端之间串联至少一晶体管，如第三晶体管和第四晶体管，以将第一晶体管源极和汲极间的电压负荷分摊到该至少一晶体管上，藉此当第一节点上处于高电压状态时，第一晶体管不致受此影响而产生漏电流使得第一节点上之电压降低，进而使得像素驱动电压不足，因此本发明能够有效解决闸极驱动电路之驱动电压稳定性的问题，提高闸极驱动电路的可靠度，进一步提升显示面板的画面显示品质。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
工业实用性
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Claims (14)

  1. 一种显示器的闸极驱动电路，所述电路包含：
    一第一节点，其在一起始信号通过时具有一电压水平；
    一第一晶体管，其耦接于该第一节点和一参考电压信号输入端，当该第一晶体管开启时，该第一节点的电压会被下拉到接近该参考电压信号的电压；
    一第二晶体管，其一端与该第一晶体管电性连接，另一端与该参考电压信号输入端电性连接；
    一第二节点，位于该第一晶体管和该第二晶体管的连接端；
    一电容，设置于该第二节点和一时脉信号输入端，该第一晶体管、该第二晶体管和该电容用于抑制杂讯的产生；以及
    一第三晶体管，设置于该第一晶体管和该参考电压信号输入端之间，该第三晶体管与该第一晶体管串联连接，用于与该第一晶体管分摊该第一节点与该参考电压信号输入端之间的电压差。
  2. 根据权利要求1所述的显示器的闸极驱动电路，其中该第一晶体管的闸极与该第三晶体管的闸极电性连接。
  3. 根据权利要求1所述的显示器的闸极驱动电路，更包含：
    一第四晶体管，设置於该第三晶体管和该参考电压信号输入端之间，该第四晶体管与该第三晶体管串联连接，用于与该第一晶体管和该第三晶体管分摊该第一节点与该参考电压信号输入端之间的电压差。
  4. 根据权利要求3所述的显示器的闸极驱动电路，其中该第三晶体管的闸极与该第四晶体管的闸极电性连接。
  5. 根据权利要求1所述的显示器的闸极驱动电路，其中该第二晶体管的闸极电性连接至该第一节点。
  6. 一种显示器的闸极驱动电路，所述电路包含：
    一第一晶体管，该第一晶体管的第一端耦接至提供一高电位的一第一节点，而该第一晶体管的第二端耦接至一参考电压信号输入端；
    一第二晶体管，该第二晶体管的第一端与该第一晶体管的第三端电性连接并在其间形成一第二节点，该第二晶体管的第二端耦接至该参考电压信号输入端，而该第二晶体管的第三端耦接至该第一节点；
    一电容，其一端与该第一晶体管和该第二晶体管间的该第二节点电性连接，另一端与一时脉信号输入端电性耦接；以及
    至少一晶体管，设置在该第一晶体管和该参考电压信号输入端之间，该至少一晶体管与该第一晶体管串联连接。
  7. 根据权利要求6所述的显示器的闸极驱动电路，其中该第一晶体管的第三端为闸极，该第一晶体管的闸极与该至少一晶体管的闸极电性连接。
  8. 根据权利要求6所述的显示器的闸极驱动电路，其中当该第一晶体管和该至少一晶体管开启时，该第一节点的电压会被下拉到接近该参考电压信号的电压。
  9. 根据权利要求6所述的显示器的闸极驱动电路，其中该第一晶体管的第三端为闸极，而该第二晶体管的第一端为源极或汲极。
  10. 根据权利要求6所述的显示器的闸极驱动电路，其中该第一晶体管、该第二晶体管和该至少一晶体管为非晶硅晶体管。
  11. 一种显示器的闸极驱动电路，所述电路包含：
    一第一节点，其会根据一起始信号和一时脉信号，将一高电压水平的驱动信号传送到一输出端，该输出端电性连接至一闸极线；
    一第一晶体管，该第一晶体管的第一端耦接至该第一节点，而该第一晶体管的第二端耦接至一参考电压信号输入端；
    一第二晶体管，该第二晶体管的第一端与该第一晶体管的第三端电性连接，该第二晶体管的第二端耦接至该参考电压信号输入端，而该第二晶体管的第三端耦接至该第一节点；
    一第二节点，位于该第一晶体管和该第二晶体管的连接端；
    一电容，其一端与该第一晶体管和该第二晶体管间的该第二节点电性连接，另一端与该时脉信号的输入端电性耦接；以及
    至少一晶体管，设置于该第一晶体管和该参考电压信号输入端之间，该至少一晶体管与该第一晶体管串联连接。
  12. 根据权利要求11所述的显示器的闸极驱动电路，更包含：
    一起始晶体管，设置于该起始信号之输入端和该第一节点之间；以及
    一时脉晶体管，设置于该时脉信号之输入端和该第一节点之间。
  13. 根据权利要求11所述的显示器的闸极驱动电路，更包含：
    一存储电容，设置于该第一节点和该输出端之间。
  14. 根据权利要求11所述的显示器的闸极驱动电路，更包含：
    一第一下拉晶体管，设置于该第一节点和该参考电压信号输入端之间；以及
    一第二下拉晶体管，设置于该输出端和该参考电压信号输入端之间，其中当该第一下拉晶体管和该第二下拉晶体管基于一重置信号而导通时，会将该第一节点和该输出端的电压下拉至该参考电压信号输入端的电压。
PCT/CN2012/073516 2012-03-30 2012-04-05 显示器的闸极驱动电路 Ceased WO2013143157A1 (zh)

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