Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/45—Differential amplifiers
  • H03F3/45071—Differential amplifiers with semiconductor devices only
  • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
  • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/45—Differential amplifiers
  • H03F3/45071—Differential amplifiers with semiconductor devices only
  • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
  • H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
  • H03F3/45968—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction
  • H03F3/45973—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction by using a feedback circuit
  • H03F3/45977—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction by using a feedback circuit using switching means, e.g. sample and hold
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45461—Indexing scheme relating to differential amplifiers the CSC comprising one or more switched capacitors
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
  • H03F2203/45—Indexing scheme relating to differential amplifiers
  • H03F2203/45551—Indexing scheme relating to differential amplifiers the IC comprising one or more switched capacitors

Definitions

• This is directed, in general, to an auto-zeroed amplifier and, more specifically, to an auto-zeroed amplifier with a low leakage into the offset-hold capacitor.
• FIG. 1 illustrates a prior art auto-zeroed amplifier 100.
• auto-zeroed amplifiers are often used to decrease amplifier voltage offset.
• a Vin 105 is coupled to a switch S2 115.
• the switch S2 1 15 is coupled to a node 119, which is in turn coupled to a non-inverting input of an amplifier auto-zeroed ("AO") 140.
• a Vout 180 of the amplifier AO 140 is coupled to a switch S5 170 through a node 181.
• the switch S5 170 is coupled into an inverting input of the amplifier AO 140 through a node 151.
• the node 181 is also coupled to resistor Rl 160.
• the resistor Rl 160 is coupled to a node 111, and the node 111 is coupled to a switch SI 110 and a resistor R2 120.
• the switch SI 110 is coupled to a node 117.
• the resistor R2 120 is coupled to a node 121, and from the node 121 to a ground 122.
• the node 121 is also coupled to a negative terminal of a voltage source 130, a positive terminal of which is coupled to a node 131.
• the node 131 is in turn coupled to a switch S3 133, and also to a switch S4 135.
• the switch S3 133 is coupled to the switch SI 110 through the node 117, and the switch S4 135 is coupled to the switch S2 115 at a node 119, which is in turn coupled to a non-inverting input of the amplifier AO 140.
• a capacitor AZ 150 is coupled between the node 117 and the node 151.
• the auto-zeroed amplifier 100 can work as follows:
• the auto-zeroed amplifier 100 is in an "auto-offset” configuration and an offset of amplifier AO 140 is integrated over capacitor AZ 150.
• FIG. 2 illustrates a prior art sample / long hold system.
• a Vin 205 is coupled to a switch SO 210.
• the switch SO 210 is coupled to a node 212.
• a switch SI 215 is also coupled to the node 212.
• a switch S2 220 is also coupled to the node 212, as is its body diode.
• the switch SI 215 is coupled to a node 217, and the node 217 is coupled to an inverting input of an amplifier AO 230.
• the node 217 is also coupled to a Vout 235 of the amplifier AO 230.
• the switch S2 220 is coupled to a node 222.
• the node 222 is coupled to a capacitor CO 225 and a non-inverting input of the amplifier AO 230.
• the capacitor CO 225 is also coupled to a ground 227.
• the sample/long hold 200 can work as follows:
• the switch 210, and 220 are closed, which conveys the voltage Vin 205 to both the capacitor CO 225 and the non-inverting input of the amplifier AO 230.
• the amplifier AO 230 is a unity gain amplifier, as output 235 is shorted to the inverting input 217.
• FIG. 1 with the sample and hold of FIG. 2 that addresses at least some of the concerns of the usage of the prior art.
• a first aspect provides an apparatus, comprising: an amplifier having an inverting input and a non-inverting input; a capacitor coupled to the inverting input of the amplifier; an input voltage conveyance control circuit, having a first switch and a second switch, the first switch coupled to the capacitor, and the second switch coupled to the non-inverting input of the amplifier; a reference voltage conveyance control circuit having a third switch and a fourth switch, wherein a shared node is coupled between the third switch and the fourth switch, the fourth switch coupled to the non-inverting input of the amplifier; a fifth switch coupled to an output of the amplifier; a leakage control circuit having a sixth switch and a seventh switch, the sixth switch coupled between the inverting amplifier input and the fifth switch, the seventh switch coupled to the sixth switch and the capacitor; and a first resistor coupled from the output of the amplifier to the first switch.
• a second aspect provides a system including an auto-zeroed amplifier system having an inverting input and a non-inverting input, the system comprising: a capacitor coupled to the inverting input of the auto-zeroed amplifier; an input voltage conveyance control circuitry, having a first switch and a second switch, the first switch coupled to the capacitor, and the second switch coupled to the non-inverting input of the auto-zeroed amplifier; a reference voltage conveyance control circuit having a third switch and a fourth switch, wherein a shared node is coupled between the third switch and the fourth switch, the fourth switch coupled to the non-inverting input of the amplifier; a fifth switch coupled to the output of the auto-zeroed amplifier; a leakage control circuit comprising a sixth switch and a seventh switch, the sixth switch coupled between the inverting auto-zeroed amplifier and the fifth switch, the seventh switch coupled to the sixth switch and the capacitor; a first resistor coupled from the output of the auto-zeroed amplifier to the
• a third aspect provides a system including an auto-zeroed differential amplifier, having an inverting input, a non-inverting input, and a common mode voltage input; the system comprising: a high side auto-zero capacitor coupled to the inverting input of the auto-zeroed amplifier; a low side auto-zeroed capacitor coupled to the inverting input of the auto-zeroed amplifier; high side input voltage conveyance control circuit, having a high side first switch and a high side second switch, the high side first switch coupled to the high side capacitor, and the high side second switch coupled to the non-inverting input of the amplifier; low side input voltage conveyance control circuit, having a low side first switch and a low side second switch, the low side first switch coupled to the low side capacitor, and the low side second switch coupled to the non-inverting input of the amplifier; high side reference voltage conveyance control circuit having a high side third switch and a high side fourth switch, wherein a shared node is coupled between the high side third switch and the
• FIG. 1 illustrates a prior art auto-zeroed amplifier 100
• FIG. 2 illustrates a prior art sample and hold amplifier 200
• FIG. 3 illustrates an auto-zeroed amplifier with a low leakage current 300 constructed according to principles of the invention.
• FIG. 4 illustrates a differential auto-zeroed amplifier with a low leakage current
• FIG. 3 illustrated is one aspect of an auto-zeroed amplifier with a low leakage current 300 constructed according to principles of the present Application.
• a voltage across a switch S7 397 of a leakage control circuit 399 is enabled and disabled in inverse phases "F2", "Fl” to a coupled switch S6 395 of the leakage control circuit 399, thereby limiting a voltage across the switch S6 395, to a voltage across capacitor AZ 350, thereby substantially reducing the maximum voltage across the switch S6 395 when open.
• Substantially reducing the maximum voltage across switch S6 395 when open during an "F0" phase thereby substantially decreases its leakage current to the capacitor AZ 350, thereby substantially increasing operating parameters of an F0 operation time.
• the auto-zeroed amplifier 300 allows for a significant increase in length of an "F0" on time, when compared to the prior art amplifiers 100 and 200, which can be from 10's of us to 10's of ms
• a Vin 305 is coupled to a switch S2 315.
• the switch S2 315 is coupled to a node 319, which is in turn coupled to non-inverting input of an auto-zeroed amplifier 340.
• a Vout 380 of the auto-zeroed amplifier 380 is coupled to a switch S5 370 through a node 381.
• the switch S5 370 is coupled into a leakage control circuit 399.
• the various switches of the auto-zeroed amplifier 300 can be, for example, PMOS switches.
• the leakage control circuit 399 includes a node 358 coupled to the switch S5 370.
• the node 358 is also coupled to a switch S7 397 within the leakage control circuit 399.
• the switch S7 397 is coupled to a node 317.
• the switch S6 395 also within the leakage control circuit 399, is coupled to a node 356.
• the nodes 317 and 356 are coupled to the capacitor AZ 350, which is used for integration of offset of amplifier 300 during F0.
• the node 381 is also coupled to a feedback resistor Rl 360.
• the feedback resistor Rl 360.
• Rl 360 is coupled to a node 311, the node 311 is coupled to both a switch SI 310 of an input voltage conveyance control circuit 309 and a resistor R2 320.
• the switch SI 310 is coupled to the node 317.
• the resistor R2 320 is coupled to a node 321, and from a node 321 to a ground 322.
• the node 321 is also coupled to a negative terminal of a voltage source 330, a positive terminal of which is coupled to a node 331 of a reference voltage control circuit 318.
• the node 331 is, in turn, coupled to a switch S3 333, and also to a switch S4 335, also in the reference voltage control circuit 318.
• the switch S 333 is coupled to the node 317, and the switch S4 335 is coupled to the node 319.
• the voltage across the capacitor AZ 350 is substantially equal to the amplifier AO offset. Consequently, the voltage across switch S6 395 is also substantially equal to the A) offset, thereby decreasing leakage through the switch S6 395, and therefore substantially increasing hold time between auto-zeroing periods.
• the offfset can be 0-5 mV.
• the auto-zeroed amplifier 300 can work as follows:
• the auto-zeroed amplifier 300 is in an "auto-zero" configuration, and the offset of amplifier AO 340 is integrated over the capacitor AZ 150.
• the switches S3 333 and S4 335 are closed, and therefore convey the reference voltage 330 to the nodes 317 and 319, respectively.
• An offset of the amplifier AO 340 is integrated over the capacitor AZ 350.
• the switch S5 370 and switch S6 395 are closed, thereby inverting the value of the output Vout 380 to a single feedback of substantially unity gain.
• the capacitor AZ 350 is connected in series with the inverting input, as switch S2 315 is closed, Vin 305 is connected to the non-inverting input of the amplifier AO 340, as the switch S2 315 is closed.
• the offset between the inverting and non-inverting inputs of the amplifier AO 340 is therefore integrated over the capacitor AZ 350.
• the switch S7 397 is also closed during "F2", the "low leakage hold phase” configuration. Because of the closing of switch S7 397 during "F2", during “F2” the voltage across the closed switch S7 397 is therefore coupled in parallel to the capacitor AZ 350 and the open S6 switch 395, which therefore applies a limit of a low maximum ceiling of voltage to open switch S6 395.
• limiting the voltage across the switch S6 370 in this circuit when this switch is open changes limits its leakage current, thereby improving functionality of the auto-zeroed amplifier 300.
• FIG. 4 illustrates a differential auto-zeroed amplifier 400.
• Principles of construction and operation of the auto-zeroed amplifier 400 are generally analogous to those of the auto-zeroed amplifier 300, except that the auto-zeroed amplifier 300 is a single-ended amplifier, and the auto-zeroed amplifier 400 is a differential amplifier.
• a positive differential side 401 is mirrored in a negative differential side 403.
• the "Fl" and "F2" phases of the positive differential side 401 can be applied by analogy to the negative differential side 403.
• phase "Fl" a "differential auto zero" configuration of the differential auto-zeroed amplifier 400
• the capacitors AZ 450, 451 are electrically connected between the VCM (input common mode voltage or ground or reference) and amplifier AO 440 out+ and amplifier AO 440 out- through a third high side switch S3 415 and a third low side switch 418 of a differential voltage reference conveyance circuit 414.
• the conveyed reference voltage is the common mode voltage.
• Offsets of the inverting and non- inverting inputs of the amplifier AO 440 are integrated across are integrated across the capacitors AZ 450, 451.
• C2+, C2-? Can have a few pFvalue for small die area.

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• Engineering & Computer Science (AREA)
• Power Engineering (AREA)
• Amplifiers (AREA)

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• 2012
  • 2012-07-25 US US13/557,446 patent/US8810311B2/en active Active
• 2013
  • 2013-03-14 CN CN201380014201.0A patent/CN104170251B/zh active Active
  • 2013-03-14 WO PCT/US2013/031151 patent/WO2013138546A1/en not_active Ceased
  • 2013-03-14 JP JP2015500588A patent/JP6253634B2/ja active Active

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