WO2013091256A1 - 液晶面板的驱动电路及液晶显示器 - Google Patents

液晶面板的驱动电路及液晶显示器 Download PDF

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Publication number
WO2013091256A1
WO2013091256A1 PCT/CN2011/084645 CN2011084645W WO2013091256A1 WO 2013091256 A1 WO2013091256 A1 WO 2013091256A1 CN 2011084645 W CN2011084645 W CN 2011084645W WO 2013091256 A1 WO2013091256 A1 WO 2013091256A1
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Prior art keywords
clock signal
thin film
film transistor
liquid crystal
potential
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PCT/CN2011/084645
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English (en)
French (fr)
Inventor
李仕琦
林师勤
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/381,344 priority Critical patent/US20130162508A1/en
Publication of WO2013091256A1 publication Critical patent/WO2013091256A1/zh
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a driving circuit for a liquid crystal panel and a liquid crystal display.
  • each pixel has a thin film field effect transistor (Thin Film) Transistor (TFT), whose gate is connected to the horizontal scanning line, and the drain or source is connected to the vertical data line.
  • TFT Thin Film field effect transistor
  • the TFT element When a high voltage is applied to the scan line (gate), the TFT element is turned on, and the gray scale voltage can enter the pixel electrode (drain/source) from the data line (source/drain) and pass through the transparent pixel electrode. Applied to the liquid crystal layer, changing the standing angle of the liquid crystal to display a predetermined gray scale
  • the driving circuit for applying voltage on the scanning line is mainly completed by an external driving chip of the liquid crystal panel, but the method of externally driving the chip is not only costly, but also needs to connect the driving chip, thereby increasing the processing time.
  • the prior art generally uses an array substrate row driver (Gate Driver on The Array, GOA) circuit replaces the driver chip and directly fabricates the gate driver circuits (Gate driver ICs) on the array substrate.
  • GOA array substrate row driver
  • FIG. 1 is a structural block diagram of a GOA circuit in the prior art, including a clock signal input terminal 11, and further includes a first thin film transistor 12, a second thin film transistor 13, a third thin film transistor 14, and a fourth thin film transistor 15. And the control terminal 16, further comprising a first pull-down circuit 17 and a second pull-down circuit 18.
  • the size of the first thin film transistor 12 is generally large, and its internal parasitic capacitance (not shown) is relatively large.
  • the control terminal 16 ie, the node
  • the potential is pulled high (or pulled low)
  • the gate of the first thin film transistor 12 is turned on, thereby causing the first thin film transistor 12 to leak, resulting in the first
  • the gate of the thin film transistor 12 outputs a high potential, causing an abnormality in the voltage output to the scanning line Gn, which causes an abnormality in the screen display.
  • the prior art generally lowers the potential of the control terminal 16 by alternately operating the first pull-down circuit 17 and the second pull-down circuit 18 to avoid abnormality of the gate output of the first thin film transistor 12, wherein
  • the pull-down circuit 17 and the second pull-down circuit 18 are composed of a plurality of thin film transistors.
  • the method since the method requires the use of a plurality of thin film transistors to form the two pull-down circuits, the area of the bezel area is increased, and the circuit structure is complicated; and since the characteristics of the thin film transistor are easily changed, the leakage of the two pull-down circuits may be affected.
  • the screen display of the LCD monitor since the method requires the use of a plurality of thin film transistors to form the two pull-down circuits, the area of the bezel area is increased, and the circuit structure is complicated; and since the characteristics of the thin film transistor are easily changed, the leakage of the two pull-down circuits may be affected.
  • the screen display of the LCD monitor since the method requires the use of a plurality of
  • An object of the present invention is to provide a driving circuit for a liquid crystal panel and a liquid crystal display to solve the problem of suppressing the change of the potential of the control terminal by using a plurality of thin film transistors to form a pull-down circuit in the prior art, thereby increasing the frame area.
  • the area makes the circuit structure more complicated; and because the characteristics of the thin film transistor are easily changed, the above-mentioned pull-down circuit is leaked, which affects the technical problem of the display effect of the liquid crystal display.
  • the present invention constructs a driving circuit for a liquid crystal panel, comprising a first clock signal terminal for inputting a first clock signal, further comprising a first thin film transistor and a control terminal; the control terminal is connected to a gate of the first thin film transistor The first thin film transistor is disposed between the control terminal and the first clock signal end;
  • the driving circuit of the liquid crystal panel further includes a second clock signal end for inputting a second clock signal, the first clock signal end is connected to a source or a drain of the first thin film transistor, and the control terminal is disposed at Between the first thin film transistor and the second clock signal end, a suppression capacitor is further disposed between the second clock signal end and the control terminal;
  • the first clock signal has a first high potential and a first low potential
  • the second clock signal has a second high potential and a second low potential
  • the first clock signal and the second clock signal have the same a signal period
  • the suppression capacitor is configured to suppress a potential of the control terminal when a potential of the first clock signal changes, and when the second clock signal changes opposite to a potential change of the first clock signal The change.
  • the second clock signal is converted by the second low potential when the first clock signal is switched from the first high potential to the first low potential in the same signal period. Going to a second high potential; when the first clock signal is switched from the first low potential to the first high potential, the second clock signal is switched from the second high potential to the second low potential.
  • the driving circuit of the liquid crystal panel of the present invention further includes a second thin film transistor, a third thin film transistor, and a fourth thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film. Transistors are all connected to the control terminals.
  • Another object of the present invention is to provide a driving circuit for a liquid crystal panel, which solves the problem of suppressing the change of the potential of the control terminal by using a plurality of thin film transistors to form a pull-down circuit in the prior art, thereby increasing the area of the bezel area and making the circuit
  • the structure is relatively complicated; and because the characteristics of the thin film transistor are easily changed, the above-mentioned pull-down circuit may leak, which may affect the technical display effect of the liquid crystal display screen.
  • the present invention constructs a driving circuit for a liquid crystal panel, including a first clock signal terminal for inputting a first clock signal, and further includes a first thin film transistor and a control terminal; the control terminal is connected to the first a gate of a thin film transistor, the first thin film transistor being disposed between the control terminal and the first clock signal end;
  • the driving circuit of the liquid crystal panel further includes a second clock signal end for inputting a second clock signal, the control terminal being disposed between the first thin film transistor and the second clock signal end, the second A suppression capacitor is further disposed between the clock signal end and the control terminal;
  • the second clock signal is opposite to the potential of the first clock signal
  • the suppression capacitor is used to change a potential of the first clock signal
  • the second clock signal occurs with the
  • the first clock signal terminal is connected to a source or a drain of the first thin film transistor.
  • the first clock signal has a first high potential and a first low potential
  • the second clock signal has a second high potential and a second low potential
  • the first clock The signal and the second clock signal have the same signal period.
  • the second clock signal is converted by the second low potential when the first clock signal is switched from the first high potential to the first low potential in the same signal period. Going to a second high potential; when the first clock signal is switched from the first low potential to the first high potential, the second clock signal is switched from the second high potential to the second low potential.
  • the driving circuit of the liquid crystal panel of the present invention further includes a second thin film transistor, a third thin film transistor, and a fourth thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film. Transistors are all connected to the control terminals.
  • a further object of the present invention is to provide a liquid crystal display to solve the problem in the prior art that a plurality of thin film transistors are used to form a pull-down circuit to suppress a change in potential of a control terminal, thereby increasing the area of the bezel area and making the circuit structure more complicated. Moreover, since the characteristics of the thin film transistor are easily changed, the above-mentioned pull-down circuit may leak, which may affect the technical display effect of the liquid crystal display screen.
  • the present invention constructs a liquid crystal display including a driving circuit of a liquid crystal panel, the driving circuit of the liquid crystal panel includes a first clock signal end for inputting a first clock signal, and further includes a first thin film transistor and a control terminal; the control terminal is connected to a gate of the first thin film transistor, and the first thin film transistor is disposed between the control terminal and the first clock signal end;
  • the driving circuit of the liquid crystal panel further includes a second clock signal end for inputting a second clock signal, the control terminal being disposed between the first thin film transistor and the second clock signal end, the second A suppression capacitor is further disposed between the clock signal end and the control terminal;
  • the second clock signal is opposite to the potential of the first clock signal
  • the suppression capacitor is used to change a potential of the first clock signal
  • the second clock signal occurs with the
  • the first clock signal terminal is connected to a source or a drain of the first thin film transistor.
  • the first clock signal has a first high potential and a first low potential
  • the second clock signal has a second high potential and a second low potential
  • the first clock signal and the The second clock signal has the same signal period.
  • the second clock signal is switched from the second low potential to the second when the first clock signal is switched from the first high potential to the first low potential in the same signal period a high potential; the second clock signal is switched from a second high potential to a second low potential when the first clock signal is switched from the first low potential to the first high potential.
  • the driving circuit of the liquid crystal panel further includes a second thin film transistor, a third thin film transistor, and a fourth thin film transistor, and the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are connected The control terminal.
  • the present invention switches from a low potential to a high potential (or from a high potential) by setting a second clock signal terminal and providing a suppression capacitor between the second clock signal terminal and the control terminal. Switching to low potential) while the second clock signal is switched from high to low (or from low to high), pulling down (or pulling high) the potential of the control terminal without passing through multiple thin film transistors
  • the pull-down circuit is formed to suppress the change of the potential of the control terminal, the area of the frame area is saved, the circuit structure is simplified, the leakage of the pull-down circuit due to the change of the characteristics of the thin film transistor is avoided, and the screen display effect of the liquid crystal display is improved.
  • FIG. 1 is a schematic structural view of an array substrate row driving circuit in the prior art
  • FIG. 2 is a schematic structural view of a first preferred embodiment of a driving circuit of a liquid crystal panel according to the present invention
  • FIG. 3 is a schematic structural view of a second preferred embodiment of a driving circuit of a liquid crystal panel according to the present invention.
  • FIGS. 2 and 3 are partial simulation views of a driving circuit of the liquid crystal panel shown in FIGS. 2 and 3.
  • FIG. 5 is a schematic diagram of signal periods of a first clock signal and a second clock signal in the present invention.
  • FIG. 2 is a structural block diagram of a first preferred embodiment of a driving circuit of a liquid crystal panel according to the present invention.
  • the driving circuit of the liquid crystal panel includes a first clock signal input terminal 21, a second clock signal input terminal 22, a first thin film transistor 23, a second thin film transistor 24, a third thin film transistor 25, a fourth thin film transistor 26, and a control terminal. 27 and the suppression capacitor 28.
  • the first clock signal terminal 21 is connected to the source or the drain of the first thin film transistor 23 (not shown); the second clock signal terminal 22 is connected to the control terminal 27; the suppression capacitor 28 is disposed at the second clock signal terminal 22 and is controlled. Between terminals 27.
  • the control terminal 27 is connected to the gate of the first thin film transistor 23 (not shown). Of course, the control terminal 27 is also connected to the second thin film transistor 24, the third thin film transistor 25, and the fourth thin film transistor 26. Since it is a mature technology, it will not be described in detail herein.
  • FIG. 4 is a partial schematic view of the driving circuit of the liquid crystal panel shown in FIG. 2.
  • a parasitic capacitance 231 is formed in the first thin film transistor 23, and the parasitic capacitance 231 is located between the first clock signal input end 21 and the control terminal 27; it is not difficult to see from the above description and the drawings that the control terminal 27 is located. Between the parasitic capacitance 231 and the suppression capacitor 28.
  • the first clock signal input terminal 21 is configured to input a first clock signal
  • the first clock signal has a first high potential and a first low potential
  • the second clock signal input terminal 22 is configured to input a second clock signal.
  • the second clock signal has a second high potential and a second low potential.
  • the first clock signal input terminal 21 and the second clock signal input terminal 22 generate a first clock signal and a second clock signal in the same signal period. In the same signal period, the first clock signal terminal 21 and the second clock signal terminal 22 alternately input high-potential and low-potential clock signals.
  • FIG. 5 is a schematic diagram of a preferred embodiment of a signal period of a first clock signal and a second clock signal in the present invention.
  • the second clock signal terminal 22 In the same signal period T, when the first clock signal input terminal 21 generates the first clock signal CK of the first high potential H1, the second clock signal terminal 22 generates the second clock signal XCK of the second low potential L2; When a clock signal input terminal 21 generates the first clock signal CK of the first low potential L1, the second clock signal terminal 22 generates a second clock signal XCK of the second high potential H2.
  • the second clock signal XCK input from the second clock signal terminal 22 is converted from the second low potential L2 to The second high potential H2.
  • the first clock signal CK is switched from the first high potential H1 to the first low potential L1, so that the parasitic capacitance 231 in the first thin film transistor 23 generates a coupling effect, and the size of the parasitic capacitance 231 is large, so that the potential of the control terminal 27 Pull up.
  • the second clock signal XCK is converted from the second low potential L2 to the second high potential H2, so that the suppression capacitor 28 generates a coupling effect, thereby causing the potential of the control terminal 27 to be pulled low.
  • the second clock signal XCK is converted from the second high potential H2 to the second low potential L2. Due to the potential conversion of the first clock signal CK, the parasitic capacitance 231 is internally coupled, thereby causing the potential of the control terminal 27 to be pulled low. At this time, since the second clock signal XCK performs an opposite potential conversion, the internal coupling of the capacitor 28 is suppressed, thereby The potential of the control terminal 27 is pulled high.
  • the suppression capacitor 28 can effectively suppress the change of the potential of the control terminal 27, cancel the influence of the coupling of the parasitic capacitance 231 on the potential of the control terminal 27, and maintain the stability of the potential of the control terminal 27, thereby ensuring the output to the scan.
  • the voltage of line Gn remains normal.
  • the invention also saves the area of the frame area, simplifies the circuit structure, avoids the problem of leakage of the pull-down circuit due to the change of the characteristics of the thin film transistor, and improves the screen display effect of the liquid crystal display.
  • FIG. 5 shows a preferred embodiment.
  • the first high potential H1 and the first low potential L1 are each 50% of a signal period T
  • the second The low potential L2 and the second high potential H2 are each also 50% of a signal period T such that when the first clock signal changes, the second clock signal simultaneously produces an opposite change.
  • the first clock signal and the second clock signal may also be distributed according to other time ratios.
  • the first low potential L1 and the second low potential L2 may each occupy 60% of the period T, Then, the first high potential H1 and the second high potential H2 each occupy 40% of the period T.
  • the suppression control terminal 27 can be achieved. The effect of the potential change.
  • FIG. 3 is a structural block diagram of a second preferred embodiment of a driving circuit of a liquid crystal panel according to the present invention, which is different from the first preferred embodiment shown in FIG.
  • a pull-down circuit 31 is further included.
  • the first clock signal CK when the first clock signal CK is switched from the first high potential H1 to the first low potential L1, the potential of the control terminal 27 is pulled up. At this time, the pull-down circuit 31 and the suppression capacitor 28 are common. Acting, the potential of the control terminal 27 is pulled low.
  • the second preferred embodiment Compared with the first pull-down circuit 17 and the second pull-down circuit 18 shown in FIG. 1 , the second preferred embodiment only provides one pull-down circuit 31 and cooperates with the suppression capacitor 28 through the pull-down circuit 31.
  • the first clock signal CK is switched from the first high potential H1 to the first low potential L1, the potential of the control terminal 27 is pulled low.
  • this second preferred embodiment not only simplifies the circuit architecture, but also saves the area of the bezel area.
  • the principle of the second preferred embodiment shown in FIG. 3 is similar to the principle of the first preferred embodiment shown in FIG. 2, and details are not described herein again.
  • the present invention also provides a liquid crystal display comprising the driving circuit of the liquid crystal panel provided by the present invention. Since the circuit has been described in detail above, it will not be described herein.

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  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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Abstract

一种液晶面板的驱动电路及液晶显示器。所述液晶面板的驱动电路包括用于输入第一时钟信号的第一时钟信号端（21），用于输入第二时钟信号的第二时钟信号端（22），还包括第一薄膜晶体管（23）和控制端子（27）；控制端子（27）设置于第一薄膜晶体管（23）和第二时钟信号端（22）之间，所述第二时钟信号端（22）和控制端子（27）之间还设置一抑制电容（28）；抑制电容（28）用于在第一时钟信号的电位发生变化，第二时钟信号发生与第一时钟信号的电位变化相反的变化时，抑制控制端子（27）的电位变化。所述液晶面板的驱动电路节省了边框区的面积，简化了电路架构，提高了液晶显示器的画面显示效果。

Description

液晶面板的驱动电路及液晶显示器 技术领域
本发明涉及液晶显示技术领域，特别是涉及一种液晶面板的驱动电路及液晶显示器。
 背景技术
随着液晶技术的不断发展，对液晶面板内各部件的要求越来越高。
在主动式矩阵液晶显示器中，每个像素具有一个薄膜场效应晶体管(Thin Film Transistor，TFT)，其栅极(Gate)连接至水平方向扫描线，漏极(Drain)或者源极（Source）连接至垂直方向的数据线。
当在扫描线（栅极）上施以高电压时，TFT元件打开，灰阶电压就能从数据线（源极/漏极）进入像素电极（漏极/源极），并经由透明像素电极施加于液晶层上，改变液晶的站立角度从而显示预定灰阶
若在水平方向的某一条扫描线施加足够的正电压，会使得该条扫描线所有的TFT打开，此时该条扫描线对应的像素电极与垂直方向的数据线连接，进而将数据线的信号电压写入像素中，并经由像素电极施加于对应的液晶层上，改变液晶的站立角度从而达到控制色彩的效果。目前在扫描线施加电压的驱动电路主要是由液晶面板外接驱动芯片来完成，但是外接驱动芯片的方式不仅成本高，而且需要对驱动芯片进行连接，增加了制程时间。
为了解决上述问题，现有技术一般采用阵列基板行驱动（Gate Driver on Array，GOA）电路替代驱动芯片，直接将栅极驱动电路(Gate driver ICs)制作在阵列基板上。
请参阅图1，图1为现有技术中GOA电路的结构框图，包括时钟信号输入端11，还包括第一薄膜晶体管12、第二薄膜晶体管13、第三薄膜晶体管14、第四薄膜晶体管15以及控制端子16，还包括第一下拉电路17以及第二下拉电路18。
由于需要满足电阻-电容拉升的要求，第一薄膜晶体管12的尺寸通常比较大，其内部寄生电容（图未标示）也相对较大。当时钟信号端11输入的时钟信号由低电位切换到高电位时（或者由高电位切换到低电位），由于第一薄膜晶体管13内部寄生电容耦合的作用，使得控制端子16（即节点）的电位被拉高（或者被拉低），一旦控制端子16的电位被拉高到一定的程度，将会使得第一薄膜晶体管12的栅极打开，从而使得第一薄膜晶体管12漏电，造成第一薄膜晶体管12的栅极输出高电位，造成输出到扫描线Gn的电压异常，进而导致画面显示异常。
为了避免上述问题，现有技术一般是通过第一下拉电路17以及第二下拉电路18交替运行来拉低控制端子16的电位，避免第一薄膜晶体管12的栅极输出异常，其中，第一下拉电路17以及第二下拉电路18采用多个薄膜晶体管组成。但是由于该方式需要使用多个薄膜晶体管组成上述两个下拉电路，增加了边框区的面积，使得电路架构比较复杂；而且由于薄膜晶体管的特性容易发生变化，会导致上述两个下拉电路漏电，影响液晶显示器的画面显示效果。
 技术问题
本发明的一个目的在于提供一种液晶面板的驱动电路以及一种液晶显示器，以解决现有技术中由于需要使用多个薄膜晶体管组成下拉电路来抑制控制端子的电位的变化，增加了边框区的面积，使得电路架构比较复杂；而且由于薄膜晶体管的特性容易发生变化，会导致上述下拉电路漏电，影响液晶显示器画面显示效果的技术问题。
 技术解决方案
本发明构造了一种液晶面板的驱动电路，包括用于输入第一时钟信号的第一时钟信号端，还包括第一薄膜晶体管和控制端子；所述控制端子连接所述第一薄膜晶体管的栅极，所述第一薄膜晶体管设置于所述控制端子和所述第一时钟信号端之间；
所述液晶面板的驱动电路还包括用于输入第二时钟信号的第二时钟信号端，所述第一时钟信号端连接所述第一薄膜晶体管的源极或者漏极，所述控制端子设置于所述第一薄膜晶体管和所述第二时钟信号端之间，所述第二时钟信号端和所述控制端子之间还设置一抑制电容；
所述第一时钟信号具有第一高电位和第一低电位，所述第二时钟信号具有第二高电位和第二低电位，所述第一时钟信号和所述第二时钟信号具有相同的信号周期；所述抑制电容用于在所述第一时钟信号的电位发生变化，所述第二时钟信号发生与所述第一时钟信号的电位变化相反的变化时，抑制所述控制端子的电位的变化。
在本发明的液晶面板的驱动电路中，在同一个信号周期内，在所述第一时钟信号由第一高电位转换到第一低电位时，所述第二时钟信号由第二低电位转换到第二高电位；在所述第一时钟信号由第一低电位转换到第一高电位时，所述第二时钟信号由第二高电位转换到第二低电位。
在本发明的液晶面板的驱动电路中，所述液晶面板的驱动电路还包括第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管，所述第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管均连接所述控制端子。
本发明的另一个目的在于提供一种液晶面板的驱动电路，以解决现有技术中由于需要使用多个薄膜晶体管组成下拉电路来抑制控制端子的电位的变化，增加了边框区的面积，使得电路架构比较复杂；而且由于薄膜晶体管的特性容易发生变化，会导致上述下拉电路漏电，影响液晶显示器画面显示效果的技术问题。
为解决上述问题，本发明构造了一种液晶面板的驱动电路，包括用于输入第一时钟信号的第一时钟信号端，还包括第一薄膜晶体管和控制端子；所述控制端子连接所述第一薄膜晶体管的栅极，所述第一薄膜晶体管设置于所述控制端子和所述第一时钟信号端之间；
所述液晶面板的驱动电路还包括用于输入第二时钟信号的第二时钟信号端，所述控制端子设置于所述第一薄膜晶体管和所述第二时钟信号端之间，所述第二时钟信号端和所述控制端子之间还设置一抑制电容；
在同一时刻，所述第二时钟信号与所述第一时钟信号的电位相反，所述抑制电容，用于在所述第一时钟信号的电位发生变化，所述第二时钟信号发生与所述第一时钟信号的电位变化相反的变化时，抑制所述控制端子的电位的变化。
在本发明的液晶面板的驱动电路中，所述第一时钟信号端连接所述第一薄膜晶体管的源极或者漏极。
在本发明的液晶面板的驱动电路中，所述第一时钟信号具有第一高电位和第一低电位；所述第二时钟信号具有第二高电位和第二低电位；所述第一时钟信号和所述第二时钟信号具有相同的信号周期。
在本发明的液晶面板的驱动电路中，在同一个信号周期内，在所述第一时钟信号由第一高电位转换到第一低电位时，所述第二时钟信号由第二低电位转换到第二高电位；在所述第一时钟信号由第一低电位转换到第一高电位时，所述第二时钟信号由第二高电位转换到第二低电位。
在本发明的液晶面板的驱动电路中，所述液晶面板的驱动电路还包括第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管，所述第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管均连接所述控制端子。
本发明的又一个目的在于提供一种液晶显示器，以解决现有技术中由于需要使用多个薄膜晶体管组成下拉电路来抑制控制端子的电位的变化，增加了边框区的面积，使得电路架构比较复杂；而且由于薄膜晶体管的特性容易发生变化，会导致上述下拉电路漏电，影响液晶显示器画面显示效果的技术问题。
为解决上述问题，本发明构造了一种液晶显示器，所述液晶面板包括一液晶面板的驱动电路，所述液晶面板的驱动电路包括用于输入第一时钟信号的第一时钟信号端，还包括第一薄膜晶体管和控制端子；所述控制端子连接所述第一薄膜晶体管的栅极，所述第一薄膜晶体管设置于所述控制端子和所述第一时钟信号端之间；
所述液晶面板的驱动电路还包括用于输入第二时钟信号的第二时钟信号端，所述控制端子设置于所述第一薄膜晶体管和所述第二时钟信号端之间，所述第二时钟信号端和所述控制端子之间还设置一抑制电容；
在同一时刻，所述第二时钟信号与所述第一时钟信号的电位相反，所述抑制电容，用于在所述第一时钟信号的电位发生变化，所述第二时钟信号发生与所述第一时钟信号的电位变化相反的变化时，抑制所述控制端子的电位的变化。
在本发明的液晶显示器中，所述第一时钟信号端连接所述第一薄膜晶体管的源极或者漏极。
在本发明的液晶显示器中，所述第一时钟信号具有第一高电位和第一低电位；所述第二时钟信号具有第二高电位和第二低电位；所述第一时钟信号和所述第二时钟信号具有相同的信号周期。
在本发明的液晶显示器中，在同一个信号周期内，在所述第一时钟信号由第一高电位转换到第一低电位时，所述第二时钟信号由第二低电位转换到第二高电位；在所述第一时钟信号由第一低电位转换到第一高电位时，所述第二时钟信号由第二高电位转换到第二低电位。
在本发明的液晶显示器中，所述液晶面板的驱动电路还包括第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管，所述第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管均连接所述控制端子。
 有益效果
本发明相对于现有技术，通过设置第二时钟信号端，并在第二时钟信号端和控制端子之间设置一抑制电容，在第一时钟信号从低电位切换到高电位（或者从高电位切换到低电位），同时第二时钟信号从高电位切换到低电位（或者从低电位切换到高电位）时，拉低（或者拉高）所述控制端子的电位，无须通过多个薄膜晶体管组成下拉电路来抑制控制端子的电位的变化，节省了边框区的面积，简化了电路架构，避免了由于薄膜晶体管的特性发生变化造成的下拉电路漏电的问题，提高了液晶显示器的画面显示效果。
 附图说明
图1为现有技术中阵列基板行驱动电路的结构示意图；
图2为本发明中液晶面板的驱动电路的第一较佳实施例结构示意图；
图3为本发明中液晶面板的驱动电路的第二较佳实施例结构示意图；
图4为图2和图3所示的液晶面板的驱动电路的部分模拟图；
图5为本发明中第一时钟信号和第二时钟信号的信号周期示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。
请参阅图2，图2为本发明中液晶面板的驱动电路的第一较佳实施例的结构框图。
所述液晶面板的驱动电路包括第一时钟信号输入端21，第二时钟信号输入端22，第一薄膜晶体管23，第二薄膜晶体管24，第三薄膜晶体管25，第四薄膜晶体管26、控制端子27以及抑制电容28。
第一时钟信号端21连接所述第一薄膜晶体管23的源极或者漏极（图未标示）；第二时钟信号端22连接控制端子27；抑制电容28设置于第二时钟信号端22和控制端子27之间。
控制端子27连接所述第一薄膜晶体管23的栅极（图未标示）。当然，控制端子27还连接所述第二薄膜晶体管24、第三薄膜晶体管25以及第四薄膜晶体管26，鉴于为成熟技术，此处不再详述。
请参阅图4，图4为图2所示的液晶面板的驱动电路的部分模拟图。在具体实施过程中，第一薄膜晶体管23内形成有寄生电容231，寄生电容231位于第一时钟信号输入端21和控制端子27之间；从上述描述及附图不难看出，控制端子27位于寄生电容231和抑制电容28之间。
在具体实施过程中，第一时钟信号输入端21用于输入第一时钟信号，第一时钟信号具有第一高电位和第一低电位；第二时钟信号输入端22用于输入第二时钟信号，第二时钟信号具有第二高电位和第二低电位。
其中，第一时钟信号输入端21和第二时钟信号输入端22在相同信号周期内产生第一时钟信号和第二时钟信号。在同一信号周期内，第一时钟信号端21和第二时钟信号端22交替输入高电位和低电位的时钟信号。
请参阅图5，图5为本发明中第一时钟信号和第二时钟信号的信号周期较佳实施例示意图。
在同一信号周期T内，第一时钟信号输入端21产生第一高电位H1的第一时钟信号CK时，第二时钟信号端22产生所述第二低电位L2的第二时钟信号XCK；第一时钟信号输入端21产生第一低电位L1的第一时钟信号CK时，第二时钟信号端22产生第二高电位H2的第二时钟信号XCK。
本发明提供的液晶面板的驱动电路的第一较佳实施例的工作原理为：
在第一时钟信号端21输入的第一时钟信号CK由第一高电位H1转换到第一低电位L1时，第二时钟信号端22输入的第二时钟信号XCK由第二低电位L2转换为第二高电位H2。
第一时钟信号CK由第一高电位H1转换到第一低电位L1，使得所述第一薄膜晶体管23内寄生电容231产生耦合效应，而且寄生电容231的尺寸较大，使得控制端子27的电位拉升。此时，第二时钟信号XCK由第二低电位L2转换为第二高电位H2，使得抑制电容28产生耦合效应，进而使得控制端子27的电位拉低。
在第一时钟信号CK由第一低电位L1转换到第一高电位H1时，第二时钟信号XCK由第二高电位H2转换为第二低电位L2。由于第一时钟信号CK的电位转换，寄生电容231内部耦合，进而使得控制端子27的电位拉低，此时，由于第二时钟信号XCK进行一相反的电位转换，抑制电容28内部耦合，进而使得控制端子27的电位拉高。
显然，抑制电容28可以有效地抑制控制端子27的电位的变化，抵消了由于寄生电容231的耦合对控制端子27的电位造成的影响，保持了控制端子27电位的稳定，进而保证了输出到扫描线Gn的电压保持正常。而且，本发明还节省了边框区的面积，简化了电路架构，避免了由于薄膜晶体管的特性发生变化造成的下拉电路漏电的问题，提高了液晶显示器的画面显示效果。
其中，图5所示的为一较佳实施例，在该较佳实施例的一信号周期T内，第一高电位H1和第一低电位L1各自为一信号周期T的50%，第二低电位L2和第二高电位H2同样各自为一信号周期T的50%，这样在第一时钟信号变化时，第二时钟信号同时产生一相反变化。当然，在一个周期T内，第一时钟信号和第二时钟信号还可以按照其它的时间比例分布，譬如，第一低电位L1和第二低电位L2还可以各自占所在周期T的60%，则第一高电位H1和第二高电位H2各自占所在周期T的40%，此时，虽然第一时钟信号的变化和第二时钟信号的变化不同时进行，但仍能达到抑制控制端子27的电位变化的效果。
请参阅图3，图3为本发明中液晶面板的驱动电路的第二较佳实施例的结构框图，与图2所示的第一较佳实施例不同之处在于，在图3所示的第二较佳实施例中，还包括下拉电路31。
在具体实施过程中，第一时钟信号CK由第一高电位H1转换到第一低电位L1时，使得控制端子27的电位拉升，此时，所述下拉电路31与所述抑制电容28共同作用，将控制端子27的电位拉低。
该第二较佳实施例相对图1所示的第一下拉电路17以及第二下拉电路18相比，仅仅设置一个下拉电路31，并通过该下拉电路31与所述抑制电容28的共同作用，在第一时钟信号CK由第一高电位H1转换到第一低电位L1时，拉低所述控制端子27的电位。显然，该第二较佳实施例不仅电路架构简化，而且同样节省了边框区的面积。鉴于图3所示的第二较佳实施例的原理与图2所示的第一较佳实施例的原理类似，此处不再赘述。
本发明还提供一种液晶显示器，所述液晶显示器包括本发明提供的液晶面板的驱动电路，鉴于该电路在上文已有详细的描述，此处不再赘述。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
工业实用性
序列表自由内容

Claims (13)

  1. 一种液晶面板的驱动电路，包括用于输入第一时钟信号的第一时钟信号端，还包括第一薄膜晶体管和控制端子；所述控制端子连接所述第一薄膜晶体管的栅极，所述第一薄膜晶体管设置于所述控制端子和所述第一时钟信号端之间，其中：
    所述液晶面板的驱动电路还包括用于输入第二时钟信号的第二时钟信号端，所述第一时钟信号端连接所述第一薄膜晶体管的源极或者漏极，所述控制端子设置于所述第一薄膜晶体管和所述第二时钟信号端之间，所述第二时钟信号端和所述控制端子之间还设置一抑制电容；
    所述第一时钟信号具有第一高电位和第一低电位，所述第二时钟信号具有第二高电位和第二低电位，所述第一时钟信号和所述第二时钟信号具有相同的信号周期；所述抑制电容用于在所述第一时钟信号的电位发生变化，所述第二时钟信号发生与所述第一时钟信号的电位变化相反的变化时，抑制所述控制端子的电位的变化。
  2. 根据权利要求1所述的液晶面板的驱动电路，其中，在同一个信号周期内，在所述第一时钟信号由第一高电位转换到第一低电位时，所述第二时钟信号由第二低电位转换到第二高电位；在所述第一时钟信号由第一低电位转换到第一高电位时，所述第二时钟信号由第二高电位转换到第二低电位。
  3. 根据权利要求1所述的液晶面板的驱动电路，其中，所述液晶面板的驱动电路还包括第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管，所述第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管均连接所述控制端子。
  4. 一种液晶面板的驱动电路，包括用于输入第一时钟信号的第一时钟信号端，还包括第一薄膜晶体管和控制端子；所述控制端子连接所述第一薄膜晶体管的栅极，所述第一薄膜晶体管设置于所述控制端子和所述第一时钟信号端之间，其中：
    所述液晶面板的驱动电路还包括用于输入第二时钟信号的第二时钟信号端，所述控制端子设置于所述第一薄膜晶体管和所述第二时钟信号端之间，所述第二时钟信号端和所述控制端子之间还设置一抑制电容；
    在同一时刻，所述第二时钟信号与所述第一时钟信号的电位相反，所述抑制电容，用于在所述第一时钟信号的电位发生变化，所述第二时钟信号发生与所述第一时钟信号的电位变化相反的变化时，抑制所述控制端子的电位的变化。
  5. 根据权利要求4所述的液晶面板的驱动电路，其中，所述第一时钟信号端连接所述第一薄膜晶体管的源极或者漏极。
  6. 根据权利要求4所述的液晶面板的驱动电路，其中，所述第一时钟信号具有第一高电位和第一低电位；所述第二时钟信号具有第二高电位和第二低电位；所述第一时钟信号和所述第二时钟信号具有相同的信号周期。
  7. 根据权利要求6所述的液晶面板的驱动电路，其中，在同一个信号周期内，在所述第一时钟信号由第一高电位转换到第一低电位时，所述第二时钟信号由第二低电位转换到第二高电位；在所述第一时钟信号由第一低电位转换到第一高电位时，所述第二时钟信号由第二高电位转换到第二低电位。
  8. 根据权利要求4所述的液晶面板的驱动电路，其中，所述液晶面板的驱动电路还包括第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管，所述第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管均连接所述控制端子。
  9. 一种液晶显示器，其中，所述液晶显示器包括一液晶面板的驱动电路，所述液晶面板的驱动电路包括用于输入第一时钟信号的第一时钟信号端，还包括第一薄膜晶体管和控制端子；所述控制端子连接所述第一薄膜晶体管的栅极，所述第一薄膜晶体管设置于所述控制端子和所述第一时钟信号端之间；
    所述液晶面板的驱动电路还包括用于输入第二时钟信号的第二时钟信号端，所述控制端子设置于所述第一薄膜晶体管和所述第二时钟信号端之间，所述第二时钟信号端和所述控制端子之间还设置一抑制电容；
    所述抑制电容，用于在所述第一时钟信号的电位发生变化，所述第二时钟信号发生与所述第一时钟信号的电位变化相反的变化时，抑制所述控制端子的电位的变化。
  10. 根据权利要求9所述的液晶显示器，其中，所述第一时钟信号端连接所述第一薄膜晶体管的源极或者漏极。
  11. 根据权利要求9所述的液晶显示器，其中，所述第一时钟信号具有第一高电位和第一低电位；所述第二时钟信号具有第二高电位和第二低电位；所述第一时钟信号和所述第二时钟信号具有相同的信号周期。
  12. 根据权利要求11所述的液晶显示器，其中，在同一个信号周期内，在所述第一时钟信号由第一高电位转换到第一低电位时，所述第二时钟信号由第二低电位转换到第二高电位；在所述第一时钟信号由第一低电位转换到第一高电位时，所述第二时钟信号由第二高电位转换到第二低电位。
  13. 根据权利要求9所述的液晶显示器，其中，所述液晶面板的驱动电路还包括第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管，所述第二薄膜晶体管、第三薄膜晶体管以及第四薄膜晶体管均连接所述控制端子。
PCT/CN2011/084645 2011-12-21 2011-12-26 液晶面板的驱动电路及液晶显示器 Ceased WO2013091256A1 (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9171516B2 (en) 2013-07-03 2015-10-27 Shenzhen China Star Optoelectronics Technology Co., Ltd Gate driver on array circuit
CN103310755B (zh) * 2013-07-03 2016-01-13 深圳市华星光电技术有限公司 阵列基板行驱动电路
CN105206216A (zh) * 2015-10-23 2015-12-30 武汉华星光电技术有限公司 显示装置及其应用在栅极驱动电路中的移位寄存电路
CN106935198B (zh) * 2017-04-17 2019-04-26 京东方科技集团股份有限公司 一种像素驱动电路、其驱动方法及有机发光显示面板
WO2022110247A1 (zh) * 2020-11-30 2022-06-02 京东方科技集团股份有限公司 驱动电路、其驱动方法及显示装置
CN112596314A (zh) * 2020-12-10 2021-04-02 Tcl华星光电技术有限公司 显示面板
CN112820246A (zh) * 2021-01-04 2021-05-18 Tcl华星光电技术有限公司 Tft阵列基板
CN114067729B (zh) * 2021-11-16 2022-10-04 武汉华星光电技术有限公司 发光驱动电路及显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101546069A (zh) * 2008-03-26 2009-09-30 北京京东方光电科技有限公司 液晶显示器面板结构及其制造方法
CN101556832A (zh) * 2008-04-10 2009-10-14 北京京东方光电科技有限公司 移位寄存器及液晶显示器栅极驱动装置
CN101556833A (zh) * 2008-04-11 2009-10-14 北京京东方光电科技有限公司 移位寄存器及液晶显示器栅极驱动装置
CN101978505A (zh) * 2008-06-12 2011-02-16 夏普株式会社 Tft、移位寄存器、扫描信号线驱动电路、显示装置以及tft的成形方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2743662B1 (fr) * 1996-01-11 1998-02-13 Thomson Lcd Perfectionnement aux registres a decalage utilisant des transistors mis de meme polarite
JP4990034B2 (ja) * 2006-10-03 2012-08-01 三菱電機株式会社 シフトレジスタ回路およびそれを備える画像表示装置
FR2920907B1 (fr) * 2007-09-07 2010-04-09 Thales Sa Circuit de commande des lignes d'un ecran plat a matrice active.

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101546069A (zh) * 2008-03-26 2009-09-30 北京京东方光电科技有限公司 液晶显示器面板结构及其制造方法
CN101556832A (zh) * 2008-04-10 2009-10-14 北京京东方光电科技有限公司 移位寄存器及液晶显示器栅极驱动装置
CN101556833A (zh) * 2008-04-11 2009-10-14 北京京东方光电科技有限公司 移位寄存器及液晶显示器栅极驱动装置
CN101978505A (zh) * 2008-06-12 2011-02-16 夏普株式会社 Tft、移位寄存器、扫描信号线驱动电路、显示装置以及tft的成形方法

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