WO2013091256A1 - Circuit d'attaque pour panneau à cristaux liquides et écran d'affichage à cristaux liquides - Google Patents

Circuit d'attaque pour panneau à cristaux liquides et écran d'affichage à cristaux liquides Download PDF

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Publication number
WO2013091256A1
WO2013091256A1 PCT/CN2011/084645 CN2011084645W WO2013091256A1 WO 2013091256 A1 WO2013091256 A1 WO 2013091256A1 CN 2011084645 W CN2011084645 W CN 2011084645W WO 2013091256 A1 WO2013091256 A1 WO 2013091256A1
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WO
WIPO (PCT)
Prior art keywords
clock signal
thin film
film transistor
liquid crystal
potential
Prior art date
Application number
PCT/CN2011/084645
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English (en)
Chinese (zh)
Inventor
李仕琦
林师勤
Original Assignee
深圳市华星光电技术有限公司
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Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US13/381,344 priority Critical patent/US20130162508A1/en
Publication of WO2013091256A1 publication Critical patent/WO2013091256A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to a driving circuit for a liquid crystal panel and a liquid crystal display.
  • each pixel has a thin film field effect transistor (Thin Film) Transistor (TFT), whose gate is connected to the horizontal scanning line, and the drain or source is connected to the vertical data line.
  • TFT Thin Film field effect transistor
  • the TFT element When a high voltage is applied to the scan line (gate), the TFT element is turned on, and the gray scale voltage can enter the pixel electrode (drain/source) from the data line (source/drain) and pass through the transparent pixel electrode. Applied to the liquid crystal layer, changing the standing angle of the liquid crystal to display a predetermined gray scale
  • the driving circuit for applying voltage on the scanning line is mainly completed by an external driving chip of the liquid crystal panel, but the method of externally driving the chip is not only costly, but also needs to connect the driving chip, thereby increasing the processing time.
  • the prior art generally uses an array substrate row driver (Gate Driver on The Array, GOA) circuit replaces the driver chip and directly fabricates the gate driver circuits (Gate driver ICs) on the array substrate.
  • GOA array substrate row driver
  • FIG. 1 is a structural block diagram of a GOA circuit in the prior art, including a clock signal input terminal 11, and further includes a first thin film transistor 12, a second thin film transistor 13, a third thin film transistor 14, and a fourth thin film transistor 15. And the control terminal 16, further comprising a first pull-down circuit 17 and a second pull-down circuit 18.
  • the size of the first thin film transistor 12 is generally large, and its internal parasitic capacitance (not shown) is relatively large.
  • the control terminal 16 ie, the node
  • the potential is pulled high (or pulled low)
  • the gate of the first thin film transistor 12 is turned on, thereby causing the first thin film transistor 12 to leak, resulting in the first
  • the gate of the thin film transistor 12 outputs a high potential, causing an abnormality in the voltage output to the scanning line Gn, which causes an abnormality in the screen display.
  • the prior art generally lowers the potential of the control terminal 16 by alternately operating the first pull-down circuit 17 and the second pull-down circuit 18 to avoid abnormality of the gate output of the first thin film transistor 12, wherein
  • the pull-down circuit 17 and the second pull-down circuit 18 are composed of a plurality of thin film transistors.
  • the method since the method requires the use of a plurality of thin film transistors to form the two pull-down circuits, the area of the bezel area is increased, and the circuit structure is complicated; and since the characteristics of the thin film transistor are easily changed, the leakage of the two pull-down circuits may be affected.
  • the screen display of the LCD monitor since the method requires the use of a plurality of thin film transistors to form the two pull-down circuits, the area of the bezel area is increased, and the circuit structure is complicated; and since the characteristics of the thin film transistor are easily changed, the leakage of the two pull-down circuits may be affected.
  • the screen display of the LCD monitor since the method requires the use of a plurality of
  • An object of the present invention is to provide a driving circuit for a liquid crystal panel and a liquid crystal display to solve the problem of suppressing the change of the potential of the control terminal by using a plurality of thin film transistors to form a pull-down circuit in the prior art, thereby increasing the frame area.
  • the area makes the circuit structure more complicated; and because the characteristics of the thin film transistor are easily changed, the above-mentioned pull-down circuit is leaked, which affects the technical problem of the display effect of the liquid crystal display.
  • the present invention constructs a driving circuit for a liquid crystal panel, comprising a first clock signal terminal for inputting a first clock signal, further comprising a first thin film transistor and a control terminal; the control terminal is connected to a gate of the first thin film transistor The first thin film transistor is disposed between the control terminal and the first clock signal end;
  • the driving circuit of the liquid crystal panel further includes a second clock signal end for inputting a second clock signal, the first clock signal end is connected to a source or a drain of the first thin film transistor, and the control terminal is disposed at Between the first thin film transistor and the second clock signal end, a suppression capacitor is further disposed between the second clock signal end and the control terminal;
  • the first clock signal has a first high potential and a first low potential
  • the second clock signal has a second high potential and a second low potential
  • the first clock signal and the second clock signal have the same a signal period
  • the suppression capacitor is configured to suppress a potential of the control terminal when a potential of the first clock signal changes, and when the second clock signal changes opposite to a potential change of the first clock signal The change.
  • the second clock signal is converted by the second low potential when the first clock signal is switched from the first high potential to the first low potential in the same signal period. Going to a second high potential; when the first clock signal is switched from the first low potential to the first high potential, the second clock signal is switched from the second high potential to the second low potential.
  • the driving circuit of the liquid crystal panel of the present invention further includes a second thin film transistor, a third thin film transistor, and a fourth thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film. Transistors are all connected to the control terminals.
  • Another object of the present invention is to provide a driving circuit for a liquid crystal panel, which solves the problem of suppressing the change of the potential of the control terminal by using a plurality of thin film transistors to form a pull-down circuit in the prior art, thereby increasing the area of the bezel area and making the circuit
  • the structure is relatively complicated; and because the characteristics of the thin film transistor are easily changed, the above-mentioned pull-down circuit may leak, which may affect the technical display effect of the liquid crystal display screen.
  • the present invention constructs a driving circuit for a liquid crystal panel, including a first clock signal terminal for inputting a first clock signal, and further includes a first thin film transistor and a control terminal; the control terminal is connected to the first a gate of a thin film transistor, the first thin film transistor being disposed between the control terminal and the first clock signal end;
  • the driving circuit of the liquid crystal panel further includes a second clock signal end for inputting a second clock signal, the control terminal being disposed between the first thin film transistor and the second clock signal end, the second A suppression capacitor is further disposed between the clock signal end and the control terminal;
  • the second clock signal is opposite to the potential of the first clock signal
  • the suppression capacitor is used to change a potential of the first clock signal
  • the second clock signal occurs with the
  • the first clock signal terminal is connected to a source or a drain of the first thin film transistor.
  • the first clock signal has a first high potential and a first low potential
  • the second clock signal has a second high potential and a second low potential
  • the first clock The signal and the second clock signal have the same signal period.
  • the second clock signal is converted by the second low potential when the first clock signal is switched from the first high potential to the first low potential in the same signal period. Going to a second high potential; when the first clock signal is switched from the first low potential to the first high potential, the second clock signal is switched from the second high potential to the second low potential.
  • the driving circuit of the liquid crystal panel of the present invention further includes a second thin film transistor, a third thin film transistor, and a fourth thin film transistor, the second thin film transistor, the third thin film transistor, and the fourth thin film. Transistors are all connected to the control terminals.
  • a further object of the present invention is to provide a liquid crystal display to solve the problem in the prior art that a plurality of thin film transistors are used to form a pull-down circuit to suppress a change in potential of a control terminal, thereby increasing the area of the bezel area and making the circuit structure more complicated. Moreover, since the characteristics of the thin film transistor are easily changed, the above-mentioned pull-down circuit may leak, which may affect the technical display effect of the liquid crystal display screen.
  • the present invention constructs a liquid crystal display including a driving circuit of a liquid crystal panel, the driving circuit of the liquid crystal panel includes a first clock signal end for inputting a first clock signal, and further includes a first thin film transistor and a control terminal; the control terminal is connected to a gate of the first thin film transistor, and the first thin film transistor is disposed between the control terminal and the first clock signal end;
  • the driving circuit of the liquid crystal panel further includes a second clock signal end for inputting a second clock signal, the control terminal being disposed between the first thin film transistor and the second clock signal end, the second A suppression capacitor is further disposed between the clock signal end and the control terminal;
  • the second clock signal is opposite to the potential of the first clock signal
  • the suppression capacitor is used to change a potential of the first clock signal
  • the second clock signal occurs with the
  • the first clock signal terminal is connected to a source or a drain of the first thin film transistor.
  • the first clock signal has a first high potential and a first low potential
  • the second clock signal has a second high potential and a second low potential
  • the first clock signal and the The second clock signal has the same signal period.
  • the second clock signal is switched from the second low potential to the second when the first clock signal is switched from the first high potential to the first low potential in the same signal period a high potential; the second clock signal is switched from a second high potential to a second low potential when the first clock signal is switched from the first low potential to the first high potential.
  • the driving circuit of the liquid crystal panel further includes a second thin film transistor, a third thin film transistor, and a fourth thin film transistor, and the second thin film transistor, the third thin film transistor, and the fourth thin film transistor are connected The control terminal.
  • the present invention switches from a low potential to a high potential (or from a high potential) by setting a second clock signal terminal and providing a suppression capacitor between the second clock signal terminal and the control terminal. Switching to low potential) while the second clock signal is switched from high to low (or from low to high), pulling down (or pulling high) the potential of the control terminal without passing through multiple thin film transistors
  • the pull-down circuit is formed to suppress the change of the potential of the control terminal, the area of the frame area is saved, the circuit structure is simplified, the leakage of the pull-down circuit due to the change of the characteristics of the thin film transistor is avoided, and the screen display effect of the liquid crystal display is improved.
  • FIG. 1 is a schematic structural view of an array substrate row driving circuit in the prior art
  • FIG. 2 is a schematic structural view of a first preferred embodiment of a driving circuit of a liquid crystal panel according to the present invention
  • FIG. 3 is a schematic structural view of a second preferred embodiment of a driving circuit of a liquid crystal panel according to the present invention.
  • FIGS. 2 and 3 are partial simulation views of a driving circuit of the liquid crystal panel shown in FIGS. 2 and 3.
  • FIG. 5 is a schematic diagram of signal periods of a first clock signal and a second clock signal in the present invention.
  • FIG. 2 is a structural block diagram of a first preferred embodiment of a driving circuit of a liquid crystal panel according to the present invention.
  • the driving circuit of the liquid crystal panel includes a first clock signal input terminal 21, a second clock signal input terminal 22, a first thin film transistor 23, a second thin film transistor 24, a third thin film transistor 25, a fourth thin film transistor 26, and a control terminal. 27 and the suppression capacitor 28.
  • the first clock signal terminal 21 is connected to the source or the drain of the first thin film transistor 23 (not shown); the second clock signal terminal 22 is connected to the control terminal 27; the suppression capacitor 28 is disposed at the second clock signal terminal 22 and is controlled. Between terminals 27.
  • the control terminal 27 is connected to the gate of the first thin film transistor 23 (not shown). Of course, the control terminal 27 is also connected to the second thin film transistor 24, the third thin film transistor 25, and the fourth thin film transistor 26. Since it is a mature technology, it will not be described in detail herein.
  • FIG. 4 is a partial schematic view of the driving circuit of the liquid crystal panel shown in FIG. 2.
  • a parasitic capacitance 231 is formed in the first thin film transistor 23, and the parasitic capacitance 231 is located between the first clock signal input end 21 and the control terminal 27; it is not difficult to see from the above description and the drawings that the control terminal 27 is located. Between the parasitic capacitance 231 and the suppression capacitor 28.
  • the first clock signal input terminal 21 is configured to input a first clock signal
  • the first clock signal has a first high potential and a first low potential
  • the second clock signal input terminal 22 is configured to input a second clock signal.
  • the second clock signal has a second high potential and a second low potential.
  • the first clock signal input terminal 21 and the second clock signal input terminal 22 generate a first clock signal and a second clock signal in the same signal period. In the same signal period, the first clock signal terminal 21 and the second clock signal terminal 22 alternately input high-potential and low-potential clock signals.
  • FIG. 5 is a schematic diagram of a preferred embodiment of a signal period of a first clock signal and a second clock signal in the present invention.
  • the second clock signal terminal 22 In the same signal period T, when the first clock signal input terminal 21 generates the first clock signal CK of the first high potential H1, the second clock signal terminal 22 generates the second clock signal XCK of the second low potential L2; When a clock signal input terminal 21 generates the first clock signal CK of the first low potential L1, the second clock signal terminal 22 generates a second clock signal XCK of the second high potential H2.
  • the second clock signal XCK input from the second clock signal terminal 22 is converted from the second low potential L2 to The second high potential H2.
  • the first clock signal CK is switched from the first high potential H1 to the first low potential L1, so that the parasitic capacitance 231 in the first thin film transistor 23 generates a coupling effect, and the size of the parasitic capacitance 231 is large, so that the potential of the control terminal 27 Pull up.
  • the second clock signal XCK is converted from the second low potential L2 to the second high potential H2, so that the suppression capacitor 28 generates a coupling effect, thereby causing the potential of the control terminal 27 to be pulled low.
  • the second clock signal XCK is converted from the second high potential H2 to the second low potential L2. Due to the potential conversion of the first clock signal CK, the parasitic capacitance 231 is internally coupled, thereby causing the potential of the control terminal 27 to be pulled low. At this time, since the second clock signal XCK performs an opposite potential conversion, the internal coupling of the capacitor 28 is suppressed, thereby The potential of the control terminal 27 is pulled high.
  • the suppression capacitor 28 can effectively suppress the change of the potential of the control terminal 27, cancel the influence of the coupling of the parasitic capacitance 231 on the potential of the control terminal 27, and maintain the stability of the potential of the control terminal 27, thereby ensuring the output to the scan.
  • the voltage of line Gn remains normal.
  • the invention also saves the area of the frame area, simplifies the circuit structure, avoids the problem of leakage of the pull-down circuit due to the change of the characteristics of the thin film transistor, and improves the screen display effect of the liquid crystal display.
  • FIG. 5 shows a preferred embodiment.
  • the first high potential H1 and the first low potential L1 are each 50% of a signal period T
  • the second The low potential L2 and the second high potential H2 are each also 50% of a signal period T such that when the first clock signal changes, the second clock signal simultaneously produces an opposite change.
  • the first clock signal and the second clock signal may also be distributed according to other time ratios.
  • the first low potential L1 and the second low potential L2 may each occupy 60% of the period T, Then, the first high potential H1 and the second high potential H2 each occupy 40% of the period T.
  • the suppression control terminal 27 can be achieved. The effect of the potential change.
  • FIG. 3 is a structural block diagram of a second preferred embodiment of a driving circuit of a liquid crystal panel according to the present invention, which is different from the first preferred embodiment shown in FIG.
  • a pull-down circuit 31 is further included.
  • the first clock signal CK when the first clock signal CK is switched from the first high potential H1 to the first low potential L1, the potential of the control terminal 27 is pulled up. At this time, the pull-down circuit 31 and the suppression capacitor 28 are common. Acting, the potential of the control terminal 27 is pulled low.
  • the second preferred embodiment Compared with the first pull-down circuit 17 and the second pull-down circuit 18 shown in FIG. 1 , the second preferred embodiment only provides one pull-down circuit 31 and cooperates with the suppression capacitor 28 through the pull-down circuit 31.
  • the first clock signal CK is switched from the first high potential H1 to the first low potential L1, the potential of the control terminal 27 is pulled low.
  • this second preferred embodiment not only simplifies the circuit architecture, but also saves the area of the bezel area.
  • the principle of the second preferred embodiment shown in FIG. 3 is similar to the principle of the first preferred embodiment shown in FIG. 2, and details are not described herein again.
  • the present invention also provides a liquid crystal display comprising the driving circuit of the liquid crystal panel provided by the present invention. Since the circuit has been described in detail above, it will not be described herein.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

L'invention concerne un circuit d'attaque pour panneau à cristaux liquides et un écran d'affichage à cristaux liquides. Le circuit d'attaque pour panneau à cristaux liquides comprend une première borne de signal d'horloge (21) pour l'entrée d'un premier signal d'horloge et une seconde borne de signal d'horloge (22) pour l'entrée d'un second signal d'horloge ; il comprend en outre un premier transistor à couches minces (23) et une borne de commande (27). La borne de commande (27) est placée entre le premier transistor à couches minces (23) et la seconde borne de signal d'horloge (22). L'invention comprend également un condensateur de suppression (28) placé entre la seconde borne de signal d'horloge (22) et la borne de commande (27). Le condensateur de suppression (28) est utilisé pour supprimer le potentiel de la borne de commande (27) lorsque le potentiel du premier signal d'horloge change et que le changement du second signal d'horloge est l'opposé de celui du premier signal d'horloge. Le circuit d'attaque pour panneau à cristaux liquides réduit la surface de la région de cadre, simplifie l'architecture du circuit et améliore les effets d'affichage d'images de l'écran d'affichage à cristaux liquides.
PCT/CN2011/084645 2011-12-21 2011-12-26 Circuit d'attaque pour panneau à cristaux liquides et écran d'affichage à cristaux liquides WO2013091256A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/381,344 US20130162508A1 (en) 2011-12-21 2011-12-26 Driving Circuit of a Liquid Crystal Panel and an LCD

Applications Claiming Priority (2)

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CN201110433177.7 2011-12-21
CN2011104331777A CN102411917A (zh) 2011-12-21 2011-12-21 液晶面板的驱动电路及液晶显示器

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WO2013091256A1 true WO2013091256A1 (fr) 2013-06-27

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Families Citing this family (8)

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US9171516B2 (en) 2013-07-03 2015-10-27 Shenzhen China Star Optoelectronics Technology Co., Ltd Gate driver on array circuit
CN103310755B (zh) * 2013-07-03 2016-01-13 深圳市华星光电技术有限公司 阵列基板行驱动电路
CN105206216A (zh) * 2015-10-23 2015-12-30 武汉华星光电技术有限公司 显示装置及其应用在栅极驱动电路中的移位寄存电路
CN106935198B (zh) * 2017-04-17 2019-04-26 京东方科技集团股份有限公司 一种像素驱动电路、其驱动方法及有机发光显示面板
WO2022110247A1 (fr) * 2020-11-30 2022-06-02 京东方科技集团股份有限公司 Circuit d'attaque, procédé d'attaque associé et dispositif d'affichage
CN112596314A (zh) * 2020-12-10 2021-04-02 Tcl华星光电技术有限公司 显示面板
CN112820246A (zh) * 2021-01-04 2021-05-18 Tcl华星光电技术有限公司 Tft阵列基板
CN114067729B (zh) * 2021-11-16 2022-10-04 武汉华星光电技术有限公司 发光驱动电路及显示面板

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CN101546069A (zh) * 2008-03-26 2009-09-30 北京京东方光电科技有限公司 液晶显示器面板结构及其制造方法
CN101556832A (zh) * 2008-04-10 2009-10-14 北京京东方光电科技有限公司 移位寄存器及液晶显示器栅极驱动装置
CN101556833A (zh) * 2008-04-11 2009-10-14 北京京东方光电科技有限公司 移位寄存器及液晶显示器栅极驱动装置
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JP4990034B2 (ja) * 2006-10-03 2012-08-01 三菱電機株式会社 シフトレジスタ回路およびそれを備える画像表示装置
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CN101556832A (zh) * 2008-04-10 2009-10-14 北京京东方光电科技有限公司 移位寄存器及液晶显示器栅极驱动装置
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