WO2013079688A1 - Substrat hétéro pour fabriquer des circuits intégrés pourvus de composants optiques, opto-électroniques et électroniques - Google Patents

Substrat hétéro pour fabriquer des circuits intégrés pourvus de composants optiques, opto-électroniques et électroniques Download PDF

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Publication number
WO2013079688A1
WO2013079688A1 PCT/EP2012/074141 EP2012074141W WO2013079688A1 WO 2013079688 A1 WO2013079688 A1 WO 2013079688A1 EP 2012074141 W EP2012074141 W EP 2012074141W WO 2013079688 A1 WO2013079688 A1 WO 2013079688A1
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WO
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Prior art keywords
substrate
layer
regions
silicon
hetero
Prior art date
Application number
PCT/EP2012/074141
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German (de)
English (en)
Inventor
Dieter Knoll
Bernd Heinemann
Lars Zimmermann
Harald Richter
Yuji Yamamoto
Original Assignee
Ihp Gmbh - Innovations For High Performance Microelectronics / Leibniz-Institut Für Innovative Mikroelektronik
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Application filed by Ihp Gmbh - Innovations For High Performance Microelectronics / Leibniz-Institut Für Innovative Mikroelektronik filed Critical Ihp Gmbh - Innovations For High Performance Microelectronics / Leibniz-Institut Für Innovative Mikroelektronik
Publication of WO2013079688A1 publication Critical patent/WO2013079688A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76262—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using selective deposition of single crystal silicon, i.e. SEG techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits

Definitions

  • the invention relates to a heterogeneously structured substrate for the production of integrated circuits with optical, opto-electronic and electronic components, also referred to below as hetero-substrate.
  • optical and opto-electronic components based on silicon (English: Silicon photonics or Si photonics) has been experiencing a great upswing since the beginning of the 90s of the last century.
  • Such components in particular those with dimensions of less than one micrometer (English: Submicron Si photonics), are used as key components, e.g. for optical telecommunications or optical connections in or between microelectronic circuits. Examples of such components are couplers, waveguides, modulators and photodetectors.
  • the photonic layer is located above the metallization layers of the electronic components (above IC approach, where IC stands for close integrated circuit). There are two suboptions for this first option:
  • Such requirements include low attenuation and a certain desired radius of curvature of waveguides.
  • the typical Si layer thicknesses for Option 2 range between 200 nm and a few ⁇ m, while the silicon oxide layer thicknesses are typically in the range of 2 to 4 ⁇ m. With this layer structure, however, the requirements of the electronic components is not optimally taken into account, which will be discussed below.
  • Option 2 has been demonstrated so far mostly using so-called complementary metal oxide semiconductor technologies (English: Complementary Metal Oxide Semiconductor (CMOS) technologies) for the production of the electronic components, only exceptionally, the integration of the photonic components in a SOI bipolar Process.
  • CMOS Complementary Metal Oxide Semiconductor
  • most state-of-the-art CMOS technologies use either pure Si substrates (bulk CMOS process) to achieve best performance of their CMOS transistors or, when working with SOI substrates, quite different layer thickness ranges than they do for best photonic layer properties necessary.
  • CMOS complementary metal oxide semiconductor technologies
  • SOI-based CMOS technologies Substrates whose upper Si layer is typically thinner than 50 nm.
  • a general disadvantage of a pure SOI substrate, whether optimized for photonic layers or not, is the practical impossibility of producing bipolar transistors with best high frequency properties, eg. For example, state-of-the-art silicon-germanium hetero-bipolar transistors with cut-off frequencies of up to 500 GHz, which would be highly desirable for many Option 2 applications, and which have so far only been demonstrated on pure Si substrates.
  • the main reason for this is the practical impossibility of producing transistor transistors with very low resistance, a basic requirement for the realization of ultra-fast bipolar transistors, in SOI layers, especially when their Si thickness is only 200-300 nm, as is often the case for photonic layers is the case.
  • Another reason is the lower thermal conductivity of silicon oxide compared to silicon. It leads to transistors of similar geometry under the same operating conditions (chip tion, current) on SOI substrate show a much stronger, undesired self-heating than on a silicon substrate.
  • this oxide layer is less than 400 nm in modern CMOS processes, ie significantly thinner than the oxide layers on which the waveguides are located when using SOI substrates. Nevertheless, to obtain low attenuation of the waveguides, the CMOS isolation layer is removed at the process end by a special etching step underneath the waveguide structures. Despite this trick, such polycrystalline waveguides do not achieve the low attenuation values typical of SOI-based monocrystalline Si waveguides. Besides this disadvantage, however, the main disadvantage of this approach is the practical impossibility of producing photodetectors coupled directly to the waveguides. Such photodetectors form key components of photonic layers.
  • a first quintessence of all this is that the so far mostly used for Option 2 pure SOI substrates, especially with the tailored mainly to the requirements of the photonic layers thickness ranges for the Si cover layer and the underlying silicon oxide layer, not with the substrate requirements modern technologies for the production of the most important electronic components, such as CMOS transistors and in particular also bipolar transistors, are compatible.
  • the second quintessence is that the known solutions for the integration of photonic structures in a modern bulk CMOS process provide waveguides that have significantly worse parameters compared to waveguides based on SOI and also a realization of photo detectors, the by epitaxy coupled directly to the waveguide, do not allow.
  • the publication US 2007/0238233 discloses hetero-substrates with SOI and Si regions.
  • the technical problem underlying the invention is to provide a substrate that allows the joint integration of both a photonic layer with best properties, but also of electronic components with improved parameters.
  • a further technical problem underlying the invention is to specify a method for producing such a substrate, with which the described disadvantages of known methods with regard to the joint integration of a photonic layer with the best possible parameters and CMOS transistors and bipolar transistors can be avoided with parameters that correspond to the prior art.
  • the technical problem is solved by a hetero-substrate having a multiplicity of first regions contained therein, starting from a substrate surface in a vertical direction with respect to the hetero-substrate having an SOI structure second regions which are adjacent to the first regions at a distance in vertical directions perpendicular to the first regions and which are formed in the vertical direction, starting from the substrate surface, until in the immediate vicinity of the substrate backside made of single-crystal silicon.
  • the first regions are also referred to as SOI regions and, as indicated above, have a layer sequence of monocrystalline silicon and silicon oxide applied on a monocrystalline silicon substrate. These SOI areas form in a manufacturing process for integrated circuits with optical, opto-electronic and electronic components predominantly the basis for the production of the optical components, such. As waveguide, coupling grating and others.
  • the SOI regions also form the basis for the production of the opto-electronic components, such as modulators, photosensitive diodes and others.
  • Different first regions may have either an equal or a different lateral extent in different embodiments. On the same hetero-substrate, therefore, different groups of first regions can be provided, as required, with in each group the same lateral extent, wherein the first regions of different groups have different lateral dimensions.
  • the hetero-substrate includes trenches which are either empty or filled with a dielectric material and which laterally separate the first regions from the respectively adjacent second regions and extend from the substrate surface in the vertical direction of the substrate.
  • the trenches extend from the substrate surface at least to the depth of a lower edge of a silicon layer of the SOI structure. In various alternative embodiments, they terminate before the depth of a lower edge of a silicon oxide layer of the SOI structure, or they end directly at the level of a lower edge of a silicon oxide layer of the SOI structure.
  • the heterosubstrate according to the invention has cavities communicating with the trenches which extend laterally from a respective trench wall into the respective adjacent silicon oxide layer of the first regions.
  • the heterosubstrate according to the invention has an improved crystal quality compared to the prior art cited at the beginning on. This is made possible by the method procedure according to the invention which is explained below, which provides inter alia for removing a residual layer of silicon oxide, which has initially been deliberately left, in wells prepared by anisotropic removal of the silicon oxide by highly selective wet etching. This process allows the exposure of the underlying Si support in the area of the depression with an unimpaired high crystalline surface quality.
  • the second regions can have a particularly high crystal quality in the heterosubstrate according to the invention. Due to the isotropic etching behavior of the wet-chemical etching process, this process procedure simultaneously effects the formation of the cavities characteristic of a heterosubstrate according to the invention.
  • the invention therefore provides hetero-substrates which meet two quality criteria that have hitherto been incompatible with one another: a) laterally precisely defined second regions of silicon in the depth region to be used, and b) at the same time a particularly high crystal quality of the second regions.
  • exemplary embodiments of the heterosubstrate according to the invention are described below. The respective additional features of the embodiments may be combined to form further embodiments.
  • the invention also relates to embodiments whose second regions contain a material other than pure Si. This applies in particular to silicon germanium alloys with a predominant proportion of silicon.
  • silicon-germanium alloys are included within the scope of an embodiment, as referred to in the context of the present description and the claims of silicon.
  • silicon oxide is spoken, this is to be understood as a common abbreviation for the widely used in semiconductor technology insulator material silicon dioxide.
  • the trenches extend in the lateral spacing direction between two adjacent first and second regions over a few nanometers to a few 100 nm.
  • the extent of the trenches in the said spacing direction is also referred to as the width of the trenches.
  • a second aspect of the present invention relates to a process for producing a hetero-substrate comprising
  • an SOI substrate having a monocrystalline silicon support an SOI structure disposed on the silicon support with a silicon dioxide layer and a monocrystalline silicon layer disposed on the silicon oxide layer, and, in a lateral direction, adjacent to first regions in the SOI substrate, which starting from a substrate surface of the silicon layer in a vertical direction with respect to the hetero-substrate having the SOI structure:
  • the formation of the depressions comprises a removal of the silicon dioxide layer in the vertical direction except for a residual layer, so that the bottom of the depressions is at a distance from an interface between the silicon dioxide layer and the silicon dioxide layer.
  • Carrier has.
  • the residual layer is thereby removed by means of silicon etching and the material of the auxiliary layer highly selective wet etching.
  • the process of the invention enables the preparation of the hetero-substrate of the first aspect of the invention. It shares its advantages mentioned in the present description.
  • the selective deposition of monocrystalline silicon is preferably continued in all the variants described exclusively in the depressions and up to a layer thickness (height) which is greater than a layer thickness of the SOI structure and in which a subsequent chemical mechanical polishing is carried out the layer thickness of the silicon layer is reduced to a desired level.
  • FIG. 1a shows, in a schematic cross-sectional view, three embodiments of the hetero-substrate according to the invention.
  • 1 b and 1 c show, in a schematic cross-sectional view, two embodiments of hetero-substrates according to the prior art
  • Figs. 2 to 9 illustrate an embodiment of a manufacturing process of the
  • Si regions 4 in the context of this application also referred to as second regions, which are connected directly to the substrate 1, that is to say without intermediate layers.
  • second regions 4 are in a manufacturing process for the integrated circuits with optical, opto-electronic and electronic components mainly the electronic components, such.
  • the second areas 4 are surrounded by other areas, in the context of this application also referred to as first areas and as SOI areas in which in the manufacturing process for the integrated circuits with optical, opto-electronic and electronic components predominantly the optical components such eg Waveguides, coupling gratings and others, as well as the opto-electronic components, such as e.g. Modulators, photosensitive diodes and others.
  • these SOI regions contain an Si oxide layer 2 and a monocrystalline Si layer 3 with thicknesses which can be adapted to the requirements of the optical and optoelectronic components.
  • the Si regions 4 and the SOI regions consisting of the Si oxide layer 2 and the Si layer 3 are laterally separated by trenches 5.
  • Typical trench widths range between a few nanometers and a few 100 nm.
  • the trenches 5 may have different depths.
  • the trenches end in the vertical direction above the surface of the Si substrate 1.
  • cavities 6 are provided. These cavities 6 extend laterally from the height of the Si oxide-side trench wall into the silicon oxide layer 2 of the SOI regions.
  • a step height between the surfaces of regions 4 and 3 is at most 100 nm.
  • FIG. 1 c shows an embodiment in which trenches 5 even extend into the substrate 1. In both cases, the hetero-substrate contains no cavities 6.
  • An exemplary embodiment of a manufacturing process according to the invention of the hetero-substrate of FIG. 1a will now be described with reference to FIGS. 2-9.
  • Fig. 2 shows the starting substrate which is used for the preparation of the hetero-substrate according to the invention. It knows throughout, i. Lateral interrupted nowhere, an SOI structure consisting of a monocrystalline Si layer 3 over a Si oxide layer 2, applied to a Si substrate 1.
  • the thicknesses of the layers 2 and 3 so be chosen that they are optimally adapted to the requirements of the optical and opto-electronic components.
  • the typical thicknesses of layer 3 are in the range between 200 nm and a few ⁇ m, while the thicknesses of layer 4 are typically in the range of 2 to 4 ⁇ m.
  • FIG. 3 demonstrates auxiliary layers needed to fabricate the hetero-substrate of the present invention and deposited using techniques commonly used in integrated circuit (IC) technology.
  • Layer 7 is a Si nitride layer and layer 8 is a Si oxide layer.
  • Fig. 4 illustrates how partially the homogeneous SOI structure is laterally interrupted.
  • RIE reactive Ion Etching
  • FIGS. 5 and 6 illustrate further steps of the manufacturing process.
  • a Si nitride layer 10 Figure 5
  • spacers 10a are formed from layer 10, the main purpose of which is to cover the etching edges of layer 3 (FIG. 6).
  • the Si oxide layers 2a and 8 serve as so-called etching stop layers.
  • these Si oxide layers 2a and 8 are removed by wet etching with high selectivity to Si and Si nitride, which can also form the cavity 6 (Fig. 7). It is clear that cavity 6 can not form if the spacers 10 a touch the surface of the Si substrate 1 or even reach into the substrate 1, which is achieved by the larger etch depths discussed in the context of FIG. 4.
  • Fig. 8 illustrates the filling of the etched areas with a so-called selective Si epitaxy step, i. a step where only Si growth occurs on Si surfaces but no Si deposition occurs on regions covered with insulator layers (such as Si oxide or Si nitride).
  • insulator layers such as Si oxide or Si nitride.
  • the particular benefit of the spacer 10a is clear, which prevent unwanted Si growth in the horizontal direction, starting from the etching edges of the Si layer 3.
  • the layer 4 epitaxial growth step is performed such that the faceted surface of FIG. 4 begins about a few hundred nanometers above the surface of the Si layer 3.
  • the final step in the preparation of the hetero-substrate according to the invention is the wet-chemical removal of the Si-nitride auxiliary layers 7 and 10a (usually by means of phosphoric acid), forming the structure shown in FIG. 1a.
  • the hetero-substrate according to the invention has the great advantage, in comparison to the prior art, that it permits the joint integration of optical and opto-electronic components with best properties as well as electronic components with the best parameters.
  • An initially laterally homogeneous SOI substrate whose thicknesses for the top Si layer and the underlying Si oxide layer are chosen to be optimal for the optical and opto-electronic components is modified as described for this purpose in that locally pure Si regions without SOI structure are formed, which are used to produce the electronic structures, such as CMOS transistors and bipolar transistors, can be used.

Abstract

L'invention concerne un substrat hétéro, comprenant une pluralité de premières zones qui présentent en partant d'une surface de substrat, dans une direction verticale par rapport au substrat hétéro, une structure SOI et une pluralité de deuxièmes zones qui sont approchées à une distance des premières zones dans des directions latérales perpendiculaires à la direction verticale et qui sont formées en continu de silicium monocristallin dans la direction verticale, en partant de la surface de substrat, jusqu'à proximité immédiate du côté arrière du substrat.
PCT/EP2012/074141 2011-12-02 2012-11-30 Substrat hétéro pour fabriquer des circuits intégrés pourvus de composants optiques, opto-électroniques et électroniques WO2013079688A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE201110087681 DE102011087681A1 (de) 2011-12-02 2011-12-02 Hetero-Substrat zur Herstellung von integrierten Schaltkreisen mit optischen, opto-elektronischen und elektronischen Komponenten
DE102011087681.2 2011-12-02

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WO2013079688A1 true WO2013079688A1 (fr) 2013-06-06

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Citations (4)

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Publication number Priority date Publication date Assignee Title
US20030057487A1 (en) * 2001-09-27 2003-03-27 Kabushiki Kaisha Toshiba Semiconductor chip having multiple functional blocks integrated in a single chip and method for fabricating the same
US20040150044A1 (en) * 2003-01-21 2004-08-05 Hajime Nagano Element formation substrate, method of manufacturing the same, and semiconductor device
US20050045951A1 (en) * 2003-08-28 2005-03-03 Takashi Yamada Semiconductor device and manufacturing method thereof
US20070238233A1 (en) 2006-03-30 2007-10-11 Sadaka Mariam G Method of making a multiple crystal orientation semiconductor device

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US6555891B1 (en) * 2000-10-17 2003-04-29 International Business Machines Corporation SOI hybrid structure with selective epitaxial growth of silicon
US7524707B2 (en) * 2005-08-23 2009-04-28 Freescale Semiconductor, Inc. Modified hybrid orientation technology
US7399686B2 (en) * 2005-09-01 2008-07-15 International Business Machines Corporation Method and apparatus for making coplanar dielectrically-isolated regions of different semiconductor materials on a substrate

Patent Citations (4)

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Publication number Priority date Publication date Assignee Title
US20030057487A1 (en) * 2001-09-27 2003-03-27 Kabushiki Kaisha Toshiba Semiconductor chip having multiple functional blocks integrated in a single chip and method for fabricating the same
US20040150044A1 (en) * 2003-01-21 2004-08-05 Hajime Nagano Element formation substrate, method of manufacturing the same, and semiconductor device
US20050045951A1 (en) * 2003-08-28 2005-03-03 Takashi Yamada Semiconductor device and manufacturing method thereof
US20070238233A1 (en) 2006-03-30 2007-10-11 Sadaka Mariam G Method of making a multiple crystal orientation semiconductor device

Non-Patent Citations (1)

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Title
STEFAN MEISTER ET AL: "Photonic crystal microcavities in SOI waveguides produced in a CMOS environment</title>", PROCEEDINGS OF SPIE, vol. 7606, 11 February 2010 (2010-02-11), pages 760616, XP055059813, ISSN: 0277-786X, DOI: 10.1117/12.842714 *

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