WO2013073293A1 - 半導体装置の製造方法および半導体装置 - Google Patents

半導体装置の製造方法および半導体装置 Download PDF

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WO2013073293A1
WO2013073293A1 PCT/JP2012/074661 JP2012074661W WO2013073293A1 WO 2013073293 A1 WO2013073293 A1 WO 2013073293A1 JP 2012074661 W JP2012074661 W JP 2012074661W WO 2013073293 A1 WO2013073293 A1 WO 2013073293A1
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Prior art keywords
substrate
semiconductor device
oxide film
trench
manufacturing
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French (fr)
Japanese (ja)
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増田　健良
和田　圭司
透 日吉
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Sumitomo Electric Industries Ltd
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Sumitomo Electric Industries Ltd
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Priority to KR1020147004423A priority Critical patent/KR20140041863A/ko
Priority to EP12849942.3A priority patent/EP2782137A4/en
Priority to CN201280049775.7A priority patent/CN103890951B/zh
Publication of WO2013073293A1 publication Critical patent/WO2013073293A1/ja
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    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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    • H10D12/01—Manufacture or treatment
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    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
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    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
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    • H10D30/00—Field-effect transistors [FET]
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    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
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    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
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    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01366—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the semiconductor being silicon carbide
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    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/512—Disposition of the gate electrodes, e.g. buried gates
    • H10D64/513—Disposition of the gate electrodes, e.g. buried gates within recesses in the substrate, e.g. trench gates, groove gates or buried gates
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
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    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6518—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer
    • H10P14/6524—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer the substance being nitrogen
    • H10P14/6526—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer the substance being nitrogen introduced into an oxide material, e.g. changing SiO to SiON
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
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    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials

Definitions

  • the present invention relates to a method of manufacturing a semiconductor device and a semiconductor device, and more specifically, a method of manufacturing a semiconductor device capable of stably manufacturing a semiconductor device having desired characteristics, and an electric field to an oxide film.
  • the present invention relates to a semiconductor device capable of stably exhibiting a desired withstand voltage by relaxing concentration.
  • Silicon carbide is a wide band gap semiconductor having a large band gap as compared to silicon which has conventionally been widely used as a material constituting a semiconductor device. Therefore, by adopting silicon carbide as a material forming the semiconductor device, it is possible to achieve high breakdown voltage of the semiconductor device, reduction of on-resistance, and the like.
  • Patent Document 1 a method of manufacturing a trench gate type MOSFET having a low threshold voltage and a high withstand voltage by forming a thin oxide film on the sidewall of the trench and a thick oxide film on the bottom of the trench. Has been proposed.
  • Patent Document 1 a crystal surface with a slow oxidation rate is adopted as the trench sidewall surface, a crystal plane with a fast oxidation rate is adopted as the trench bottom, and the plane orientation dependency of the oxidation rate is used.
  • a MOSFET having a low threshold voltage and a high withstand voltage can be manufactured.
  • the film thickness of the oxide film to be formed also varies due to the surface orientation dependency of the oxidation rate. And, the variation in the film thickness of the oxide film also affects the characteristics of the manufactured MOSFET. As a result, it becomes difficult to stably manufacture a MOSFET having desired characteristics.
  • the present invention has been made in view of the above problems, and an object thereof is a method of manufacturing a semiconductor device capable of stably manufacturing a semiconductor device having desired characteristics, and relaxation of electric field concentration on an oxide film. It is an object of the present invention to provide a semiconductor device capable of stably exhibiting a desired withstand voltage.
  • a method of manufacturing a semiconductor device comprises the steps of: preparing a substrate made of silicon carbide; forming a trench opened on one main surface side of the substrate in the substrate; and oxidizing a region including the surface of the trench. Forming a film.
  • the substrate is heated at a temperature of 1250 ° C. or higher in an atmosphere containing oxygen.
  • the inventor has conducted a detailed study on measures for stably manufacturing a semiconductor device having desired characteristics.
  • the heating temperature of the substrate in the formation of the oxide film functioning as a gate insulating film higher than a general heating temperature, specifically by setting the heating temperature to 1250 ° C. or higher, the plane orientation of the oxidation rate of the substrate
  • the substrate is heated at an appropriate temperature of 1250 ° C. or more to form an oxide film in a region including the trench surface formed in the substrate. Therefore, the dependence of the film thickness of the formed oxide film on the surface orientation of the trench surface is reduced.
  • a semiconductor device having characteristics such as desired threshold voltage by stably forming an oxide film having a desired film thickness in a region including a trench surface. Can be manufactured stably.
  • the substrate in the step of forming an oxide film, may be heated at a temperature of 1300 ° C. or more. Thereby, the dependence of the film thickness of the formed oxide film on the surface orientation of the trench surface can be more effectively reduced.
  • the substrate in the step of forming an oxide film, may be heated at a temperature of 1400 ° C. or less.
  • the method of manufacturing the semiconductor device can be performed at an appropriate temperature of 1400 ° C. or less in consideration of the durability of the manufacturing apparatus.
  • the method for manufacturing a semiconductor device further includes the step of introducing nitrogen atoms into a region including the interface between the oxide film and silicon carbide constituting the substrate by heating the substrate in an atmosphere containing a gas containing nitrogen atoms. You may have.
  • the interface state present in the region including the interface between the oxide film and silicon carbide forming the substrate can be reduced. Therefore, a decrease in channel mobility due to the presence of interface states can be suppressed.
  • the main surface of the substrate may be a ⁇ 0001 ⁇ plane.
  • Silicon carbide can be easily grown in the ⁇ 0001> direction. Therefore, the substrate can be easily prepared by setting the main surface of the substrate made of silicon carbide to the ⁇ 0001 ⁇ plane.
  • the state where the main surface is the ⁇ 0001 ⁇ plane means that the off angle with respect to the ⁇ 0001 ⁇ plane of the main surface is within 8 °.
  • a trench including a wall surface having an angle of 40 ° to 70 ° with the ⁇ 0001 ⁇ plane may be formed.
  • a semiconductor device having high channel mobility is manufactured by forming a trench including the wall whose angle with the ⁇ 0001 ⁇ plane is in the above range and forming a channel region along the wall. be able to.
  • a semiconductor device includes a substrate made of silicon carbide and having a trench formed on one of the main surfaces and an oxide film formed to cover the surface of the trench.
  • the maximum value of the thickness of the oxide film is equal to or less than twice the minimum value of the thickness of the oxide film.
  • the film thickness of the oxide film means the film thickness in the direction perpendicular to the surface of the trench.
  • the semiconductor device according to the present invention it is possible to provide a semiconductor device capable of stably exhibiting a desired withstand voltage by relaxing the concentration of the electric field on the oxide film.
  • a semiconductor device having desired characteristics can be stably manufactured. Further, according to the semiconductor device according to the present invention, it is possible to provide a semiconductor device capable of stably exhibiting a desired withstand voltage by relaxing the electric field concentration on the oxide film.
  • MOSFET 1 as a semiconductor device according to the present embodiment includes silicon carbide substrate 10, silicon carbide layer 20, oxide film 40, gate electrode 41, interlayer insulating film 50, and a source electrode. 60, a drain electrode 70, a source wiring 61, and a back surface protection electrode 71.
  • Silicon carbide layer 20 includes a drift region 21, a body region 22, a source region 23 and a contact region 24. Silicon carbide substrate 10 and silicon carbide layer 20 constitute a substrate 30 made of silicon carbide.
  • MOSFET 1 as the semiconductor device according to the present embodiment is a silicon carbide semiconductor device provided with substrate 30 made of silicon carbide.
  • a trench 15 is formed which is open on the side of one main surface 30A.
  • Trench 15 includes side wall surface 15A and bottom surface 15B, and penetrates source region 23 and body region 22 such that side wall surface 15A extends to source region 23, body region 22 and drift region 21, and bottom surface 15B is drift region 21. It is formed to be located in
  • Silicon carbide substrate 10 has n conductivity type by containing n type impurities.
  • Drift region 21 is formed on main surface 10A of silicon carbide substrate 10.
  • Drift region 21 has n type conductivity by containing n type impurities.
  • the concentration value of the n-type impurity contained in drift region 21 is lower than the concentration value of the n-type impurity contained in silicon carbide substrate 10.
  • Body region 22 is formed on the opposite side to silicon carbide substrate 10 as viewed from drift region 21.
  • Body region 22 includes side wall surface 15A, and is formed to extend in contact with drift region 21 in a direction away from side wall surface 15A.
  • Body region 22 has p type conductivity by containing p type impurities.
  • the p-type impurity contained in body region 22 is, for example, Al (aluminum), B (boron) or the like.
  • Source region 23 is formed on the opposite side to drift region 21 as viewed from body region 22.
  • Source region 23 includes side wall surface 15A, and is formed to extend in contact with body region 22 in a direction away from side wall surface 15A.
  • the source region 23 has an n-type conductivity by containing an n-type impurity.
  • the concentration value of the n-type impurity contained in source region 23 is higher than the concentration value of the n-type impurity contained in drift region 21.
  • the n-type impurity contained in source region 23 is, for example, P (phosphorus).
  • the contact region 24 is formed to be adjacent to the source region 23 while being in contact with the body region 22.
  • the contact region 24 has a p-type conductivity by containing a p-type impurity.
  • the concentration value of the p-type impurity contained in the contact region 24 is higher than the concentration value of the p-type impurity contained in the body region 22.
  • the p-type impurity contained in contact region 24 is, for example, Al, B, etc., similarly to the p-type impurity contained in body region 22.
  • Oxide film 40 is formed to cover the surface of trench 15, that is, sidewall surface 15A and bottom surface 15B, and main surface 30A of substrate 30.
  • the maximum value of the film thickness of the oxide film 40 is equal to or less than twice the minimum value of the film thickness of the oxide film 40.
  • Oxide film 40 is made of, for example, silicon dioxide (SiO 2 ).
  • Gate electrode 41 is formed in trench 15 to be in contact with oxide film 40 formed to cover sidewall surface 15A and bottom surface 15B.
  • Gate electrode 41 is made of, for example, a conductor such as polysilicon to which an impurity is added, or Al.
  • Source electrode 60 is formed to be in contact with source region 23 and contact region 24.
  • Source electrode 60 is made of a material capable of making ohmic contact with source region 23, such as Ni x Si y (nickel silicide), Ti x Si y (titanium silicide), Al x Si y (aluminum silicide), and Ti x Al. y Si z (titanium aluminum silicide) or the like is electrically connected to the source region 23.
  • Interlayer insulating film 50 is formed to surround gate electrode 41 together with oxide film 40, and electrically insulates gate electrode 41 from source electrode 60 and source interconnection 61.
  • Interlayer insulating film 50 is made of, for example, silicon dioxide (SiO 2 ).
  • Source interconnection 61 is formed to cover interlayer insulating film 50 and source electrode 60.
  • Source interconnection 61 is made of a conductor such as Al, for example, and is electrically connected to source region 23 through source electrode 60.
  • Drain electrode 70 is formed on main surface 10 B opposite to drift region 21 as viewed from silicon carbide substrate 10.
  • Drain electrode 70 is made of a material that can make ohmic contact with silicon carbide substrate 10, for example, the same material as source electrode 60, and is electrically connected to silicon carbide substrate 10.
  • the back surface protection electrode 71 is formed to cover the drain electrode 70.
  • Back surface protection electrode 71 is made of a conductor such as Al, for example.
  • the MOSFET 1 in the state where the voltage applied to gate electrode 41 is less than the threshold voltage, that is, in the off state, body region 22 and drift occur even if a voltage is applied between source electrode 60 and drain electrode 70.
  • the pn junction formed between the region 21 and the region 21 is reverse biased and becomes nonconductive.
  • an inversion layer is formed in a channel region which is a region in body region 22 in contact with sidewall surface 15A.
  • source region 23 and drift region 21 are electrically connected, and a current flows between source electrode 60 and drain electrode 70.
  • the MOSFET 1 operates.
  • the maximum value of the film thickness of the oxide film 40 is equal to or less than twice the minimum value of the film thickness of the oxide film 40.
  • step (S10) a step of preparing a substrate made of silicon carbide is performed.
  • This process (S10) includes the processes (S11) and (S12) shown below.
  • step (S11) a silicon carbide substrate preparation step is performed.
  • silicon carbide substrate 10 is prepared.
  • Silicon carbide substrate 10 is made of, for example, 4H-type hexagonal silicon carbide.
  • an epitaxial growth layer formation step is performed as a step (S12).
  • silicon carbide layer 20 is formed on main surface 10A of silicon carbide substrate 10 by epitaxial growth.
  • substrate 30 formed of silicon carbide substrate 10 and silicon carbide layer 20 is prepared.
  • Main surface 30A of substrate 30 may be a ⁇ 0001 ⁇ plane. Silicon carbide can be easily grown in the ⁇ 0001> direction. Therefore, substrate 30 can be easily prepared by setting main surface 30A of substrate 30 made of silicon carbide to the ⁇ 0001 ⁇ plane.
  • an ion implantation step is performed as a step (S20).
  • this step (S20) referring to FIG. 4, for example, Al ions are implanted into the surface layer portion of silicon carbide layer 20, for example.
  • P ions are implanted into the surface layer portion of silicon carbide layer 20 at an implantation depth shallower than the implantation depth of Al ions.
  • source region 23 in which P ions are implanted and body region 22 in which Al ions are implanted are formed.
  • silicon carbide layer 20 a region where source region 23 and body region 22 are not formed becomes drift region 21.
  • a trench formation step is performed.
  • a trench 15 opened on the side of one main surface 30A of substrate 30 is formed in substrate 30. More specifically, trench 15 penetrates source region 23 and body region 22 so that sidewall surface 15 A extends from source region 23 to body region 22 and drift region 21, and bottom surface 15 B extends to drift region 21. It is formed to be positioned.
  • trench 15 is formed on substrate 30 by dry etching such as RIE (Reactive Ion Etching) or thermal etching using halogen gas such as chlorine gas, or an etching method combining these, for example. It may be formed. Specifically, for example, a mask layer (not shown) made of silicon dioxide (SiO 2 ) is formed on main surface 30A of substrate 30, and after preliminary etching is performed by RIE, further thermal etching is performed. Trenches 15 may be formed in the substrate 30. Further, in this step (S30), by forming the trenches 15 in the substrate 30 using an etching method including thermal etching, it is possible to reduce the variation in the surface orientation of the side wall surfaces 15A facing each other. As a result, in the gate oxide film forming step (S60) described later, it is possible to reduce the variation in the film thickness of the oxide film formed in the region including the sidewall surface 15A.
  • RIE Reactive Ion Etching
  • halogen gas such as chlorine gas
  • trench 15 may be formed such that the angle between sidewall surface 15A and the ⁇ 0001 ⁇ plane is 40 ° or more and 70 ° or less.
  • MOSFET 15 having high channel mobility is formed by forming trench 15 including sidewall surface 15A whose angle with the ⁇ 0001 ⁇ plane is in the above range, and forming a channel region along sidewall surface 15A. 1) can be manufactured.
  • trench 15 may be formed as a U-shaped trench including sidewall surface 15A and bottom surface 15B, but is not limited thereto.
  • trench 15 may be formed as a V-type trench which does not include bottom surface 15B but includes only sidewall surface 15A.
  • a contact region formation step is performed.
  • this step (S40) referring to FIG. 6, by implanting Al ions, for example, in source region 23, contact region 24 adjacent to source region 23 while being in contact with body region 22 is formed.
  • an activation annealing step is performed as a step (S50).
  • the substrate 30 is heated to activate the impurities introduced in the above steps (S20) and (S40). As a result, desired carriers are generated in the region into which the impurity is introduced.
  • a gate oxide film formation step is performed.
  • this step (S60) referring to FIG. 7, by heating substrate 30 in an atmosphere containing oxygen, the surface of trench 15, that is, side wall surface 15A and bottom surface 15B, and main surface 30A of substrate 30 are obtained.
  • An oxide film 40 is formed over the region including.
  • the oxide film 40 is formed of, for example, silicon dioxide (SiO 2 ).
  • the atmosphere containing oxygen may be an atmosphere containing only oxygen gas, for example, a mixed gas of a rare gas such as argon and oxygen gas, N 2 O, NO, NO 2 , POCl 3 , SO 2 and An atmosphere containing an oxidizing gas such as SO 4 may be used.
  • the substrate 30 is heated at a temperature of 1250 ° C. or higher.
  • the substrate 30 is preferably heated to a temperature of 1300 ° C. or higher.
  • the dependence of the film thickness of the oxide film 40 on the surface orientation of the surface of the trench 15 can be more effectively reduced.
  • the substrate 30 may be heated at a temperature of 1400 ° C. or less.
  • the step (S60) can be carried out at an appropriate temperature taking into consideration the durability of the manufacturing apparatus, such as 1250 ° C. or more and 1400 ° C. or less.
  • a nitrogen atom introducing step is performed.
  • this step (S70) by heating substrate 30 in an atmosphere containing a gas containing nitrogen atoms, nitrogen atoms are introduced into a region including an interface between oxide film 40 and silicon carbide constituting substrate 30. .
  • this step (S70) is not an essential step, by carrying out this step, the interface state present in the region including the interface between oxide film 40 and silicon carbide constituting substrate 30 can be reduced. Therefore, a decrease in channel mobility due to the presence of interface states can be suppressed.
  • the gas containing a nitrogen atom for example, NO (nitrogen monoxide), NO 2 (nitrogen dioxide) and N 2 O (nitrous oxide) may be used.
  • a gate electrode formation step is performed.
  • a polysilicon film is formed in trench 15 by, for example, a low pressure chemical vapor deposition (LPCVD) method.
  • LPCVD low pressure chemical vapor deposition
  • interlayer insulating film forming step is performed.
  • interlayer insulating film 50 made of SiO 2 which is an insulator is surrounded by gate electrode 41 together with oxide film 40 by P (Plasma) -CVD method, for example. It is formed.
  • an ohmic electrode formation step is performed as a step (S100).
  • step (S100) referring to FIG. 9, first, interlayer insulating film 50 and oxide film 40 are removed in the region where source electrode 60 is to be formed, and source region 23 and contact region 24 are exposed. Become. Then, a film made of, for example, Ni is formed in the region. On the other hand, in silicon carbide substrate 10, a film made of, for example, Ni is formed on main surface 10B opposite to the side on which drift region 21 is formed. Thereafter, alloy heat treatment is performed, and at least a part of the film made of Ni is silicided, whereby the source electrode 60 and the drain electrode 70 are formed.
  • a wiring formation step is performed.
  • source interconnection 61 made of Al which is a conductor, is formed to cover interlayer insulating film 50 and source electrode 60, for example, by evaporation.
  • back surface protection electrode 71 made of, for example, Al is formed to cover drain electrode 70.
  • the substrate 30 is heated at an appropriate temperature of 1250 ° C. or more to oxidize the region including the surface of the trench 15 formed in the substrate 30.
  • a film 40 is formed. Therefore, the dependence of the film thickness of the oxide film 40 to be formed on the surface orientation of the surface of the trench 15 is reduced. As a result, even when the surface orientation of the surface of the trench 15 is uneven, the oxide film 40 close to the target film thickness can be formed.
  • oxide film 40 having a desired film thickness is stably formed in a region including the surface of trench 15, whereby desired characteristics such as threshold voltage are obtained.
  • the MOSFET 1 can be stably manufactured.
  • the method of manufacturing the semiconductor device of the present invention is not limited to this.
  • the method of manufacturing a semiconductor device according to the present invention is widely used in a method of manufacturing a semiconductor device including a step of forming a thermal oxide film in a region including the surface of a trench, such as a method of manufacturing a trench gate type IGBT (insulated gate bipolar transistor). be able to.
  • a trench gate type IGBT insulated gate bipolar transistor
  • a trench gate type MOSFET was manufactured using the method for manufacturing a semiconductor device according to the present embodiment.
  • the oxide film was formed in a region including the trench surface by heating at 1350 ° C. for 20 minutes in an oxygen atmosphere.
  • the cross-sectional structure of the manufactured MOSFET is observed by Blight Field-Scanning Transmission Electron Microscope (BF-STEM), and the obtained BF-STEM photograph shows that the oxide film formed in the region including the trench surface of the MOSFET is The film thickness was investigated.
  • FIG. 10 is a BF-STEM photograph showing a cross-sectional structure of a region including the trench surface of the MOSFET manufactured in the above experiment (50000 ⁇ magnification).
  • the oxide film 40 is formed to have a film thickness of about 0.05 ⁇ m, although the surface orientation is largely different between the side wall surface 15A and the bottom surface 15B. From this, it was confirmed that in the method of manufacturing a semiconductor device according to the present invention, the plane orientation dependency of the oxidation rate in the formation of the oxide film is reduced, and the oxide film having a desired film thickness can be stably formed. .
  • a trench gate type MOSFET was manufactured using the method for manufacturing a semiconductor device according to the present embodiment.
  • the trench is formed in the substrate such that the bottom surface is a (000-1) plane and the side wall surface is a (0-33-8) plane.
  • the region including the sidewall surface and the bottom surface of the trench is heated at temperatures of 1200 ° C., 1250 ° C., 1300 ° C., 1350 ° C. and 1400 ° C. for 20 minutes in an atmosphere containing oxygen. Formed an oxide film.
  • the film thickness of the oxide film formed in the region including the side wall surface and the bottom surface was evaluated, and the influence of the heating temperature of the substrate on the film thickness of the oxide film was investigated.
  • Table 1 shows the influence of the heating temperature of the substrate on the thickness of the oxide film formed in the region including the side wall surface and the bottom surface.
  • Table 2 shows the influence of the heating temperature of the substrate on the film thickness ratio of the oxide film formed in the region including the side wall surface and the bottom surface.
  • the film thickness ratio means the ratio of the film thickness of the oxide film formed in the region including the bottom to the film thickness of the oxide film formed in the region including the sidewall surface.
  • FIG. 11 shows the influence of the heating temperature of the substrate on the thickness of the oxide film formed in the region including the side wall surface and the bottom surface.
  • FIG. 12 shows the influence of the heating temperature of the substrate on the thickness ratio of the oxide film formed in the region including the side wall surface and the bottom surface.
  • the heating temperature is 1200 ° C.
  • the film thickness ratio of the oxide film is 50% or less, but by setting the heating temperature to 1250 ° C. or more
  • the film thickness ratio of the oxide film was 50% or more.
  • the oxidation rate in the formation of the oxide film is set by setting the heating temperature of the substrate in the formation of the oxide film to 1250 ° C. or higher, preferably 1300 ° C. or higher. It has been confirmed that the plane orientation dependency of the above can be reduced, and an oxide film with a desired film thickness can be stably formed.
  • a method of manufacturing a semiconductor device and a semiconductor device according to the present invention is a method of manufacturing a semiconductor device which is required to stably manufacture a semiconductor device having desired characteristics, and a desired electric field concentration on an oxide film is alleviated.
  • the present invention can be applied particularly advantageously to a semiconductor device which is required to stably exhibit a withstand voltage.
  • Reference Signs List 1 MOSFET 10 silicon carbide substrate, 10A, 10B, 30A main surface, 15 trench, 15A sidewall surface, 15B bottom surface, 20 silicon carbide layer, 21 drift region, 22 Body region, 23 source region, 24 contact region, 30 substrate, 40 oxide film, 41 gate electrode, 50 interlayer insulating film, 60 source electrode, 61 source wiring, 70 drain electrode, 71 back surface protection electrode.

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  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
PCT/JP2012/074661 2011-11-16 2012-09-26 半導体装置の製造方法および半導体装置 Ceased WO2013073293A1 (ja)

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CN103890951A (zh) 2014-06-25
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