WO2013067855A1 - 薄膜晶体管及其制造方法、显示器件 - Google Patents
薄膜晶体管及其制造方法、显示器件 Download PDFInfo
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- WO2013067855A1 WO2013067855A1 PCT/CN2012/081614 CN2012081614W WO2013067855A1 WO 2013067855 A1 WO2013067855 A1 WO 2013067855A1 CN 2012081614 W CN2012081614 W CN 2012081614W WO 2013067855 A1 WO2013067855 A1 WO 2013067855A1
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- 239000010409 thin film Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
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- 238000005229 chemical vapour deposition Methods 0.000 claims description 19
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
Definitions
- Embodiments of the present invention relate to a thin film transistor (TFT), a method of fabricating the same, and a display device.
- TFT thin film transistor
- TFTs have been used in a variety of electro-optical devices including liquid crystal display devices, semiconductor devices.
- the quality of the gate insulating layer has an extremely important influence on its electrical characteristics.
- the high quality of the high k value (ie, dielectric constant) of the gate insulating material can greatly improve the device performance of the TFT, for example, reducing the threshold voltage, increasing the switching ratio, and reducing the sub-thickness swing.
- Non-Patent Document 1 describes a method of preparing a gate insulating layer by using a tetraethyl orthosilicate (TEOS) process.
- TEOS tetraethyl orthosilicate
- this method still belongs to the CVD process, and the thin layer of the gate insulating film formed is relatively loose due to the low formation temperature, and the insulating property is not good (only about 5.6 10 6 Vcm is achieved) 1 ), which is for the TFT device. If the leakage current is too large, the device performance will be affected. If the gate insulating layer is thickened, the operating voltage of the device will increase and the process time will be prolonged.
- An embodiment of the present invention provides a method of fabricating a thin film transistor, comprising the steps of: providing a substrate; forming a semiconductor layer on the substrate; forming a gate insulating layer; and forming a gate electrode, wherein the gate
- the insulating layer includes a first gate insulating layer formed by oxidizing a portion of the semiconductor layer, and an unoxidized portion of the semiconductor layer forms an active layer, and And wherein the gate electrode is formed such that a gate insulating layer is interposed between the gate electrode and the active layer.
- Another embodiment of the present invention provides a thin film transistor including a substrate, an active layer, a gate insulating layer, a gate electrode, and a source/drain electrode, wherein the gate insulating layer includes a direct interface with the active layer And contacting the first gate insulating layer, and the first gate insulating layer has a dielectric strength of at least 8 10 6 V-cm.
- Still another embodiment of the present invention provides a display device including a thin film transistor according to any of the embodiments of the present invention.
- Figure 1 is a view showing a substrate used in a process of fabricating a TFT device according to an example of the present invention
- Figure 2 is a view showing a structure formed in a process of fabricating a TFT device according to an example of the present invention
- Figure 3 is a view showing a structure formed in a process of fabricating a TFT device according to an example of the present invention
- Figure 4 is a view showing a structure formed in a process of fabricating a TFT device according to an example of the present invention
- Figure 5 is a view showing a structure formed in a process of fabricating a TFT device according to an example of the present invention
- Fig. 6 is a view showing the construction of a TFT device according to an example of the present invention. detailed description
- the TFT device includes a substrate 1, an active layer 3, a first gate insulating layer 5 over the active layer 3, a gate electrode 4 over the first gate insulating layer 5, and A source/drain electrode 6 having an opening in the first gate insulating layer 5 in contact with the active layer 3.
- the first gate insulating layer 5 is in direct contact with the active layer 3.
- the TFT device 101 may further include a buffer layer 2 between the active layer 3 and the substrate 1.
- the buffer layer 2 may have a thickness of 5 to 1000 nm and is formed of SiO 2 or SiN x .
- the substrate 1 may be a transparent glass, and the substrate 1 may have a thickness of 30 to 1000 ⁇ m. However, the substrate 1 is not limited to the transparent glass, and may be another transparent or opaque substrate, and the thickness of the substrate 1 is not limited to the above thickness.
- the active layer 3 is formed of polysilicon.
- Polycrystalline silicon can be obtained by using an excimer laser annealing ELA process. For example, on the transparent substrate 1 on which the buffer layer 2 is deposited, amorphous silicon having a thickness of 50-200 ⁇ is first deposited, and then an ELA device such as a high energy (for example, about 100-500 mJ-cm" 2 ) is used. Scanning is performed to crystallize the amorphous silicon layer to be converted into a polysilicon layer.
- an ELA device such as a high energy (for example, about 100-500 mJ-cm" 2 ) is used. Scanning is performed to crystallize the amorphous silicon layer to be converted into a polysilicon layer.
- the semiconductor layer 3' for example, a polysilicon layer, see FIG. 3 for forming the active layer 3 may be placed in an oxidizing atmosphere (for example, a nitrogen-containing or oxygen-containing atmosphere). Convective heating or laser heating or the like causes the surface of the semiconductor layer 3' to directly form a dense thermally oxidized gate insulating layer 5.
- a dense thermal oxide gate insulating layer 5 thermal silicon oxide layer
- the gate insulating layer 5 may have a thickness of 1-100 nm.
- the surface layer of the semiconductor layer is oxidized to form a dense thermally oxidized gate insulating layer 5, and the unoxidized portion of the semiconductor layer forms the active layer 3 (see Fig. 4).
- an additional second gate insulating layer may be formed on the gate insulating layer 5 by other methods (for example, CVD method or sputtering method) to form a composite gate insulating layer (not shown). Out).
- the total thickness of the composite gate insulating layer i.e., the sum of the thicknesses of the first gate insulating layer and the second gate insulating layer
- the second gate insulating layer is located between the gate electrode 4 and the first gate insulating layer 5, and the source/drain electrode 6 is in contact with the active layer 3 through an opening in the composite gate insulating layer.
- the gate electrode 4 may be formed over a gate insulating layer composed of the first gate insulating layer 5 or composed of the above composite gate insulating layer (top gate structure). Alternatively, in the TFT having the bottom gate structure, the gate electrode 4 may be formed on the substrate 1. In one embodiment, the technical solution according to an embodiment of the present invention may be applied to a bottom gate structure. In this case, the gate electrode 4 is disposed on the substrate 1 (or the buffer layer 2), and the gate insulating layer is disposed on the gate electrode 4. In this case, the gate electrode 4 may be formed first, but a semiconductor layer is formed on the gate electrode 4, and then an insulating layer is formed on the bottom of the semiconductor layer by injecting oxygen into the bottom of the semiconductor layer.
- the insulating layer can be used as a gate insulating layer, and the unoxidized upper portion is used as an active layer.
- the element for oxidizing the above-mentioned semiconductor layer to be oxidized may use other elements having an oxidized form in addition to the oxygen element.
- the thickness of the gate electrode 4 is 1-200 nm, and materials such as Mo, Cr, Au, and other alloys can be selected.
- the gate electrode 4 can be formed by patterning a gate metal layer.
- the source/drain electrode 6 has a thickness of 5-300 nm, and a metal such as Mo, Al, In, Ti, or a composite metal, and an alloy material can be selected.
- the source/drain electrode 6 can be formed by patterning a source/drain metal layer.
- Fig. 1 shows a transparent substrate 1 used in a process of fabricating a TFT device according to an example of the present invention.
- the transparent substrate 1 can be cleaned by a standard process and the buffer layer 2 and the semiconductor layer 3' can be formed in this order.
- the semiconductor 3' can be formed by first forming a semiconductor layer precursor 3" (for example, amorphous silicon), thereby obtaining the structure shown in Fig. 2.
- the semiconductor layer shown in Fig. 2 can be used.
- the body 3" is converted into a semiconductor layer 3' for forming the active layer 3, thereby obtaining the structure shown in FIG.
- an amorphous silicon film is crystallized by laser crystallization or the like to form a polysilicon layer 3'.
- the method for forming the semiconductor layer 3' is not limited to the above-described method of forming a polycrystalline silicon layer by a laser crystallization process for amorphous silicon germanium.
- Fig. 4 is a view showing the structure obtained by forming the gate insulating layer 5 on the structure shown in Fig. 3.
- the surface of the semiconductor layer 3' (for example, a polysilicon layer) may be first treated with 1% hydrofluoric acid (HF), and then the surface layer of the semiconductor layer 3' is thermally oxidized to a dense gate in an oxidizing atmosphere. Pole insulating layer 5. At the same time, the unoxidized portion (lower portion) of the semiconductor layer 3' forms the active layer 3.
- HF hydrofluoric acid
- Thermal oxidation can be carried out by dry thermal oxidation or wet thermal oxidation processes, and by means of an annealing furnace or ELA to provide energy for the oxidation process.
- the volumetric content of oxygen is greater than 98% and the volumetric content of water is less than 10 ppm.
- the volume content of oxygen is more than 97%, and the volume content of water is 10-1000 ppm.
- the atmosphere of the wet thermal oxidation process can be obtained by: when oxygen passes through the annealing furnace, It is passed through a container containing deionized water (for example, a conical flask) or the like so that oxygen naturally carries moisture when passing through deionized water.
- the volume content of water is preferably from 10 to 1000 ppm.
- the oxidizing atmosphere includes not only an oxygen-containing atmosphere, but also an atmosphere containing other oxidizing substances, such as a nitrogen-containing atmosphere.
- the nitrogen-containing atmosphere may be an atmosphere containing N 2 or NH 3 .
- gate insulating layers may also be deposited on the first gate insulating layer 5 by a conventional method (for example, CVD or sputtering).
- a conventional method for example, CVD or sputtering
- an embodiment of the method according to the present invention further comprises a composite Si0 2 deposited Si0 2 with other portions of the thermal oxidation method to form the gate insulating layer.
- a gate metal layer may be deposited next, and a desired pattern is formed by photolithography or the like to form the gate electrode 4. Then, through the photolithography and etching processes, the openings (contact holes) required for the contact between the source and drain electrodes 6 and the active layer are etched, thereby depositing a source/drain metal layer, and forming a desired pattern by a photolithography process. The source and drain electrodes 6 are formed, thereby obtaining the TFT device shown in FIG. At this time, the source/drain electrodes 6 are in contact with the active layer through the openings in the gate insulating layer 5. In the above process of forming a composite gate insulating layer, the source and drain electrodes 6 are in contact with the active layer through openings in the composite gate insulating layer. Finally, the obtained structure was tested and analyzed.
- the quartz substrate is cleaned, and 50 nm of SiN x and 300 ⁇ of Si0 2 are sequentially deposited on the substrate by a CVD method as a buffer layer, and then amorphous silicon having a thickness of 100 nm is deposited, and an excimer laser is used.
- the amorphous silicon is crystallized, and then the sample is first treated with 1% by volume of HF, and then a 50 nm thick Si0 2 film is deposited on the surface of the sample by CVD, and then a Mo gate is sequentially formed thereon. Electrode and Mo/Al source drain electrode.
- the SiO 2 film formed by the method is relatively loose, and the gate insulating property is generally, the density is 1.9-2.3 g cm" 3 , the refractive index is 1.43-1.45, and the dielectric strength is about 5.6 ⁇ 10 6 ⁇ -cm" 1 » Adaptable to Ordinary glass, Si0 2 film deposition time is about 1-10 min.
- Example 1 Drying Thermal Oxidation Process Using an Annealing Furnace to Obtain a Gate Insulation Layer
- the quartz substrate is cleaned, and a 50 nm thickness is sequentially deposited on the substrate by CVD.
- Si0 x and 300 ⁇ thick SiO 2 are used as a buffer layer, followed by deposition of amorphous silicon of 100 nm thickness, crystallization of amorphous silicon by excimer laser, and then passing the sample to 1% by volume of HF.
- the surface was treated and the sample was placed in an oven of dry pure oxygen (the volume of oxygen was greater than 98% and the volume of water was less than 10 ppm) and the annealing temperature was raised to 1000.
- C oxidized for 20 min, thereby forming a dense SiO 2 film of about 50 nm thick, and then forming a Mo gate electrode and a Mo/Al source drain electrode in this order.
- the SiO 2 film formed by the method is the most dense, the gate insulating property is the best, the density is 2.0-2.4 g cm" 3 , the refractive index is 1.45-1.47, and the dielectric strength is greater than 10 x 10 6 V.cm. High temperature glass, Si0 2 film growth time is greater than 20 min.
- the glass substrate is cleaned, and SiN x of 100 nm thickness and SiO 2 of 200 ⁇ thickness are sequentially deposited on the substrate by a CVD method as a buffer layer, and then amorphous silicon having a thickness of 100 nm is deposited, and an excimer laser is used.
- the amorphous silicon is crystallized, and then the sample is first treated with 1% by volume of HF, and then the sample is placed in a dry pure oxygen atmosphere (the volume of oxygen is greater than 98%, and the volume of water is less than 10).
- a near-infrared excimer laser with a high energy density (100-500 mJ.cm- 2 ) is again scanned to form a dense SiO 2 film of about 30 nm thick, and then a Mo gate is sequentially formed thereon.
- Electrode and Mo/Al source drain electrode are sequentially formed thereon.
- the SiO 2 film formed by the method has a compact structure, good gate insulating property, a density of 2.0-2.4 g cm" 3 , a refractive index of 1.45-1.47, and a dielectric strength of 9 x 10 6 V.cm.
- the method can be used at ordinary high temperatures.
- the glass is applied and the growth time of the Si0 2 film is approximately 30-60 min (for 370 mm 470 mm samples).
- the glass substrate is cleaned, and SiN x of 200 nm thickness and SiO 2 of 200 ⁇ thickness are sequentially deposited on the substrate by a CVD method as a buffer layer, and then amorphous silicon of 100 nm thickness is deposited, and an excimer laser is used.
- the crystallization process of amorphous silicon after which the sample is first treated with 1% by volume of HF, and then placed in an annealing furnace containing an oxygen atmosphere of 1000 ppm, the annealing temperature is raised to 400 ° C, and oxidized. 100 seconds, thereby forming a SiO 2 film of about 5-10 nm thick. Then use it on it
- the CVD method deposits Si0 2 with a thickness of 40 nm, and finally forms a Mo gate electrode and a Mo/Al source drain electrode in this order.
- the growth time of the SiO 2 film in the method is as follows: The thermal oxidation time is about 60-300 seconds, and then the CVD method is grown for about 60-300 seconds, the total time is about 2-10 min, and the active layer and the gate are insulated.
- the 5-10 nm SiO 2 film near the layer contact surface is denser and has good insulation properties.
- Thermal oxide film layer density 2.0-2.4 g'cm- 3 , refractive index 1.45-1.47, dielectric strength ⁇ 10 ⁇ 10 6 V-cm; CVD deposited film: density 2.0-2.2 g'cm- 3 , refractive index 1.43-1.45, Dielectric strength ⁇ 6 ⁇ 10 6 V'cm Therefore, the quality of the contact interface between the active layer and the gate insulating layer can be ensured, and the process can be adapted to ordinary glass.
- Embodiment 4 Gate insulating film formed of SiN x
- the quartz substrate is cleaned, and 50 nm of SiN x and 300 ⁇ of Si0 2 are sequentially deposited on the substrate by a CVD method as a buffer layer, followed by deposition of amorphous silicon of 100 nm thickness and excimer laser.
- the crystallization process of amorphous silicon after which the sample is first treated with 1% by volume of HF, and then in an atmosphere containing NH 3 , an ELA process (energy density of about 100-500 mJ-cm) 2
- a 50 nm thick SiN x film is grown, and a Mo gate electrode and a Mo/Al source drain electrode are sequentially formed thereon.
- the SiN film formed by the method is relatively dense and has good insulating properties, the density is 3.2-3.5 g.cm- 3 , the refractive index is 1.43-1.45, and the dielectric strength is >1 X 10 7 V.cm.
- the method can be adapted to ordinary glass.
- the deposition time of the film is about 10-30 min.
- the embodiment according to the present invention is not limited to the above examples.
- the source drain electrode 6 and the gate electrode 4 are all described above above the active layer 3, the embodiment of the present invention is not limited to this structure.
- the source/drain electrode 6 may also be below the active layer 3 and the gate electrode 4 may be above the active layer.
- the source/drain electrode 6 needs to be formed on the substrate.
- the active layer 3 may be Contact with the source/drain electrode 6.
- a process of forming a contact hole for contact between the source/drain electrode 6 and the active layer 3 in the gate insulating layer may be omitted.
- the present invention it is possible to form a dense gate insulating layer, reduce the thickness of the gate insulating layer and process time, while reducing leakage current of the TFT device and improving the electrical performance of the lifter. Therefore, in one aspect, the present invention reduces the surface state effect between the active layer and the gate insulating layer, and on the other hand, the dense gate insulating layer facilitates leakage current of the TFT device.
- the gate insulating layer includes a first gate insulating layer formed by oxidizing a portion of the semiconductor layer, and an unoxidized portion of the semiconductor layer forms an active layer, and
- the gate electrode is formed such that a gate insulating layer is interposed between the gate electrode and the active layer.
- the volume content of water is less than 10 ppm, or the oxygen content of the oxidizing atmosphere is more than 97%, and the volume content of water is 10-1000 ppm.
- a buffer layer is formed on the substrate before forming the semiconductor layer
- the semiconductor layer is formed by forming an amorphous silicon layer on the buffer layer and crystallizing the amorphous silicon layer into a polysilicon layer by an excimer laser method.
- a thin film transistor comprising a substrate, an active layer, a gate insulating layer, a gate electrode, and a source/drain electrode, wherein the gate insulating layer includes a first gate directly in contact with the active layer a very insulating layer, and the first gate insulating layer has a dielectric strength of at least 9 10 6 Yc
- the gate insulating layer further includes a second gate insulating layer on the first gate insulating layer,
- the second gate insulating layer is formed by a chemical vapor deposition method or a sputtering method.
- a display device comprising the thin film transistor according to any one of (13) to (15). Further, in the step of oxidizing the semiconductor in the above item (1), it is not limited to the above-described process of heating in an oxidizing atmosphere, but any suitable oxidation method may be employed. For example, it is also possible to oxidize a part of the semiconductor layer by injecting an element having an oxidizing property such as an oxygen element or a nitrogen element. At this time, the position of the oxidized portion can be controlled, for example, the bottom portion of the semiconductor layer is oxidized.
- the gate electrode and the source and drain electrodes may both be above the gate insulating layer, and the source and drain electrodes are in contact with the active layer through openings in the gate insulating layer; or the gate electrode is above the gate insulating layer, and the source The drain electrode is under the active layer to be in direct contact with the active layer.
- the gate electrode may be above the active layer or below the active layer as long as they are separated by a gate insulating layer.
- the first gate insulating layer of the TFT may have a dielectric strength of at least 9 ⁇ 10 6 Y-cm. Further, preferably, the first gate insulating layer has a mass density of 2.0-3.5 g. -cm" 3 hail
- the TFT according to an embodiment of the present invention can be used in a display device such as a liquid crystal display.
- a display device such as a liquid crystal display.
- An embodiment of the present invention also provides a display device comprising a thin film transistor according to any of the embodiments of the present invention or a thin film transistor fabricated according to the method of any of the embodiments of the present invention.
- Other components of the display device are known to those skilled in the art.
- these components include, but are not limited to: polarizers, common electrodes, alignment layers, sealants, liquid crystals, spacers, protective layers, organic semiconductor active layers, anisotropic conductive pastes (ACF), driver ICs , printed circuit board (PCB), control IC, black matrix (BM) and color film (CF).
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- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
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- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Formation Of Insulating Films (AREA)
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Abstract
Description
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EP12778033.6A EP2613346B1 (en) | 2011-11-11 | 2012-09-19 | Thin film transistor, manufacturing method thereof and display device |
US13/703,537 US9218957B2 (en) | 2011-11-11 | 2012-09-19 | Thin film transistor and manufacturing method thereof and display device |
KR1020147014697A KR101530503B1 (ko) | 2011-11-11 | 2012-09-19 | 박막 트랜지스터, 그 제조 방법 및 디스플레이 장치 |
JP2014540297A JP2015502029A (ja) | 2011-11-11 | 2012-09-19 | 薄膜トランジスタ及びその製造方法、表示デバイス |
KR1020127030806A KR101543829B1 (ko) | 2011-11-11 | 2012-09-19 | 박막 트랜지스터, 그 제조 방법 및 디스플레이 장치 |
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CN102646595A (zh) * | 2011-11-11 | 2012-08-22 | 京东方科技集团股份有限公司 | 薄膜晶体管及其制造方法、显示器件 |
CN102856392B (zh) * | 2012-10-09 | 2015-12-02 | 深圳市华星光电技术有限公司 | 薄膜晶体管主动装置及其制作方法 |
CN103456765B (zh) * | 2013-09-10 | 2015-09-16 | 深圳市华星光电技术有限公司 | 有源式有机电致发光器件背板及其制作方法 |
CN103489920B (zh) * | 2013-09-26 | 2016-08-17 | 京东方科技集团股份有限公司 | 一种薄膜晶体管及其制备方法、阵列基板和显示装置 |
CN106469750A (zh) * | 2015-08-19 | 2017-03-01 | 昆山工研院新型平板显示技术中心有限公司 | 薄膜晶体管及其制造方法 |
CN107170784A (zh) * | 2017-05-25 | 2017-09-15 | 京东方科技集团股份有限公司 | 一种oled阵列基板及其制备方法和oled显示装置 |
KR20210062129A (ko) * | 2019-11-20 | 2021-05-31 | 삼성디스플레이 주식회사 | 표시 장치 및 표시 장치의 제조 방법 |
CN112235948A (zh) * | 2020-10-13 | 2021-01-15 | 廖斌 | 一种柔性线路板制备方法及其制备的柔性线路板和该柔性线路板的应用 |
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US9218957B2 (en) | 2015-12-22 |
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KR101543829B1 (ko) | 2015-08-11 |
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US20140124787A1 (en) | 2014-05-08 |
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