WO2013064025A1 - 改善晶圆上栅极光刻关键尺寸均匀性的方法 - Google Patents

改善晶圆上栅极光刻关键尺寸均匀性的方法 Download PDF

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WO2013064025A1
WO2013064025A1 PCT/CN2012/083354 CN2012083354W WO2013064025A1 WO 2013064025 A1 WO2013064025 A1 WO 2013064025A1 CN 2012083354 W CN2012083354 W CN 2012083354W WO 2013064025 A1 WO2013064025 A1 WO 2013064025A1
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wafer
uniformity
gate
improving
reflective coating
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English (en)
French (fr)
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廖映雪
杨兆宇
许宗能
赵志勇
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无锡华润上华科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/091—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by antireflection means or light filtering or absorbing means, e.g. anti-halation, contrast enhancement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities

Definitions

  • the present invention relates to the field of semiconductor fabrication, and more particularly to a method for improving the uniformity of critical dimensions of gate lithography on a wafer, and to a dielectric anti-reflective coating.
  • CMOS complementary metal oxide semiconductor field effect transistor
  • the main method is to control the parameters in the recipe of the polysilicon gate lithography process, and generally adjust the focal length and NA in the lithography process. Parameters such as numerical aperture), sigma, energy, and photoresist thickness are used to improve.
  • a method for improving the uniformity of critical dimensions of gate lithography on a wafer comprising the steps of: providing a wafer, forming a gate layer on the surface of the wafer; depositing silicon oxynitride on the surface of the gate layer to form a dielectric An anti-reflective coating, wherein the thickness of the dielectric anti-reflective coating is less than 2% of the thickness of the target; coating the photoresist on the dielectric anti-reflective coating, and exposing the lithographic pattern forming the gate .
  • the thickness of the dielectric anti-reflective coating is controlled within 315 ⁇ 325 ⁇ , the N value is controlled within 2.09 ⁇ 2.11, and the K value is controlled within 0.62 ⁇ 0.66.
  • the deposition is chemical vapor deposition
  • the reaction gas includes SiH 4 , N 2 O and He
  • the flow rate of SiH 4 is 69-89 sccm
  • the flow rate of N 2 O is 130-230 sccm
  • the flow rate of He is 1800 ⁇ 2200 sccm
  • the deposition reaction pressure is 4 to 7 Torr
  • the deposition reaction power is 80 to 120 W.
  • the flow rate of the SiH 4 is 75 sccm.
  • the flow rate of the N 2 O is 210 sccm.
  • the flow rate of the He is 1900 sccm.
  • the deposition has a reaction pressure of 5.5 Torr.
  • the deposition has a reaction power of 95W.
  • the machine model used for the deposition is a Producer.
  • a dielectric anti-reflective coating is disposed on the surface of the gate layer and is made of silicon oxynitride.
  • the deviation of the thickness of the dielectric anti-reflective coating from the target thickness is less than 2%.
  • the above method for improving the critical dimension uniformity of gate lithography on a wafer uses an improved dielectric anti-reflective coating (DARC) to effectively control and adjust the polysilicon gate key by improving the uniformity of the thickness of SiON in the DARC.
  • DARC dielectric anti-reflective coating
  • the uniformity of the size achieves the purpose of solving leakage at the edge of the wafer. Compared with the traditional method of adjusting the lithography program, there is no need to re-plate and verify, which shortens the time and cost of yield improvement.
  • FIG. 1 is a flow chart of a method for improving the uniformity of critical dimensions of gate lithography on a wafer in an embodiment
  • FIG. 2 is a graph showing the critical dimension of a wafer polysilicon gate with a wafer margin as a polysilicon gate formed by a subsequent process using a conventional process of depositing a SiON dielectric anti-reflective coating using an AMAT 5000 machine;
  • Figure 3 is a comparison diagram of the curve shown in Figure 2 and the corresponding curve obtained by using the Producer machine and the parameters of the first preferred embodiment
  • Figure 4 is a graph showing thickness uniformity before and after improvement of the SiON deposition process
  • Figure 5 is a graph showing the uniformity of N value before and after the improvement of the SiON deposition process
  • Figure 6 is a graph showing the uniformity of K value before and after the improvement of the SiON deposition process
  • Figure 7 is a graph showing the leakage failure data of the wafer before and after the improvement of the SiON deposition process.
  • ARC anti-reflective coating
  • Dielectric anti-reflective coating made of SiON (silicon oxynitride) Anti-reflective Coating, DARC) is a type of ARC commonly used in lithography processes for polysilicon gates. According to research and experiments by the inventors, by improving the uniformity of the dielectric anti-reflective coating on the polysilicon gate, the problem that the critical dimension of the polysilicon gate at the edge of the wafer is smaller than the design value can be effectively solved, thereby solving the edge leakage. The problem of failure increases the yield of the product.
  • the thickness is proportional to the reaction pressure, the reaction power, the flow rate of N 2 O, the flow rate of SiH 4 , and inversely proportional to the flow rate of He;
  • the N value and the K value are proportional to the flow rate of SiH 4 and the flow rate of He It is inversely proportional to the reaction pressure, the reaction power, and the flow rate of N 2 O.
  • the N value and the K value are proportional to the reaction power and the flow rate of He, and are inversely proportional to the reaction pressure, the flow rate of SiH 4 , and the flow rate of N 2 O.
  • the present invention provides a method for improving the uniformity of the critical dimensions of gate lithography on a wafer, comprising the following steps:
  • the gate layer is made of polysilicon.
  • the deposition method is Chemical Vapor Deposition (CVD), and the deposited reaction gases include SiH 4 , N 2 O and He, the flow rate of SiH 4 is 69-89 sccm, and the flow rate of N 2 O is 130-230 sccm.
  • the flow rate of He is 1800 ⁇ 2200sccm, the reaction pressure of deposition is 4 ⁇ 7 Torr, and the reaction power of deposition is 80 ⁇ 120W.
  • the inventors also deposited a dielectric anti-reflective coating using a deposition machine model AMAT5000 and a deposition machine model Producer, respectively, and found a dielectric anti-reflective coating deposited using a Producer machine relative to the AMAT 5000 machine.
  • the uniformity of values, K values, and thicknesses is improved, resulting in improved uniformity of key dimensions of the polysilicon gate.
  • FIG. 2 is a graph showing the critical dimension of a wafer polysilicon gate with a wafer margin as a polysilicon gate formed by a subsequent process using a conventional process of depositing a SiON dielectric anti-reflective coating using an AMAT 5000 machine.
  • the abscissa indicates the distance from the edge of the wafer, and the ordinate indicates the critical dimension of the polysilicon gate. It can be seen that the critical dimension of the polysilicon gate is large in the middle and edge of the wafer.
  • Figure 3 is a graph comparing the curve shown in Figure 2 with the corresponding curve obtained using the Producer machine and the parameters of the first preferred embodiment. It can be seen that the uniformity of the critical dimensions of the polysilicon gate is greatly improved.
  • Figures 4, 5, and 6 are the thickness, N-value, and K-value uniformity of the SiON dielectric anti-reflective coating (before and after the improvement of the SiON deposition process) using the AMAT5000 machine conventional process and the first preferred embodiment of the Producer machine. The graph. It can be seen that the uniformity of thickness, N value, and K value is greatly improved. Referring to Fig. 3, although it is desired to obtain 320 ⁇ of SiON, there is still an error of approximately 5 ⁇ .
  • Figure 7 is a graph showing the leakage failure data of the wafer before and after the improvement of the SiON deposition process. After depositing the SiON dielectric anti-reflective coating with the first preferred embodiment of the Producer machine, the average leakage rate of the DIE is reduced to less than 1%.
  • the above method for improving the critical dimension uniformity of gate lithography on a wafer uses an improved dielectric anti-reflective coating (DARC) to effectively control the uniformity of the K value, the N value, and the thickness of the SiON in the DARC. And adjust the uniformity of the critical dimension of the polysilicon gate to achieve the purpose of solving the leakage of the edge of the wafer.
  • DARC dielectric anti-reflective coating

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Abstract

提供一种改善晶圆上栅极光刻关键尺寸均匀性的方法以及一种电介质防反射涂层。该方法包括以下步骤：提供晶圆，在所述晶圆表面形成栅极层（S110）；在所述栅极层表面淀积氮氧化硅，形成电介质防反射涂层，所述电介质防反射涂层任意一处的厚度与目标厚度的偏差都小于2%（S120）；在所述电介质防反射涂层上涂敷光刻胶，曝光形成栅极的光刻图案（S130）。上述方法使用一种改善后的电介质防反射涂层，通过改善电介质防反射涂层中氮氧化硅的厚度的均匀性，有效地控制和调整多晶硅栅极关键尺寸的均匀性，达到解决晶圆边缘漏电的目的。和传统的通过调整光刻程式的方法相比，不需重新制版及验证，缩短了良率改善的时间与成本。

Description

改善晶圆上栅极光刻关键尺寸均匀性的方法
【技术领域】
本发明涉及半导体制造领域，尤其涉及一种改善晶圆上栅极光刻关键尺寸均匀性的方法，还涉及一种电介质防反射涂层。
【背景技术】
在互补金属氧化物半导体场效应管（CMOS）芯片制造中，多晶硅（poly）栅的制程是一道非常重要的工序，多晶硅栅关键尺寸（poly CD）的大小会直接影响器件的各种电性参数。多晶硅栅关键尺寸的均匀性的控制因此变得非常重要。
一种传统的0.16微米栅极长度（LG）制程中，多晶硅栅光刻后关键尺寸的均匀性不好，尤其是在晶圆的边缘处，多晶硅栅关键尺寸比晶圆中心处小了10nm以上，导致在晶圆针测（Chip Probing, CP）的时候晶圆边缘出现特殊图案的漏电失效，严重影响产品良率和客户的信心，因此解决晶圆边缘漏电失效问题变的非常的重要。
目前为了解决晶圆边缘多晶硅栅关键尺寸偏小的问题，主要的做法是通过对多晶硅栅光刻工艺的程式（recipe）中参数的调试来控制，一般会调节光刻工艺中的焦距、NA（数值孔径）、sigma、能量、光刻胶厚度等参数来做改善。
但是这些参数的调整会影响到光刻胶轮廓（PR profile）和关键尺寸的大小，对光学临近效应修正（OPC）也会有相应影响，因此对光刻工艺程式中参数调整的方法成本高、效率低。
【发明内容】
基于此，有必要提供一种成本较低，效率高的改善晶圆上栅极光刻关键尺寸均匀性的方法。
一种改善晶圆上栅极光刻关键尺寸均匀性的方法，包括以下步骤：提供晶圆，在所述晶圆表面形成栅极层；在所述栅极层表面淀积氮氧化硅，形成电介质防反射涂层，所述电介质防反射涂层任意一处的厚度与目标厚度的偏差都小于2%；在所述电介质防反射涂层上涂敷光刻胶，曝光形成栅极的光刻图案。
优选的，所述电介质防反射涂层的厚度控制在315~325Ǻ内，N值控制在2.09~2.11内，K值控制在0.62~0.66内。
优选的，所述淀积为化学气相淀积，反应气体包括SiH4， N2O以及He，SiH4的流量为69~89sccm， N2O的流量为130~230sccm，He的流量为1800~2200sccm，所述淀积的反应压力为4~7 Torr，所述淀积的反应功率为80~120W。
优选的，所述 SiH4的流量为75 sccm。
优选的，所述 N2O的流量为210sccm。
优选的，所述He的流量为1900sccm。
优选的，所述淀积的反应压力为5.5 Torr。
优选的，所述淀积的反应功率为95W。
优选的，所述淀积使用的机台型号为Producer。
还有必要提供一种改善后的电介质防反射涂层。
一种电介质防反射涂层，设于栅极层的表面，材质为氮氧化硅，所述电介质防反射涂层任意一处的厚度与目标厚度的偏差都小于2%。
上述改善晶圆上栅极光刻关键尺寸均匀性的方法，使用一种改善后的电介质防反射涂层（DARC），通过改善DARC中SiON的厚度的均匀性，有效地控制和调整多晶硅栅极关键尺寸的均匀性，达到解决晶圆边缘漏电的目的。和传统的通过调整光刻程式的方法相比，不需重新制版及验证，缩短了良率改善的时间与成本。
【附图说明】
图1是一实施例中改善晶圆上栅极光刻关键尺寸均匀性的方法的流程图；
图2是一种使用AMAT5000机台传统工艺淀积SiON电介质防反射涂层后通过后续的工艺形成多晶硅栅极的晶圆多晶硅栅极关键尺寸随晶圆边距变化的曲线图；
图3是图2所示曲线与采用Producer机台及第一优选实施例的参数得到的相应曲线的比较图；
图4是SiON淀积工艺改善前后的厚度均匀性的曲线图；
图5是SiON淀积工艺改善前后的N值均匀性的曲线图；
图6是SiON淀积工艺改善前后的K值均匀性的曲线图；
图7是SiON淀积工艺改善前后晶圆的漏电失效数据图。
【具体实施方式】
为使本发明的目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
传统的光刻工艺中，普遍使用抗反射涂层（ARC）工艺以降低驻波效应。材质为SiON（氮氧化硅）的电介质防反射涂层（Dielectric Anti-reflective Coating, DARC）是ARC中的一种，常用于多晶硅栅极的光刻工艺中。经发明人研究及实验发现，通过改善多晶硅栅极上的电介质防反射涂层的均匀性，能够有效的解决晶圆边缘的多晶硅栅极的关键尺寸比设计值偏小的问题，从而解决边缘漏电失效问题，提升产品的良品率。
为了使得电介质防反射涂层能够获得良好的均匀性，通过大量的实验发现，淀积SiON的工艺中每个工艺参数的变化和电介质防反射涂层的厚度、N值、K值、N值的范围、K值的范围都有密切的关系。例如在一定范围内，厚度与反应压力、反应功率、N2O的流量、SiH4的流量成正比，与He的流量成反比； N值、K值与SiH4的流量 、 He的流量成正比，与反应压力、反应功率、N2O的流量成反比 ；N值、K值与反应功率、He 的流量成正比，与反应压力、 SiH4的流量、N2O的流量成反比。
根据上述关系辅以大量实验，如图1所示，本发明提供一种改善晶圆上栅极光刻关键尺寸均匀性的方法，包括下列步骤：
S110，提供晶圆，在晶圆表面形成栅极层。该栅极层的材质为多晶硅。
S120，在栅极层表面淀积氮氧化硅，形成电介质防反射涂层，控制电介质防反射涂层任意一处的厚度与目标厚度的偏差都小于2%。即厚度非常均匀。
S130，在电介质防反射涂层上涂敷光刻胶，曝光形成栅极的光刻图案。
淀积的方式为化学气相淀积（Chemical Vapor Deposition, CVD），淀积的反应气体包括SiH4，N2O以及He，SiH4的流量为69~89sccm，N2O的流量为130~230sccm，He的流量为1800~2200sccm，淀积的反应压力为4~7Torr ，淀积的反应功率为80~120W。
实验数据表明在上述的参数范围内，电介质防反射涂层的厚度、N值、K值的均匀性，以及多晶硅栅极的关键尺寸在晶圆边缘减小的问题就能得到显著改善。可以理解的，发明人在此基础上通过实验单独确定了每个参数的一个优选值：SiH4的流量为75 sccm，N2O的流量为210sccm，He的流量为1900sccm，淀积的反应压力为5.5 Torr，淀积的反应功率为95W，电介质防反射涂层的厚度为320Ǻ。
下表为第一优选实施例中各参数的值。
淀积的反应压力 5.5 Torr
SiH4的流量 75 sccm
N2O的流量 210 sccm
淀积的反应功率 95 W
He的流量 1900 sccm
发明人还分别使用型号为AMAT5000的淀积机台与型号为Producer的淀积机台淀积电介质防反射涂层，发现使用Producer机台相对于AMAT5000机台淀积的电介质防反射涂层，N值、K值、厚度的均匀性都得到了改善，从而使得多晶硅栅极的关键尺寸的均匀性也得到了改善。
图2是一种使用AMAT5000机台传统工艺淀积SiON电介质防反射涂层后通过后续的工艺形成多晶硅栅极的晶圆多晶硅栅极关键尺寸随晶圆边距变化的曲线图。横坐标表示与晶圆边缘的距离，纵坐标表示多晶硅栅极的关键尺寸，可以看到多晶硅栅极的关键尺寸在晶圆中部和边缘差距较大。
图3是图2所示曲线与采用Producer机台及第一优选实施例的参数得到的相应曲线的比较图。可以看到多晶硅栅极的关键尺寸的均匀性得到了极大改善。图4、5、6分别是使用AMAT5000机台传统工艺及Producer机台第一优选实施例淀积SiON电介质防反射涂层（即SiON淀积工艺改善前后）的厚度、N值、K值均匀性的曲线图。可以看到厚度、N值、K值的均匀性都得到了极大改善。参看图3，虽然期望获得320Ǻ的SiON，但实际仍然会有接近5Ǻ的误差。图7是SiON淀积工艺改善前后晶圆的漏电失效数据图。采用Producer机台第一优选实施例淀积SiON电介质防反射涂层后DIE的平均漏电率降到了1%以下。
上述改善晶圆上栅极光刻关键尺寸均匀性的方法，使用一种改善后的电介质防反射涂层（DARC），通过改善DARC中SiON的K值、N值和厚度的均匀性，有效地控制和调整多晶硅栅极关键尺寸的均匀性，达到解决晶圆边缘漏电的目的。和传统的通过调整光刻程式的方法相比，不需重新制版及验证，缩短了良率改善的时间与成本，提升客户对产品信心。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种改善晶圆上栅极光刻关键尺寸均匀性的方法，包括以下步骤：
    提供晶圆，在所述晶圆表面形成栅极层；
    在所述栅极层表面淀积氮氧化硅，形成电介质防反射涂层，所述电介质防反射涂层任意一处的厚度与目标厚度的偏差都小于2%；
    在所述电介质防反射涂层上涂敷光刻胶，曝光形成栅极的光刻图案。
  2. 根据权利要求1所述的改善晶圆上栅极光刻关键尺寸均匀性的方法，其特征在于，所述电介质防反射涂层的厚度控制在315~325 Ǻ内，N值控制在2.09~2.11内，K值控制在0.62~0.66内。
  3. 根据权利要求1或2所述的改善晶圆上栅极光刻关键尺寸均匀性的方法，其特征在于，所述淀积为化学气相淀积，反应气体包括SiH4，N2O以及He，SiH4的流量为69~89sccm，N2O的流量为130~230sccm，He的流量为1800~2200sccm，所述淀积的反应压力为4~7 Torr，所述淀积的反应功率为80~120W。
  4. 根据权利要求3所述的改善晶圆上栅极光刻关键尺寸均匀性的方法，其特征在于，所述SiH4的流量为75 sccm。
  5. 根据权利要求3所述的改善晶圆上栅极光刻关键尺寸均匀性的方法，其特征在于，所述N2O的流量为210sccm。
  6. 根据权利要求3所述的改善晶圆上栅极光刻关键尺寸均匀性的方法，其特征在于，所述He的流量为1900sccm。
  7. 根据权利要求3所述的改善晶圆上栅极光刻关键尺寸均匀性的方法，其特征在于，所述淀积的反应压力为5.5 Torr。
  8. 根据权利要求3所述的改善晶圆上栅极光刻关键尺寸均匀性的方法，其特征在于，所述淀积的反应功率为95W。
  9. 根据权利要求3所述的改善晶圆上栅极光刻关键尺寸均匀性的方法，其特征在于，所述淀积使用的机台型号为Producer。
  10. 一种电介质防反射涂层，设于栅极层的表面，材质为氮氧化硅，其特征在于，所述电介质防反射涂层任意一处的厚度与目标厚度的偏差都小于2%。
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