TW546709B - Method to reduce the reflectivity of polysilicon layer - Google Patents

Method to reduce the reflectivity of polysilicon layer Download PDF

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TW546709B
TW546709B TW91111471A TW91111471A TW546709B TW 546709 B TW546709 B TW 546709B TW 91111471 A TW91111471 A TW 91111471A TW 91111471 A TW91111471 A TW 91111471A TW 546709 B TW546709 B TW 546709B
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silicon layer
polycrystalline silicon
chemical vapor
vapor deposition
layer
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TW91111471A
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Chinese (zh)
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Shyh-Dar Lee
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Silicon Integrated Sys Corp
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Abstract

The present invention provides a method to reduce the reflectivity of polysilicon layer, which comprises: firstly providing a semiconductor substrate; then, disposing the semiconductor substrate in the reactor of a single-wafer type chemical vapor deposition; then, introducing silicon-containing gas into the reacting chamber of the single-wafer type chemical vapor deposition, so as to form a polysilicon layer on the surface of the semiconductor substrate; next, introducing hydrogen gas into the reacting chamber of the single-wafer type chemical vapor deposition, so as to adjust the grain size on the upper surface of the polysilicon layer; further introducing oxygen and ammonia gas sequentially into the reacting chamber of the single-wafer type chemical vapor deposition, so as to form silicon oxide film and silicon nitride film on the polysilicon layer, thereby reducing the reflectivity of polysilicon layer.

Description

546709 五、發明說明(l) . ' -- 發明領域 ,本發明係有關於半導體裝置(semiconduct〇r deviee) 的製程技術’特別是有關於利用在之單一晶圓式化學氣相 沈積的反應室(single — wafer« chemicai vap0r deposition chamber),亦即以同步製程(in — situ process)來降低複晶石夕層(p〇iysiiic〇n iayer)反射率的 方法。 相關技術之描述 在半導體裝置的製程步驟,光線由微影系統 (photolithography system)的光源供應,通過光罩 (photo-mask),然後將光罩上的圖案轉移至下層的光阻層 (photoresist)。然而當位於光阻層下方的材料屬於高反 射率材料(high reflectivity material),例如金屬層 (metal layer)或是複晶矽層時,當光線照射於上述高反 射率材料,容易造成不當的反射而大幅地破壞圖案的解析 度,此光線反射而影響圖案解析度涉及若干機制。 為了降低光線的反射而解決上述問題,業者提出一種 在複晶碎層以及光阻層之間設置一防反射層(a n t i ~ ref lection layer ; AL)的方法,亦即在塗佈光阻層之前 ,於上述複晶矽層等高反射率的材料的表面先以化學氣相 沈積法或是旋塗法(spin coating),以形成習稱的底部防 反射塗覆物(bottom anti-reflection coating ;BARC), 以下舉一例子以說明相關的習知技術。 請參照第1圖,其顯示根據習知技術形成具有低反射546709 V. Description of the invention (l). --- In the field of the invention, the present invention relates to a process technology of semiconductor device deviee ', and particularly to a reaction chamber utilizing a single wafer type chemical vapor deposition (Single — wafer «chemicai vap0r deposition chamber), that is, a method of reducing the reflectivity of the polycrystalline SiO2 layer in a situ process. Description of the Related Art In the manufacturing process steps of a semiconductor device, light is supplied by a light source of a photolithography system, passes through a photo-mask, and then the pattern on the photomask is transferred to the lower photoresist layer. . However, when the material under the photoresist layer is a high reflectivity material, such as a metal layer or a polycrystalline silicon layer, when light irradiates the above high reflectivity material, it is easy to cause improper reflection. While the resolution of the pattern is greatly destroyed, the reflection of light to affect the resolution of the pattern involves several mechanisms. In order to reduce the reflection of light and solve the above-mentioned problem, the industry proposes a method of providing an anti-ref lection layer (AL) between the multi-crystal broken layer and the photoresist layer, that is, before coating the photoresist On the surface of the highly reflective material such as the polycrystalline silicon layer, a chemical vapor deposition method or a spin coating method is first used to form a commonly-known bottom anti-reflection coating (bottom anti-reflection coating; BARC), an example is given below to illustrate the related conventional technology. Please refer to FIG. 1, which shows a low reflection formed by a conventional technique.

0702-7678TWF(N) * 91P03 ; Jessica.ptd 第4頁 546709 五、發明說明(2) 率之複晶石夕層表面的流程圖。 第1圖顯示根據習知技術形成具有低反射率之複晶矽 層表面的流程圖,習知技術可用步驟S3〇1〜S3〇5來表示。 首先’在步驟S3 01之中,表示將半導體基底放置於批式化 學氣相沈積(batch-type chemical vapor deposition)的 反應室内。在步驟S302之中,顯示將Si札導入批式反應室 内’以在半導體基底上方形成複晶矽層。接著,在步驟 S303之中,表示將上述半導體基底移至電漿加強型化學氣 相沈積(plasma enhanced chemical vapor deposition ; PECVD)反應室。然後,在步驟33〇4,顯示在電漿加強型化 學氣相沈積的反應室之中,沈積氮氧矽化合物層,以在複 晶石夕層表面形成防反射層。然後,步驟S3〇5則是顯示進行 傳統的微影製程(photolithography)以及餘刻步驟 (etching),以得到想要的複晶矽圖案,例如閘極電極 (gate electrode) 〇 習知技術利用批式化學氣相沈積的反應室能夠在複數 片的半導體基底(半導體晶圓)的表面同時形成複晶矽層, 而節省每一片半導體晶圓的製程時間以及製作成本。然而 由於近年來先進技術的電路密度漸漸地縮小化,已難以承 受半導體製程技術不精確,例如利用批式化學氣相沈積的 反應室沈積的複晶矽層通常均一度不佳。再者,由於批式 化學氣相沈積的反應室的具有相對大的容積,因此,進行 沈積複晶矽層的過程中,會產生大量的顆粒以及殘留物 質’有可能在後續製程產生嚴重的問題。0702-7678TWF (N) * 91P03; Jessica.ptd Page 4 546709 V. Description of the invention (2) Flow chart of the surface of the polycrystalite layer. Fig. 1 shows a flow chart of forming a surface of a polycrystalline silicon layer having a low reflectance according to a conventional technique. The conventional technique can be represented by steps S301 to S305. First, in step S301, it means that the semiconductor substrate is placed in a reaction chamber of a batch-type chemical vapor deposition. In step S302, it is shown that Si is introduced into a batch reaction chamber 'to form a polycrystalline silicon layer over a semiconductor substrate. Next, in step S303, it is indicated that the semiconductor substrate is moved to a plasma enhanced chemical vapor deposition (PECVD) reaction chamber. Then, in step 3304, it is shown that in the reaction chamber of the plasma enhanced chemical vapor deposition, an oxynitride layer is deposited to form an anti-reflection layer on the surface of the polycrystallite layer. Then, step S305 is performed by performing a conventional photolithography process and an etching step to obtain a desired polycrystalline silicon pattern, such as a gate electrode. A chemical vapor deposition reaction chamber can simultaneously form a polycrystalline silicon layer on the surface of a plurality of semiconductor substrates (semiconductor wafers), thereby saving the process time and cost of each semiconductor wafer. However, due to the gradual reduction of the circuit density of advanced technologies in recent years, it has been difficult to withstand the inaccuracy of semiconductor process technology. For example, the polycrystalline silicon layer deposited by the reaction chamber of batch chemical vapor deposition is usually uniformly poor. Furthermore, due to the relatively large volume of the batch chemical vapor deposition reaction chamber, during the deposition of the polycrystalline silicon layer, a large number of particles and residual substances may be generated, which may cause serious problems in subsequent processes. .

0702-7678TWF(N) ; 91P03 ; Jessica.ptd 5467090702-7678TWF (N); 91P03; Jessica.ptd 546709

再者,利用習知技術,係分別在不 中進行沈積’以形成上述複晶石夕二相沈積 :2構成的防反㈣,此將導致 )乳: 二’有需要提供一種能夠降低 。因 習知技術之缺點的方法。 H <反射率並且改良 發明之概述及目的 圓 式化 法0 之及,本發明的另一目的在於提供—種降低複晶矽層 之反射率的方法,其能夠提昇沈積物質的均—度。再者 ,據本發明的方法,能夠在單一晶圓式化學氣^沈積法以 處理或是使複晶矽層產生反應而降低反射率。因此,根據 本發明的方法能夠縮短製程時間。‘ ^ 根據上述目的’本發明提供一種降低複晶石夕層之反射 率的方法,首先,提供一半導體基底,接著,將上述半導 體基底放置於單一晶圓式化學氣相沈積的反應器。然後, 導入含矽氣體(例如甲矽烷(或稱矽烷)-Si Η4)於上述單一 晶圓式化學氣相沈積的反應室内,以在上述半導體基底的 表面形成一複晶矽層。其次,導入氫氣於上述單一晶圓式 化學氣相沈積的反應室内,以調整上述複晶矽層上表面的 晶粒尺寸(grain size)。再者,導入氧氣於上述單一晶圓 式化學氣相沈積的反應室内,以在上述複晶秒層上方形成 二氧化矽薄膜,而能夠降低複晶矽層的反射率。Furthermore, using conventional techniques, the deposition is performed separately in order to form the above-mentioned two-phase sparite two-phase deposition: 2 anti-backlash, which will lead to) milk: Second, there is a need to provide a can reduce. Because of the shortcomings of conventional technology. H < Overview of reflectivity and improvement of the invention and purpose of rounding method 0, another object of the present invention is to provide a method for reducing the reflectance of a polycrystalline silicon layer, which can improve the uniformity of the deposited material . Furthermore, according to the method of the present invention, the single-wafer type chemical gas deposition method can be used to process or cause the polycrystalline silicon layer to react and reduce the reflectance. Therefore, the method according to the present invention can shorten the process time. ^ ^ According to the above object, the present invention provides a method for reducing the reflectance of a polycrystalline spar layer. First, a semiconductor substrate is provided, and then the semiconductor substrate is placed in a single wafer type chemical vapor deposition reactor. Then, a silicon-containing gas (for example, silane (or silane) -SiSi4) is introduced into the reaction chamber of the single-wafer chemical vapor deposition to form a polycrystalline silicon layer on the surface of the semiconductor substrate. Next, hydrogen is introduced into the single-wafer type chemical vapor deposition reaction chamber to adjust the grain size of the upper surface of the polycrystalline silicon layer. Furthermore, oxygen is introduced into the reaction chamber of the single-wafer chemical vapor deposition to form a silicon dioxide film above the polycrystalline second layer, thereby reducing the reflectance of the polycrystalline silicon layer.

0702-7678TWF(N) ; 91P03 ; Jessica.ptd 第6頁 546709 五、發明說明(4) 再者’上述降低複晶矽層之反射率的方法也可以在形 成一氧化石夕薄膜之後,導入氨氣於上述單一晶圓式化學氣 相沈積的反應室内,以處理上述複晶矽層表面而形成氮化 矽薄膜。 再者’上述降低複晶矽層之反射率的方法,更包括導 入一氧化二氮於上述單一晶圓式化學氣相沈積的反應室内 ’以處理上述複晶矽層表面而形成氮氧矽化合物薄膜的步 再者’上述降低複晶石夕層之反射率的方法之中,複晶 石夕層的厚度介於500埃至2500埃之間。並且,複晶矽層的 沈積溫度最好介於350 °C至680 °C之間。而沈積壓力大約介 於 150mtorr 至 40 0mtorr 之間。 再者’為了更進一步地降低複晶矽層的反射率,上述 降低複晶石夕層之反射率的方法,也可以更包括下列步驟: 將上述半導體基底移至一電漿加強型化學氣相沈積之反應 室;以及在上述二氧化矽薄膜表面形成一氮氡矽化物薄 膜0 根據上述目的,本發明提供另一種降低複晶矽層之反 =法’ f先,提供一半導體基底。然後,將上述半 導^基j放置於單-晶圓式化學氣相沈積的反應器,接著 内導::矽氣體於上述單一晶圓式化學氣相沈積的反應室 :丄1 述半導體基底的表面形成-複晶矽層。然後, 導入氰軋以及一氧化二氮於上述單一曰交 的反應室Μ,以在上述複晶#上化子乳相沈積 日矽層上方形成氮氧矽化合物薄0702-7678TWF (N); 91P03; Jessica.ptd Page 6 546709 V. Description of the invention (4) Furthermore, the method of reducing the reflectance of the polycrystalline silicon layer described above can also be introduced after the formation of a monolithic oxide film. Gas is placed in the reaction chamber of the single-wafer chemical vapor deposition to process the surface of the polycrystalline silicon layer to form a silicon nitride film. Furthermore, the method for reducing the reflectivity of the polycrystalline silicon layer further includes introducing nitrous oxide into the reaction chamber of the single-wafer chemical vapor deposition to treat the surface of the polycrystalline silicon layer to form an oxynitride compound. In the method of the thin film, in the above method for reducing the reflectance of the polycrystalline stone layer, the thickness of the polycrystalline stone layer is between 500 Angstroms and 2500 Angstroms. Moreover, the deposition temperature of the polycrystalline silicon layer is preferably between 350 ° C and 680 ° C. The deposition pressure is between 150mtorr and 400mtorr. Furthermore, in order to further reduce the reflectivity of the polycrystalline silicon layer, the method for reducing the reflectivity of the polycrystalline silicon layer may further include the following steps: moving the semiconductor substrate to a plasma-enhanced chemical vapor phase A reaction chamber for deposition; and forming an arsine silicide film on the surface of the silicon dioxide film. According to the above object, the present invention provides another inverse method for reducing a polycrystalline silicon layer. First, a semiconductor substrate is provided. Then, the above semiconductor substrate is placed in a single-wafer type chemical vapor deposition reactor, and then an internal guide: a silicon gas in the above single-wafer chemical vapor deposition reaction chamber: 丄 1 the semiconductor substrate The surface is formed-a polycrystalline silicon layer. Then, cyanide rolling and nitrous oxide are introduced into the above-mentioned single-pass reaction chamber M to form a thin layer of silicon oxynitride on the above-mentioned complex crystal # where the milk phase is deposited and the silicon oxide layer is formed.

546709546709

五、發明說明(5) 膜。 實施例 【第一實施例】 以下利用第4A圖〜第4D圖所示之降低複晶矽層之反射 率的製程剖面圖,以說明本發明的第一實施例。 首先,請參照第4A圖,提供一由單晶矽材料構成的半 導體基底1 0 0 (半導體晶圓),然後將其放置於單一晶圓式 化學氣相沈積(single-wafer type CVD)的反應室内,7列 如採用由應用材料(Appl ied Mater ials ; AMAT)公司製造 的單一晶圓式機台,商品名為” TPCC”(Thermal Pr^eess Common Centura ) 〇 接下來,請參照第4B圖,將矽烷(silane)導入上述單 一晶圓式化學氣相沈積的反應室内,以在上述半導體基底 100表面形成厚度大約介於5 0 0埃至2500埃的複晶矽層 1 0 2 ’上述複晶石夕層1 〇 2的沈積溫度被控制在大3 5 〇至6 8 〇 C左右’而沈積壓力被控制在i5〇mtorr至400mtorr左右。 然後’請參照第4 C圖,將氫氣(h2 )導入上述單一晶圓式化 學氣相沈積的反應室内,以調整上述複晶矽層丨〇 2上表面 的矽晶粒的尺寸。之後,將氧氣(〇2)導入上述單一晶圓式 化學氣相沈積的反應室内,以在上述複晶矽層丨〇 2表面形 成二Γ氧化石夕薄膜1 0 4 ’因而降低複晶石夕層1 〇 2表面的反射 率 〇 其次’請參照第4 D圖,為了更進一步地降低複晶石夕層 102表面的反射率,最好再將氮氧(NH3)及/或一氧化二氮5. Description of the invention (5) Membrane. EXAMPLES [First Example] The following is a cross-sectional view of a process for reducing the reflectance of a polycrystalline silicon layer shown in FIGS. 4A to 4D to describe a first embodiment of the present invention. First, please refer to FIG. 4A, and provide a semiconductor substrate 100 (semiconductor wafer) made of a single crystal silicon material, and then place it in a single-wafer type CVD reaction Indoor, 7 columns, if using a single wafer type machine manufactured by Applied Materials (AMAT) company, the trade name is "TPCC" (Thermal Pr ^ eess Common Centura). ○ Next, please refer to Figure 4B Silane is introduced into the reaction chamber of the single-wafer chemical vapor deposition to form a polycrystalline silicon layer 10 2 ′ on the surface of the semiconductor substrate 100 with a thickness of about 500 angstroms to 2500 angstroms. The deposition temperature of the spar evening layer 102 is controlled at about 3500 to 680 ° C, and the deposition pressure is controlled at about 500mtorr to 400mtorr. Then, referring to FIG. 4C, hydrogen (h2) is introduced into the single-wafer chemical vapor deposition reaction chamber to adjust the size of the silicon crystal grains on the upper surface of the polycrystalline silicon layer. After that, oxygen (〇2) is introduced into the reaction chamber of the single-wafer chemical vapor deposition to form a di-titanium oxide thin film 104 on the surface of the polycrystalline silicon layer 〇2, thereby reducing polycrystalline silicon. Reflectivity on the surface of layer 1 〇 2 Secondly, please refer to Figure 4D. In order to further reduce the reflectance on the surface of the polycrystalline stone layer 102, it is best to add nitrogen oxide (NH3) and / or nitrous oxide

〇702-7678TWF(N) » 91P03 ; Jessica.ptd 第8頁 546709〇702-7678TWF (N) »91P03; Jessica.ptd Page 8 546709

(化〇)導入上述單一晶圓式化學氣相沈積的反應室内,以 ,上述已形成有二氧化矽薄膜104的複晶矽層1〇2上方形成 氮化石夕或是氮氧矽化合物的含氮薄膜丨〇 6。 第2圖顯不根據本發明第一實施例形成具有低反射率 之複晶石夕層表面的流程圖,本實施例亦可用步驟34〇1〜步 驟=05來表示。首先,在步驟84〇1表示將半導體基底放置 於單一晶圓式化學氣相沈積的反應室内。步驟S4〇2表示將 S1 &導入反應室内以在半導體基底上方形成複晶矽層。接 著,步驟S 4 0 3表示將氫氣導入上述反應室以調整複晶矽層 表面的矽晶粒尺寸。步驟S404表示將氧氣導入上述反應^ 以在上述複晶矽層表面形成二氧化矽薄膜。最後,在步驟 S405之中,將氨氣(別^及/或一氧化二氮(N2〇)導入上述反 應室以降低上述複晶矽層的反射率。 【第二實施例】 以下利用第5 A圖〜第5 D圖所示之降低複晶矽層之反射 率的製程剖面圖,以說明本發明的第二實施例。 首先’請參照第5 A圖,提供一由單晶矽材料構成的半 導體基底200 (半導體晶圓),然後將其放置於單一晶圓式 化學氣相沈積(single-wafer type CVD)的反應室内,例 如採用由應用材料(Applied Materials ;AMAT)公司製造 的單一晶圓式機台,商品名為”TPCCn (Thermal Process Common Centura) 〇 接下來’請參照第5B圖’將石夕烧(silane)導入上述單 一晶圓式化學氣相沈積的反應室内,以在上述半導體基底(Chemical) is introduced into the single-wafer chemical vapor deposition reaction chamber, so that a nitrided silicon nitride or silicon oxynitride-containing silicon compound is formed over the polycrystalline silicon layer 10 on which the silicon dioxide film 104 has been formed. Nitrogen thin film 〇〇6. Fig. 2 shows a flow chart of forming a polycrystalline stone layer surface with a low reflectance according to the first embodiment of the present invention. This embodiment can also be represented by steps 3401 ~ 5. First, in step 8401, a semiconductor substrate is placed in a single-wafer chemical vapor deposition reaction chamber. Step S402 refers to introducing S1 & into the reaction chamber to form a polycrystalline silicon layer over the semiconductor substrate. Next, step S403 indicates that hydrogen is introduced into the reaction chamber to adjust the silicon grain size on the surface of the polycrystalline silicon layer. Step S404 indicates that oxygen is introduced into the reaction to form a silicon dioxide film on the surface of the polycrystalline silicon layer. Finally, in step S405, ammonia gas (not nitrogen and / or nitrous oxide (N2O)) is introduced into the reaction chamber to reduce the reflectance of the polycrystalline silicon layer. [Second Embodiment] The following uses the fifth The process cross-sectional views of the process for reducing the reflectance of the polycrystalline silicon layer shown in Figures A to 5D are used to illustrate the second embodiment of the present invention. First, please refer to Figure 5A to provide a single crystal silicon material. Semiconductor substrate 200 (semiconductor wafer), and then place it in a single-wafer type CVD reaction chamber, such as a single crystal manufactured by Applied Materials (AMAT) Round type machine, trade name is “TPCCn (Thermal Process Common Centura).” Next, “Please refer to FIG. 5B”, introduce silane into the above single wafer chemical vapor deposition reaction chamber to Semiconductor substrate

0702-7678TWF(N) ; 91P03 ; Jessica.ptd 第 頁 546709 五、發明說明(7) 200表面形成厚度大約介於5〇q埃至2500埃的複晶矽層2〇2 ’上述複晶矽層2 0 2的沈積溫度被控制在大3 5 0 °C至6 8 0 °C 左右’而沈積壓力被控制在15〇mtorr至400mtorr左右。 然後’請參照第5(:圖,將.氨氣(〇3)及/或一氧化二氮 (\0)導入上述上述單一晶圓式化學氣相沈積的反應室内 ’以在上述複晶石夕層2 〇 2形成一由氮化石夕或是氮氧石夕化合 物構成的含氮薄膜204。上述含氮薄膜204能夠降低複晶矽 層2 0 2的反射率,並且與上述複晶矽層2 〇 2係在同一反應室 之中沈積而成。 接著,將上述半導體基底200移至電漿加強型化學氣 相沈積(plasma enhanced chemical vapor deposition ; PECVD)之反應室,接下來,在上述含氮薄膜204的表面形 成由氧氧矽化合物層2 0 6,當作防反射層,以更進一步地 降低複晶矽層2 0 2的反射率。 第3圖顯示根據本發明第二實施例形成具有低反射率 之複晶矽層表面的流程圖,本實施例亦可用步驟s 5 〇 1〜步 驟S505來表示。首先,在步驟S501表示將半導體基底放置 於單一晶圓式化學氣相沈積的反應室内。步驟S 5 〇 2表示將 S i Η*導入反應至内以在半導體基底上方形成複晶秒層。接 著,步驟S 503表示將氨氣及/或一氧化二氮導入上述反應 室以,降低複晶矽層的反射率,步驟S5 04表示將半導體基底 移至電漿加強型化學氣相沈積之反應室。最後,步驟s 5 〇 5 之中,在上述複晶矽層上方沈積氮氧矽化合物層以當作防 反射層。0702-7678TWF (N); 91P03; Jessica.ptd Page 546709 V. Description of the invention (7) 200 A polycrystalline silicon layer having a thickness of about 50q Angstroms to 2500 Angstroms is formed on the surface of the polycrystalline silicon layer 202 The deposition temperature of 2 0 2 was controlled to be approximately 350 ° C to 680 ° C and the deposition pressure was controlled to be 150 mtorr to 400 mtorr. Then, "Please refer to Fig. 5 (: figure, introduce the ammonia gas (〇3) and / or nitrous oxide (\ 0) into the above-mentioned single wafer-type chemical vapor deposition reaction chamber" to the above-mentioned polymorphite The layer 2 02 forms a nitrogen-containing thin film 204 composed of a nitride nitride or an oxynitride compound. The nitrogen-containing thin film 204 can reduce the reflectance of the polycrystalline silicon layer 202, and is similar to the polycrystalline silicon layer. 02 is deposited in the same reaction chamber. Next, the semiconductor substrate 200 is moved to a plasma enhanced chemical vapor deposition (PECVD) reaction chamber. The surface of the nitrogen thin film 204 is formed of an oxy-silicon compound layer 2 06 as an anti-reflection layer to further reduce the reflectance of the polycrystalline silicon layer 2 0. FIG. 3 shows the formation according to the second embodiment of the present invention. The flowchart of the surface of the polycrystalline silicon layer with low reflectivity can also be expressed in steps s501 to S505. First, in step S501, the semiconductor substrate is placed on a single wafer type chemical vapor deposition. Reaction chamber. Step S 5 〇2 It is shown that Si Η * is introduced into the reaction to form a polycrystalline second layer above the semiconductor substrate. Next, step S503 indicates that ammonia gas and / or nitrous oxide are introduced into the reaction chamber to reduce the reflection of the polycrystalline silicon layer. Rate, step S504 means that the semiconductor substrate is moved to a plasma enhanced chemical vapor deposition reaction chamber. Finally, in step s505, a silicon oxynitride layer is deposited on the above-mentioned polycrystalline silicon layer as a precaution Reflective layer.

0702-7678TWF(N) ; 91P03 ; Jessica.ptd 第 10 頁 546709 五、發明說明(8) 發明之特徵及功效 根據本發明以單一 低複晶矽層之反射率的方法:能以目:積的反應室以降 度。 句&幵沈積物質的均一 再者,根據本發明的方法, 。一 相沈積法以處理或是使複晶石夕 ^ 一晶圓式化學氣 因此,根據本發明的方、、t At曰產生反應而降低反射率。 4旧万决旎夠縮短芻 雖然本發明已以較佳者二短W時間。 限定本發明,任何孰習二2 j揭露如上,然其並非用以 神和範圍内,當可作更動===者,在不脫離本發明之精 當視後附之申請專利範圍,因此本發明之保護範圍 J乾固所界定者為準。0702-7678TWF (N); 91P03; Jessica.ptd Page 10 546709 V. Description of the invention (8) Features and effects of the invention According to the present invention, the method of using the reflectivity of a single low polycrystalline silicon layer: The reaction chamber is decreasing. Sentence & 的 Uniformity of sedimentary material, according to the method of the present invention. A one-phase deposition method is used to process or make a polycrystalline stone a wafer-type chemical gas. Therefore, the method according to the present invention generates a reaction and reduces the reflectance. 4 The old one is short enough. Although the present invention has been better, it takes a short time. Limiting the present invention, any study 2 2 j is disclosed as above, but it is not used within the scope of God. When it can be changed ===, without departing from the scope of the present invention, the scope of patent application is attached. The scope of protection of the invention is determined by J Gangu.

M6709 圖 式簡單說明 為了讓本發明之上 明顯易懂,下文特舉—Ϊ和其他目的、特冑、和優點能更 詳細說明如下: 奴佳實施例,並配合所附圖示,作 第1圖顯示根攄習4 層表面的流程圖。 技術形成具有低反射率之複晶矽 之複Ϊ2砂圖/VI根據本發明第-實施例形成具有低反射率 灸稷日日矽層表面的流程圖。 町手 弟3圖顯示根撼太义文 1很艨本發明第二實施例形成具有低反射率 之禝晶矽層表面的流程圖。 第4 A圖〜第4D圖係根據第一實施例降低複晶矽 層之反射率的製程剖面圖。 第5 A圖第5 D圖係根據本發明第二實施例降低複晶石夕 層之反射率的製程剖面圖。 符號之說明 100、20 0〜半導體基底; 1 0 2、2 0 2〜複晶矽層; 1 0 4〜一氧化石夕薄膜; 106、204〜含氮薄膜; 2 0 6〜氮氧矽化合物層。M6709 Schematic Description In order to make the present invention obvious and easy to understand, the following special enumeration—Ϊ and other purposes, features, and advantages can be described in more detail as follows: The Nujia embodiment, with the accompanying drawings, is the first The figure shows the flow chart of the 4-layer surface of root practice. Technology to form complex sand crystals with low reflectivity complex sand 2 / VI Flow chart of forming the surface of a silicon layer with low reflectivity according to the first embodiment of the present invention. Machide 3 shows the flow of the Taiyi text. 1 is a flow chart of forming the surface of a crystalline silicon layer having a low reflectance in the second embodiment of the present invention. 4A to 4D are cross-sectional views of a process for reducing the reflectance of the polycrystalline silicon layer according to the first embodiment. FIG. 5A and FIG. 5D are cross-sectional views of a process for reducing the reflectance of the polycrystallite layer according to the second embodiment of the present invention. Explanation of symbols: 100, 200 ~ semiconductor substrate; 102, 202 ~ multicrystalline silicon layer; 104 ~ monoxide film; 106,204 ~ nitrogen-containing film; 206 ~ nitrogen silicon compound Floor.

Claims (1)

546709 9111U71 申请專利範圍546709 9111U71 Application for patent 步驟 -種降低複晶矽層之反射率的方法,至少包括下列 提供一半導體基底; $ 0!!上述半導體基底放置於單-晶圓式化學氣相沈積的 —&導入含矽氣體於上述單一晶圓式化學氣相沈積的反應 至、旨以,上述半導體基底的表面形成一複晶矽層; 、;10虱軋於上述單一晶圓式化學氣相沈積的反應室内 正亡述複晶矽層上表面的晶粒尺寸; ^入氧亂於上述單一晶圓式化學氣相沈積的反應室内 ,以f上5複晶矽層上方形成二氧化矽薄膜;以及 、士入虱氣於上述單一晶圓式化學氣相沈積的反應室内 ,以在上述二氧化矽薄膜表面形成氮化矽薄膜。 ,2 ·如申明專利範圍第1項所述之降低複晶矽層之反射 率的方法,更包括導入一氧化二氮於上述單一晶圓式化學 氣相沈積的反應室Μ,以處理上述複晶矽層表面而形成氮 氧石夕化合物薄膜的步驟。 3 ·如申請專利範圍第1項所述之降低複晶矽層之反射 率的方法,其中上述複晶矽層的厚度介於50〇埃至2 5 0 0埃 之間。 4 ·如申請專利範圍第1項所述之降低複晶矽層之反射 率的方法,其中上述複晶矽層的沈積溫度大約介於3 5 0 °c 至6 8 0 °C之間。 5 ·如申請專利範圍第1項所述之降低複晶石夕層之反射Step-A method for reducing the reflectivity of a polycrystalline silicon layer, including at least the following providing a semiconductor substrate; $ 0 !! The above semiconductor substrate is placed in a single-wafer type chemical vapor deposition-& introducing a silicon-containing gas to the above The reaction of the single-wafer chemical vapor deposition is to aim at forming a polycrystalline silicon layer on the surface of the semiconductor substrate; 10; the compound is being killed in the reaction chamber of the single-wafer chemical vapor deposition; The size of the crystal grains on the upper surface of the silicon layer; ^ oxygen is introduced into the single-wafer chemical vapor deposition reaction chamber, and a silicon dioxide film is formed over the 5 polycrystalline silicon layer on f; and A single-wafer chemical vapor deposition reaction chamber to form a silicon nitride film on the surface of the silicon dioxide film. 2. The method for reducing the reflectance of the polycrystalline silicon layer as described in item 1 of the stated patent scope, further comprising introducing nitrous oxide into the reaction chamber M of the single-wafer chemical vapor deposition to deal with the above-mentioned A step of crystallizing the surface of the silicon layer to form a thin film of oxynitride compound. 3. The method for reducing the reflectance of the polycrystalline silicon layer according to item 1 of the scope of the patent application, wherein the thickness of the polycrystalline silicon layer is between 50 Angstroms and 2500 Angstroms. 4. The method for reducing the reflectance of the polycrystalline silicon layer as described in item 1 of the scope of the patent application, wherein the deposition temperature of the polycrystalline silicon layer is between about 350 ° C and 680 ° C. 5 · Reduce the reflection of the polycrystalline stone layer as described in item 1 of the scope of patent application 第13黃 546709 案號 9111U71 曰 修正 六、申請專利範圍 率的方法,其中上述複晶石夕層的沈積壓力大約介於 150mtorr 至400mtorr 之間 。 6 ·如申請專利範圍第1項所述之降低複晶石夕層之反射 率的方法,其中上述含矽氣體係甲矽烷。 7 · —種降低複晶矽層之反射率的方法,至少包括下列 步驟: 提供一半導體基底; 將上述半導體基底放置於早一 sa圓式化學氣相沈積的 反應器; 導入含矽氣體於上述單一晶圓式化學氣相沈積的反應 室内,以在上述半導體基底的表面形成一複晶矽層;以及 導入氨氣以及一氧化二氮於上述單一晶圓式化學氣相 沈積的反應室内,以在上述複晶石夕層上方形成氮氧石夕化合 物薄膜。 8 ·如申請專利範圍第7項所述之降低複晶矽層之反射 率的方法,其中上述複晶石夕層的厚度介於5 0 0埃至2 5 0 〇埃 之間。 鲁 9 ·如申請專利範圍第7項所述之降低複晶石夕層之反射 率的方法,其中上述複晶石夕層的沈積溫度大約介於3 5 0 °c 至6 8 0 °C之間。 I 0 ·如申請專利範圍第7項所述之降低複晶矽層之反射 率的方法,其中上述複晶;5夕層的沈積壓力大約介於 150mtorr 至400mtorr 之間 。 II ·如申請專利範圍第7項所述之降低複晶矽層之反射13th Yellow 546709 Case No. 9111U71 Amendment 6. Method for applying patent coverage rate, in which the deposition pressure of the polycrystalline stone layer above is approximately 150mtorr to 400mtorr. 6. The method for reducing the reflectance of a polycrystalline spar layer as described in item 1 of the scope of the patent application, wherein the above-mentioned silicon-containing system silane. 7. A method for reducing the reflectance of a polycrystalline silicon layer, including at least the following steps: providing a semiconductor substrate; placing the semiconductor substrate in an earlier SA-type chemical vapor deposition reactor; introducing a silicon-containing gas to the above A single-wafer chemical vapor deposition reaction chamber to form a polycrystalline silicon layer on the surface of the semiconductor substrate; and introducing ammonia and nitrous oxide into the single-wafer chemical vapor deposition reaction chamber to An oxynitride compound film is formed over the polycrystallite layer. 8. The method for reducing the reflectance of the polycrystalline silicon layer as described in item 7 of the scope of the patent application, wherein the thickness of the polycrystalline silicon layer is between 500 angstroms and 2500 angstroms. Lu 9 · The method for reducing the reflectance of a polycrystalline stone layer as described in item 7 of the scope of patent application, wherein the deposition temperature of the polycrystalline stone layer is between about 3 50 ° C and 6 8 0 ° C. between. I 0 · The method for reducing the reflectance of a polycrystalline silicon layer as described in item 7 of the scope of the patent application, wherein the above polycrystalline; the deposition pressure of the layer is between 150mtorr and 400mtorr. II · Reduce the reflection of the polycrystalline silicon layer as described in item 7 of the scope of patent application 0702-7678TWFl(N) ; 91P03 ; Jessica.ptc 第14頁 546709 案號91111471 年 月 日 修正 六、申請專利範圍 率的方法,其中上述矽烷係曱矽烷。 __ 第15頁 0702-7678TWFl(N) ; 91P03 ; Jessica.ptc0702-7678TWFl (N); 91P03; Jessica.ptc Page 14 546709 Case No. 91111471 Amendment 6. Method for applying for a patent coverage rate, in which the above-mentioned silanes are silanes. __ Page 15 0702-7678TWFl (N); 91P03; Jessica.ptc
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