Classifications

• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
  • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
  • C23C14/0605—Carbon
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
  • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
  • C23C14/14—Metallic material, boron or silicon
  • C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
  • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
  • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
  • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
  • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
  • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
  • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
  • H01L2221/1068—Formation and after-treatment of conductors
  • H01L2221/1094—Conducting structures comprising nanotubes or nanowires

Definitions

• the present invention is directed to a method for forming palladium silicide nanowires.
• a number of methods for forming metal silicides including palladium silicide, which depends on their potential subsequent application, are known in the available literature.
• a palladium film is sputtered onto the surface of a substrate in the form of a silicon plate (Si) of different crystallographic orientation, e.g. (100), (11 1), or on amorphous a-Si.
• the growth takes place under ultra-vacuum conditions or in the presence of an inert gas, e.g. helium.
• Palladium silicides can also be formed on silicon carbide (SiC) substrate where Pd was deposited on Si-rich surface.
• Pd- Si islands containing palladium silicide are formed on the Si surface.
• the islands are surrounded by areas containing mostly amorphous carbon.
• Pd silicides can also be grown on Si (111) plates.
• a Pd film is deposited on a substrate of silicon of specific orientation by electron beam sputtering of palladium, evaporation of palladium, simultaneous sputtering or simultaneous evaporation of palladium and silicon.
• the morphology and shape of islands vary depending on the substrate orientation, process temperature and other conditions of the growth process. Most of the technologies described in the literature are directed to a synthesis of palladium silicide (Pd 2 S) in the form of layers or islands. It is also possible to find information relating to the methods for forming nanowires from palladium silicide (Pd 2 S). On account of the high ratio of area to volume, this type of nanowires is used as sensitive measuring elements in electronic devices.
• Tanaka, K. Ueda, A. Kumar, N. Ramgir describes a method for froming self-aligning Pd 2 Si nanowires on the Si surface using Microwave Plasma Enhanced Chemical Vapour Deposition (MPECVD) in an atmosphere of hydrogen.
• the first stage of the synthesis involves the electroplating of palladium nanoparticles on silicon (Si) substrate with a mixture of sulphuric acid (H 2 S) and PdS0 4 solution used as an electrolyte.
• a cleaned Si plate is immersed in the solution and connected to 0.1 V.
• the duration of the deposition process varies according to the size of Pd grains to be obtained.
• the plate is dried and inserted into the MPECVD chamber.
• Plasma discharge is generated with 2.45 GHz and 500 W microwaves and a voltage of 200 V applied to the electrode on which the Si plate is placed.
• the temperature of the substrate is 550 °C and the flow rate of pure H 2 in the MPECVD chamber does not exceed 80 seem.
• Hydrogen is used as a catalyst which promotes the growth of vertically aligned Pd 2 S nanowires. Pd grains are observed at the ends of nanowires.
• the American patent description US 6534402 B l presents a method for making Metal Oxide Semiconductor (MOS) transistors, and specifically for forming self- aligning metal silicides in the area of the gate and in the area of the source/drain.
• MOS Metal Oxide Semiconductor
• the essential component of the MOS transistor is a semiconductor with two electrodes: a source which is equivalent to the emitter of an electric carrier and a drain which is equivalent to the collector of an electric carrier. Electric current flows through a channel which is created between them. Along the channel, there is a third electrode refered to as a gate.
• metal ions are implanted into the Si substrate in the area of the gate and in the area of the source/drain.
• Si When the Si surface is bombarded with metal ions in the area of the gate and the source/drain, Si is transformed into an amorphous structure. Then the process of Rapid Thermal Annealing (RTA) is applied at a temperature of 450-600 °C to stimulate a reaction between the metal and the Si substrate in the area of the gate and in the area of the source/drain. As a result a highly resistant metal silicide film is formed.
• RTA process at a temperature of 600-850 °C transforms the highly resistant metal silicide film into a low- resistance film.
• the metal ions implanted into the Si substrate are derived from titanium, nickel, palladium and platinum.
• the American patent description US 6376342 B l presents a similar method for making of metal silicides but only in the area of the source/drain in Metal Oxide Semiconductor (MOS) field effect transistors.
• the substrates are made of (100) Si, but in the area of the source/drain they are initially strongly doped.
• This method is also based on the RTA process to obtain metal silicides in the area of the source/drain.
• the conditions of the RTA process are relative to the metal applied.
• the metals used include Ni, Co, Pt, Pd, Ti and Ta.
• US 2007/0221993 presents a method for obtaining an integrated circuit using the Complementary Metal Oxide Semiconductor (CMOS) technology by transforming part of the surface of the source, the gate and the drain into a metal silicide.
• the metals used include Ti, Pt, Pd, Co and Ni.
• the Si plate Prior to the deposition process, the Si plate is partially masked with Si0 2 to isolate the source from the gate and the drain. Metal silicide contacts are only formed on the Si plate, and not on Si0 2 or silicon nitride. Then the selected metal is deposited on the available sites on the Si plate. After the Si plate is heated to the temperature at which the silicon-metal reaction takes place, silicides of the specific metal are formed. Unreacted metal is removed by selective etching or chemical leaching. Metal silicides, which remain on the plate, form electric contacts between the active sites and the gate.
• CMOS Complementary Metal Oxide Semiconductor
• the Japanese patent description no. JP 57076832 concerning the formation of a palladium silicide film with good repeatability presents a substrate in the form of a Si plate covered with a insulating foil of silicon dioxide (Si0 2 ) provided with openings.
• a Pd film with a thickness of 70 nm is vaporized on the plate.
• the Pd film covers both Si0 2 sites as well as the available Si sites.
• palladium is removed from the Si0 2 sites, and the plate is held for 10 minutes at a temperature of 450 °C in an atmosphere of nitrogen which results in palladium reacting with the Si plate.
• a Pd 2 S film with a thickness of 140 nm is formed.
• the Korean patent description no. KR 10088353 presents a method for obtaining a cathode containing metal silicide nanowires.
• a cathode modified in this manner enables greater efficiency of field emission at a lower supply voltage.
• the metals used include Ni, Fe, Co, Pt, Mo, W, Y, Au and Pd.
• the surface of the substrate is deposited with a silicon film, and then a film of metallic catalyst in an appropriate manner. Me x Si y nanowires are formed as a result of the reaction between the specific metal and silicon.
• US 4687537 A presents a method for epitaxial formation of metal silicides on the Si substrate, and the invention is specifically directed to ultra-films of metal silicides applied in IR detectors - Schottky barrier photodiodes used in IR CCD devices.
• Schottky barrier detectors contain a metal film (e.g. palladium or platinum) of silicide on a Si (100) or (111) substrate. The thinner the metal silicide film, the sensitivity greater of such detector to IR radiation. Thus far the problem related to the growth of a thin, uniform and reproducible metal silicide film remains unsolved.
• Me x Si y films are non-uniform in terms of their thickness or they do not cover the entire substrate surface.
• a Si plate doped with boron (B) of resistance at 10-50 ⁇ /cm is used.
• the Si plate Prior to the formation of a metal silicide film, the Si plate is subject to chemical cleaning to remove any native oxides.
• a thin sub-layer of the first metal - preferably Ti - is deposited on the Si plate.
• This metal forms metal oxide on the surface of the Si plate by scavenging native Si oxides, thus cleaning the substrate surface and providing the basis for a more uniform distribution of the subsequently deposited metal, i.e. platinum or palladium.
• the first Ti sub-layer is deposited by electron beam evaporation in conventional vacuum chambers.
• the deposition process takes places under the pressure of 10 "6 -10 "7 mTorr and at a temperature of 200-350 °C.
• the process in such low temperature is conducive to the greater uniformity and alignment of the Me x Si y film compared to metal silicide films obtained at high temperatures of e.g. 600- 700 °C.
• the American patent description no. US 5624867 A presents a low-temperature method for forming integrated circuit surface contacts on printed circuit boards based on the technology of ion implantation at the metal/metal silicide interface.
• the density of integrated circuits is greater as a result of the process taking place in low temperature.
• the application of palladium silicide contributes to the better quality of integrated circuit contacts.
• ions are not implanted at the surface of the Si plate, but only inside the palladium or palladium silicide film deposited on the Si surface. Thus the Si substrate is protected against damage.
• the invention described in the patent is based on an n-type Si plate.
• the process of local oxidation of silicon (LOCOS) was used to define the active area.
• native oxides are removed from the active area using wet chemical methods based on a solution of hydrofluoric acid (HF). Then a Pd film with a thickness of 50 nm is deposited on the active area. The Pd film is overlaid with a Si film using the chemical vapour deposition (CVD) method.
• the subsequent stage consists in implanting BF 2 ions into the Pd film. The resulting product is held for 30 minutes at a temperature of 300 °C in an atmosphere of nitrogen to grow a palladium silicide film - this is the first annealing stage.
• a uniform Pd silicide film is formed as a result of reaction between Pd and the Si substrate.
• Palladium silicide is also formed over the LOCOS active area, but as a result of reaction between Pd and the Si film deposited during the CVD process.
• the subsequent annealing stage takes place in an atmosphere of nitrogen, but for 60 minutes and at a higher temperature of 500-800 °C.
• a low-resistance palladium silicide film is formed during the second stage.
• the essential feature of the invention is that it employs a double-stage method for forming palladium silicide nanowires based on the technology of physical vapour deposition (PVD) and chemical vapour deposition (CVD).
• the 1 st stage of this method consists in depositing on a p- or n-type Si substrate - in the process of physical vapour deposition of fullerene (C 6 o) and palladium acetate (PdC 4 3 ⁇ 40 4 ) - precursors of the initial film, a thin composite carbon-palladium film from two separate sources.
• the process takes place under dynamic vacuum of 10 "5 Torr.
• the resulting film contains evenly distributed Pd grains of 4-10 nm in the carbon matrix.
• the film deposited on the Si substrate during the PVD process is modified in the quartz tube furnace for 30 minutes at a temperature of 650 °C by way of chemical vapour deposition in the presence of xylene as an additional source of carbon.
• the additional carbon is to prevent the formation of excessive palladium silicide areas on the Si substrate as a result of reaction between Pd grains and the substrate caused by the temperature of the CVD process.
• the process takes place under atmospheric pressure and in the flow of argon as a carrier gas for xylene vapours.
• Xylene is supplied to the reaction zone over the surface of the Si substrate with a PVD film at an appropriate feed rate.
• Pd nanograins in the PVD film obtained in the 1 st stage agglomerate and form islands surrounded by the carbon matrix on the surface of the Si substrate.
• Palladium silicide nanowires of different diameter and length grow out of the Pd-Si islands.
• Palladium silicide nanowires are isolated from the carbon matrix by annealing the matrix in the air.
• Palladium silicide nanowires according to the invention are applied for example for the preparation of ohmic contacts to reduce the resistance of metallic contacts in MOS transistors installed on printed circuit boards, MOSEF field-effect transistors in which the source-drain contact is defined as an area containing palladium silicide nanowires, or as electron microscope probes to test solid samples or biological material.
• the method for forming palladium silicide nanowires comprises two stages. In the 1 st stage, in the PVD process, a composite carbon-palladium film is deposited on the Si substrate at a distance of 54 mm from the sources of fullerene (C 6 o) and palladium acetate. The PVD process lasts 10 minutes. 2.1 A current flows through the source of fullerene (C 6 o), and 1.2 A current through the source of palladium acetate. The film formed on the Si substrate contains palladium nanograins of 4 to 10 nm in the amorphous and fullerenic carbon matrix.
• the initial film formed during the PVD process is modified in the course of the CVD process by applying the temperature of 650°C and xylene as modifying factors.
• the process lasts 30 minutes in the flow of argon as a carrier gas for xylene vapours.
• the drop-feed rate of xylene is 0.1 mL/min and the flow rate of argon is 40 L/h.
• the resulting system is annealed for 60 minutes in the flow of argon.

Landscapes

• Chemical & Material Sciences (AREA)
• Engineering & Computer Science (AREA)
• Metallurgy (AREA)
• Chemical Kinetics & Catalysis (AREA)
• Organic Chemistry (AREA)
• Mechanical Engineering (AREA)
• Materials Engineering (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Power Engineering (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Electrodes Of Semiconductors (AREA)
• Silicon Compounds (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=47143248

Family Applications (1)

Country Status (2)

Cited By (2)

Citations (9)

• 2011
  • 2011-09-26 PL PL396428A patent/PL219413B1/pl unknown
• 2012
  • 2012-09-23 WO PCT/PL2012/050031 patent/WO2013048270A1/en active Application Filing

Patent Citations (9)

Non-Patent Citations (3)

Also Published As

Similar Documents

Legal Events