JPS5776832A - Method for forming palladium silicide - Google Patents

Method for forming palladium silicide

Info

Publication number
JPS5776832A
JPS5776832A JP15225280A JP15225280A JPS5776832A JP S5776832 A JPS5776832 A JP S5776832A JP 15225280 A JP15225280 A JP 15225280A JP 15225280 A JP15225280 A JP 15225280A JP S5776832 A JPS5776832 A JP S5776832A
Authority
JP
Japan
Prior art keywords
palladium
palladium layer
silicon
oxide film
silicon oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15225280A
Other languages
Japanese (ja)
Inventor
Shigeru Osawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15225280A priority Critical patent/JPS5776832A/en
Publication of JPS5776832A publication Critical patent/JPS5776832A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Silicon Compounds (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To form palladium silicide with good reproducibility, by forming a palladium layer on the surface of an insulating film having an opening on a silicon substrate, removing the palladium layer on said insulating film, and heat-treating the palladium layer on the exposed surface of the substrate. CONSTITUTION:A silicon oxide film 22 at a part of which the opening is provided is deposited on the silicon substrate 21. The palladium layer 23 with the thickness of about 700Angstrom is formed on the surface thereon by evaporation. Then the palladium layer 23 on the silicon oxide film 22 is removed. Thereafter the heat treatment is performed at 450 deg.C in an nitride atmosphere for about 10 min, and silicon 21 and the palladium layer 23 are reacted. As a result palladium silicide 24 is formed to the thickness of about 1,400Angstrom . Then, aluminum metal layer 25 which is to become an electrode is formed by evaporation. Unnecessary parts are removed, and the intended semiconductor device is obtained. Since the palladium layer 23 has good adhesion with silicon 21 but poor adhesion with the silicon oxide film 22, palladium silicide never remains on the silicon oxide film 22.
JP15225280A 1980-10-31 1980-10-31 Method for forming palladium silicide Pending JPS5776832A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15225280A JPS5776832A (en) 1980-10-31 1980-10-31 Method for forming palladium silicide

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15225280A JPS5776832A (en) 1980-10-31 1980-10-31 Method for forming palladium silicide

Publications (1)

Publication Number Publication Date
JPS5776832A true JPS5776832A (en) 1982-05-14

Family

ID=15536413

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15225280A Pending JPS5776832A (en) 1980-10-31 1980-10-31 Method for forming palladium silicide

Country Status (1)

Country Link
JP (1) JPS5776832A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006339578A (en) * 2005-06-06 2006-12-14 Renesas Technology Corp Semiconductor device and its manufacturing method
WO2013048270A1 (en) 2011-09-26 2013-04-04 Instytut Tele- I Radiotechniczny Method for forming palladium silicide nanowires

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006339578A (en) * 2005-06-06 2006-12-14 Renesas Technology Corp Semiconductor device and its manufacturing method
WO2013048270A1 (en) 2011-09-26 2013-04-04 Instytut Tele- I Radiotechniczny Method for forming palladium silicide nanowires

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