WO2013030865A1 - 薄膜トランジスタアレイの製造方法、薄膜トランジスタアレイおよび表示装置 - Google Patents
薄膜トランジスタアレイの製造方法、薄膜トランジスタアレイおよび表示装置 Download PDFInfo
- Publication number
- WO2013030865A1 WO2013030865A1 PCT/JP2011/004769 JP2011004769W WO2013030865A1 WO 2013030865 A1 WO2013030865 A1 WO 2013030865A1 JP 2011004769 W JP2011004769 W JP 2011004769W WO 2013030865 A1 WO2013030865 A1 WO 2013030865A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- film thickness
- silicon layer
- thin film
- insulating layer
- gate insulating
- Prior art date
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 227
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 64
- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000010408 film Substances 0.000 claims abstract description 378
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 238
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 96
- 230000031700 light absorption Effects 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims description 78
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 50
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 48
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 41
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 41
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 38
- 230000014509 gene expression Effects 0.000 claims description 33
- 239000012788 optical film Substances 0.000 claims description 9
- 239000004973 liquid crystal related substance Substances 0.000 claims description 8
- 238000001069 Raman spectroscopy Methods 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 6
- 230000008033 biological extinction Effects 0.000 claims description 5
- 230000002596 correlated effect Effects 0.000 claims description 4
- 238000001228 spectrum Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 562
- 238000010521 absorption reaction Methods 0.000 description 40
- 238000010586 diagram Methods 0.000 description 39
- 238000005224 laser annealing Methods 0.000 description 30
- 230000000875 corresponding effect Effects 0.000 description 28
- 238000002425 crystallisation Methods 0.000 description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 18
- 239000010703 silicon Substances 0.000 description 18
- 230000000694 effects Effects 0.000 description 16
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- 238000009826 distribution Methods 0.000 description 14
- 230000005540 biological transmission Effects 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 239000011651 chromium Substances 0.000 description 7
- 230000008025 crystallization Effects 0.000 description 7
- 229910001182 Mo alloy Inorganic materials 0.000 description 6
- 230000007423 decrease Effects 0.000 description 6
- 230000020169 heat generation Effects 0.000 description 6
- 230000003287 optical effect Effects 0.000 description 6
- 230000010355 oscillation Effects 0.000 description 6
- 239000002356 single layer Substances 0.000 description 6
- 238000002834 transmittance Methods 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 238000004364 calculation method Methods 0.000 description 5
- 239000000470 constituent Substances 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 5
- 229910052804 chromium Inorganic materials 0.000 description 4
- 230000001678 irradiating effect Effects 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000009795 derivation Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 230000010287 polarization Effects 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910001080 W alloy Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000006356 dehydrogenation reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000005499 laser crystallization Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000013081 microcrystal Substances 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- XULSCZPZVQIMFM-IPZQJPLYSA-N odevixibat Chemical compound C12=CC(SC)=C(OCC(=O)N[C@@H](C(=O)N[C@@H](CC)C(O)=O)C=3C=CC(O)=CC=3)C=C2S(=O)(=O)NC(CCCC)(CCCC)CN1C1=CC=CC=C1 XULSCZPZVQIMFM-IPZQJPLYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- -1 that is Inorganic materials 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
Definitions
- the present invention relates to a method for manufacturing a thin film transistor array, a thin film transistor array, and a display device.
- each thin film transistor constituting the thin film transistor array is formed of a-Si that is amorphous silicon or Poly-Si that is crystalline and polycrystalline silicon.
- a-Si layer amorphous silicon layer
- laser light such as excimer is applied to the amorphous silicon layer. It is formed by irradiating and instantaneously raising the temperature to crystallize.
- the thin film transistor has a bottom gate structure in which the gate metal is disposed on the substrate side as viewed from x-Si (x is a or poly) of the channel portion, and the gate metal and the source / drain metal are in the channel portion.
- the bottom gate structure is mainly used in an a-Si TFT having a channel portion formed of an amorphous silicon layer, and the top gate structure is a Poly-Si having a channel portion formed of a crystalline silicon layer. Mainly used in TFT.
- a bottom gate structure is generally used as a structure of a thin film transistor included in a liquid crystal panel or an organic EL panel used in a large-area display device.
- a Poly-Si TFT is used in a bottom gate structure, and in this case, the manufacturing cost can be suppressed.
- a crystalline silicon layer is formed by crystallizing an amorphous silicon layer by irradiating a laser.
- laser annealing crystallization method the amorphous silicon layer is crystallized by heat based on laser light irradiation.
- each thin film transistor constituting a thin film transistor array used in an organic EL panel is required to have particularly uniform characteristics.
- a technique for forming a crystalline silicon layer having uniform crystallinity on the entire surface of the substrate has been developed.
- a disadvantage occurs in the case of manufacturing a bottom gate thin film transistor by the laser annealing crystallization method using the developed formation technique. The reason will be described below.
- the amorphous silicon layer and the gate in a region where the gate electrode is generally present are formed.
- the light absorption rate with respect to the laser beam used for laser annealing differs from the amorphous silicon layer in the region where no electrode exists (referred to as “second region”). This is because the effect of multiple interference of laser light in a multilayer thin film composed of an amorphous silicon layer and a gate insulating layer changes depending on the presence or absence of a gate electrode.
- Patent Document 1 discloses a technique for solving this problem.
- the thicknesses of the gate insulating layer and the amorphous silicon layer are adjusted so that the light absorption rate of the amorphous silicon layer in the first region is equal to the light absorption rate of the amorphous silicon layer in the second region.
- a technique for forming such a film thickness structure is disclosed. Thereby, the non-uniformity of the heat generation temperature of the amorphous silicon layer between both regions immediately after laser irradiation is reduced as much as possible, and a crystalline silicon thin film having uniform crystallinity is formed on the entire surface of the substrate.
- Patent Document 1 has a problem that a crystalline silicon thin film having uniform crystallinity cannot be formed on the entire surface of the substrate in the following cases. The reason will be described below.
- an amorphous silicon layer and a gate insulating layer are formed by a process such as plasma-enhanced chemical vapor deposition (PECVD).
- PECVD plasma-enhanced chemical vapor deposition
- the thin film formed by such a process has a certain degree of film thickness variation within the substrate surface, although it depends on the film forming conditions.
- the variation in film thickness depends on the wavelength of the laser beam used for laser annealing. It is inevitable that variations in the light absorptance occur corresponding to the amount of film thickness deviation from the film thickness.
- the amorphous silicon layer and the gate insulating layer are formed aiming at a film thickness that makes the light absorption rate of the amorphous silicon layer equal in the first region and the second region, the film is not formed in the substrate plane. Thickness variation occurs. As a result, the light absorption rate of the amorphous silicon layer in the first region and the second region cannot be made equal over the entire surface of the substrate.
- the first region and the second region are amorphous over the entire surface of the substrate in the laser annealing step.
- the heat generation temperature of the crystalline silicon layer cannot be made uniform, and the crystallinity of the obtained crystalline silicon layer becomes nonuniform within the substrate surface.
- Patent Document 2 first crystallinity of a crystalline silicon layer formed on a first region is reduced with respect to film thickness variations of an amorphous silicon layer and a gate insulating layer so that the entire substrate has uniform crystallinity.
- a film thickness condition that minimizes the variation in the light absorption rate of the amorphous silicon layer on the region is adopted.
- the heat generation in laser annealing of the amorphous silicon layer on the first region and the film thickness variation of the amorphous silicon layer with respect to the crystallinity of the obtained crystalline silicon layer is adopted.
- the influence of the film thickness variation of the gate insulating layer can be minimized.
- the on-characteristic of the thin film transistor depends not only on the crystallinity of the crystalline silicon layer serving as the channel of the thin film transistor but also on the gate capacitance of the gate insulating layer. That is, fluctuations in the film thickness of the gate insulating layer in the substrate surface cause variations in the gate capacitance of the gate insulating layer, so that even if the crystalline silicon layer serving as a channel has a uniform crystallinity in each thin film transistor, When the gate capacitance fluctuates, the on characteristics of each thin film transistor vary.
- FIG. 1 is a diagram showing an example of the on-plane distribution of the on-current of each thin film transistor in the thin film transistor array.
- the thin film transistor array shown in FIG. 1 is constituted by a bottom gate TFT using a crystalline silicon layer formed by a laser annealing crystallization method, and the substrate surface (in the drawing) of the thin film transistor array has 224 ⁇ 224.
- the thin film transistor is used.
- the distribution of the on-current in the substrate surface is visualized by expressing the magnitude of the on-current of each thin film transistor in the thin film transistor array in shades.
- the unit of the on-current is standardized and shown in an arbitrary unit.
- FIG. 1 shows that the on-current of the thin film transistor is non-uniform in the substrate surface and has uneven characteristics.
- the unevenness of the ON characteristics is caused by the fact that the thickness of the gate insulating layer varies depending on the position in the substrate surface of the thin film transistor array, and the capacitance of the gate insulating layer on the gate electrode changes accordingly. Yes.
- the film thickness variation of the channel constituent layer of the thin film transistor becomes more difficult to control as the substrate used for panel fabrication becomes larger. Therefore, with an increase in the size of the display device, variation in gate insulating capacitance of each thin film transistor in the thin film transistor array used in the display device increases. Even if a crystalline silicon layer with uniform crystallinity can be formed over the entire surface of the substrate, the variation in on-state characteristics of the thin film transistor due to the variation in gate capacitance becomes more conspicuous as the display device becomes larger. That is, when a display device having a larger area is manufactured, unevenness in image quality due to variation in on-state characteristics of thin film transistors becomes a more serious problem.
- the present invention has been made in view of the above problems, and an object thereof is to provide a method of manufacturing a thin film transistor array, a thin film transistor array, and a display device using the thin film transistor array, which can be configured with thin film transistors having uniform on characteristics.
- a thin film transistor array manufacturing method includes a first step of preparing a substrate, a second step of forming a plurality of gate electrodes on the substrate, and the plurality of the plurality of gate electrodes.
- the film thickness of the gate insulating layer on the plurality of gate electrodes is determined by changing the light absorption rate of the amorphous silicon layer on the gate electrode with respect to the laser light and the gate insulation layer.
- the thickness of the amorphous silicon layer on the plurality of gate electrodes is changed to the amorphous thickness in a region having a positive correlation with the equivalent oxide thickness of the layer.
- the variation in the light absorptance with respect to the film thickness change of the qualitative silicon layer is formed in a film thickness range in a region where the fluctuation is within a predetermined range from the first reference.
- the present invention it is possible to realize a thin film transistor array manufacturing method, a thin film transistor array, and a display device using the thin film transistor array that can be configured with thin film transistors having uniform on characteristics.
- an amorphous silicon layer on the gate electrode region corresponding to each thin film transistor constituting the array on the substrate and a gate insulating layer are formed so that each film thickness satisfies a predetermined condition.
- a laser with a wavelength in the visible light region a crystal whose crystallinity has fluctuated so as to offset the influence of the increase or decrease of the gate capacitance corresponding to the increase or decrease of the gate capacitance of the gate insulating layer on the first region
- a thin film transistor array manufacturing method, a thin film transistor array, and a display device using the thin film transistor array can be realized in which a thin silicon layer is formed and the thin film transistor array formed on the entire surface of the substrate has uniform thin film transistor ON characteristics.
- FIG. 1 is a diagram illustrating an example of an in-plane distribution of on-current of each thin film transistor in a thin film transistor array.
- FIG. 2 is a cross-sectional view showing the structure of the thin film transistor constituting the thin film transistor array according to the embodiment of the present invention.
- FIG. 3 is a diagram showing an equivalent circuit of a unit cell of the thin film transistor array according to the embodiment of the present invention.
- FIG. 4 is a flowchart showing a manufacturing process of a thin film transistor constituting the thin film transistor array according to the embodiment of the present invention.
- FIG. 5A is a cross-sectional view for explaining a method of manufacturing a thin film transistor constituting the thin film transistor array according to the embodiment of the present invention.
- FIG. 5A is a cross-sectional view for explaining a method of manufacturing a thin film transistor constituting the thin film transistor array according to the embodiment of the present invention.
- FIG. 5B is a cross-sectional view for explaining the method of manufacturing the thin film transistor constituting the thin film transistor array according to the embodiment of the present invention.
- FIG. 5C is a cross-sectional view for explaining the method of manufacturing the thin film transistor constituting the thin film transistor array according to the embodiment of the present invention.
- FIG. 5D is a cross-sectional view for explaining the method for manufacturing the thin film transistor constituting the thin film transistor array according to the embodiment of the present invention.
- FIG. 5E is a cross-sectional view for explaining the method for manufacturing the thin film transistor constituting the thin film transistor array according to the embodiment of the present invention.
- FIG. 5F is a cross-sectional view for explaining the method of manufacturing the thin film transistor that constitutes the thin film transistor array according to the embodiment of the present invention.
- FIG. 5G is a cross-sectional view for explaining the method of manufacturing the thin film transistor constituting the thin film transistor array according to the embodiment of the present invention.
- FIG. 5H is a cross-sectional view for explaining the method for manufacturing the thin film transistor constituting the thin film transistor array according to the embodiment of the present invention.
- FIG. 5I is a cross-sectional view for explaining the method of manufacturing the thin film transistor constituting the thin film transistor array according to the embodiment of the present invention.
- FIG. 5J is a cross-sectional view for explaining the method of manufacturing the thin film transistor constituting the thin film transistor array according to the embodiment of the present invention.
- FIG. 6 is a diagram schematically showing laser annealing in S14 of FIG. FIG.
- FIG. 7 is a diagram showing an example of a cross section of an equivalent circuit of a unit repeating cell of the thin film transistor array according to the embodiment of the present invention.
- FIG. 8 is a diagram for explaining the amplitude transmittance and the calculation method of the amplitude transmittance.
- FIG. 9 is a diagram for explaining that there is a film thickness range suitable for the film thickness of the amorphous silicon layer when the crystalline silicon layer is formed by the laser annealing crystallization method.
- FIG. 10A is a diagram showing that there is a preferable film thickness range for the insulating film constituting the gate insulating layer when the crystalline silicon layer is formed by the laser annealing crystallization method.
- FIG. 10B is a diagram for illustrating that there is a preferable thickness range for the thickness of the insulating film constituting the gate insulating layer when the crystalline silicon layer is formed by the laser annealing crystallization method.
- FIG. 11 is a diagram showing a specific example of a film thickness range suitable for the film thickness of the insulating film constituting the gate insulating layer when the crystalline silicon layer is formed by the laser annealing crystallization method.
- FIG. 12A is a diagram showing the relationship between the capacitance formed by the varying thickness of the gate insulating layer and the absorption rate of the amorphous silicon layer when the gate insulating layer is configured under condition 1.
- FIG. 12B is a diagram showing the relationship between the capacitance formed by the varying gate insulating film thickness and the absorption rate of the amorphous silicon layer when the gate insulating layer is configured under condition 2.
- FIG. 12C is a diagram showing the relationship between the capacitance formed by the varying thickness of the gate insulating layer and the absorption rate of the amorphous silicon layer when the gate insulating layer is configured under Condition 3.
- FIG. 13A is a diagram showing the relationship between the capacitance formed by the varying film thickness and the crystallinity of the amorphous silicon layer when the gate insulating layer is configured under Condition 1.
- FIG. 13B is a diagram showing the relationship between the capacitance formed by the varying film thickness and the crystallinity of the amorphous silicon layer when the gate insulating layer is configured under condition 2.
- FIG. 13C is a diagram showing the relationship between the capacitance formed by the varying film thickness and the crystallinity of the amorphous silicon layer when the gate insulating layer is configured under condition 3.
- FIG. 14A is a diagram showing the relationship between the capacitance formed by the varying film thickness and the on-state current of the thin film transistor using the crystalline silicon layer as a channel when the gate insulating layer is configured under condition 1.
- FIG. 14B is a diagram showing the relationship between the capacitance formed by the varying film thickness and the on-state current of the thin film transistor using the crystalline silicon layer as a channel when the gate insulating layer is configured under condition 2.
- FIG. 14C is a diagram showing the relationship between the capacitance formed by the varying film thickness and the on-state current of the thin film transistor using the crystalline silicon layer as a channel when the gate insulating layer is configured under Condition 3.
- FIG. 15 is a diagram showing an example of a display device including the thin film transistor array of the present invention.
- the thin film transistor array manufacturing method includes a first step of preparing a substrate, a second step of forming a plurality of gate electrodes on the substrate, and forming a gate insulating layer on the plurality of gate electrodes.
- the film thickness of the gate insulating layer on the gate electrode is positively correlated with the light absorption rate of the amorphous silicon layer on the gate electrode with respect to the laser beam and the equivalent oxide thickness of the gate insulating layer.
- the film thickness of the amorphous silicon layer on the plurality of gate electrodes is changed to the light absorption rate with respect to the film thickness change of the amorphous silicon layer. Is formed in a film thickness range in a region where the fluctuation is within a predetermined range from the first reference.
- the equivalent oxide film thickness is a value obtained by converting the physical thickness of the gate insulating layer into an electrical film thickness equivalent to the SiO 2 film.
- a thin film transistor array is formed using a crystalline silicon layer in which the distribution of crystallinity is changed so as to have a certain relationship with the gate insulating layer capacitance in the substrate surface.
- the laser is constituted by a solid-state laser device.
- the laser is composed of a laser device using a semiconductor laser element.
- the fluctuation of the irradiation energy density of the laser light on the amorphous silicon layer is less than about 5%.
- the wavelength range of the laser is 400 nm or more and 600 nm or less.
- the film thickness of the amorphous silicon layer is set as a film thickness range of a region within a predetermined range from the first reference.
- the absorptance of the laser light wavelength ⁇ of the amorphous silicon layer normalized by the optical film thickness of the gate insulating layer normalized by the laser light wavelength ⁇ was normalized by the laser light wavelength ⁇ ,
- the amorphous silicon layer is formed in a film thickness range in which the differential coefficient when differentiated by the optical film thickness is ⁇ 5 or more and +5 or less.
- the amorphous silicon layer has an average film thickness of the amorphous silicon layer on the plurality of gate electrodes expressed by the following formula: It is formed so as to be included in the range represented by 1).
- Formula 1 0.426 ⁇ n a-Si ⁇ d a-Si / ⁇ Si ⁇ 0.641, where d a-Si represents the average thickness of the amorphous silicon layer, and ⁇ Si represents the laser beam.
- the wavelength represents the wavelength
- na -Si represents the refractive index of the amorphous silicon layer with respect to the laser beam having the wavelength ⁇ .
- the gate insulating layer is formed such that the extinction coefficient of the gate insulating layer with respect to the wavelength of the laser light is 0.01 or less.
- the gate insulating layer is a silicon oxide film.
- the gate insulating layer is a silicon nitride film.
- the gate insulating layer is composed of a laminated film of a silicon oxide film and a silicon nitride film.
- the gate insulating layer has an average film thickness of the gate insulating layer on the plurality of gate electrodes expressed by the following formula 2): Or a range represented by the following formula 3).
- Formula 2) 0.44 ⁇ n GI ⁇ d GI / ⁇ 0.74, Formula 3) 0.96 ⁇ n GI ⁇ d GI / ⁇ 1.20, where d GI is the average of the gate insulating layer The film thickness is represented, ⁇ represents the wavelength of the laser beam, and n GI represents the refractive index of the gate insulating layer with respect to the laser beam having the wavelength ⁇ .
- the gate insulating layer has an average film thickness of the gate insulating layer on the plurality of gate electrodes expressed by the following formula 4): Or a range represented by the following formula 5).
- Formula 4) 0.47 ⁇ n GI ⁇ d GI / ⁇ 0.62, Formula 5) 1.04 ⁇ n GI ⁇ d GI / ⁇ 1.13, where d GI is the average of the gate insulating layer The film thickness is represented, ⁇ represents the wavelength of the laser beam, and n GI represents the refractive index of the insulating layer with respect to the laser beam having the wavelength ⁇ .
- an average film thickness of the silicon oxide film on the plurality of gate electrodes and an average film thickness of the silicon nitride film on the plurality of gate electrodes are expressed by the following formula: It is formed so as to be included in the region represented by 6) and 7) or the region represented by 8) and 9).
- the gate insulating layer is formed by forming an average film thickness of the silicon oxide film on the plurality of gate electrodes and the nitriding on the plurality of gate electrodes.
- the average film thickness of the silicon film is formed so as to be included in the region represented by the following formula 10) and formula 11) or the region represented by formula 12) and formula 13).
- Equation 10 Y ⁇ -132.6X 6 + 181X 5 -93.8X 4 + 21.3X 3 -1.33X 2 -1.04X + 0.473, wherein 11) Y ⁇ 23.7X 6 -4.56X 5 -35. 4X 4 + 27.2X 3 ⁇ 5.75X 2 ⁇ 0.973X + 0.619, Formula 12) Y ⁇ 7.46X 6 ⁇ 32.4X 5 + 50.8X 4 ⁇ 35.7X 3 + 11.0X 2 ⁇ 2.20X + 1.
- the second step includes a step of forming an undercoat layer made of a transparent insulating film on the substrate and a step of forming a plurality of gate electrodes on the undercoat layer. Including.
- a thin film transistor array is formed on a substrate, a plurality of gate electrodes formed on the substrate, a gate insulating layer commonly formed on the plurality of gate electrodes, and the gate insulating layer.
- a crystalline silicon layer; and a source electrode and a drain electrode formed in a region on the crystalline silicon layer of each of the plurality of gate electrodes, and the crystalline silicon layer is formed on the gate insulating layer.
- the amorphous silicon layer is formed by crystallization using laser light emitted from a laser, and the film thickness of the gate insulating layer on the plurality of gate electrodes is set to be amorphous on the gate electrodes.
- the amorphous silicon layer on the plurality of gate electrodes is formed in a film thickness range in a region where the light absorption rate of the crystalline silicon layer with respect to the laser beam and the equivalent oxide film thickness are positively correlated. Thickness of the layer, change in the light absorption rate with respect to the thickness change of the amorphous silicon layer is formed in a thickness range of a region of the first reference within a predetermined range.
- the average crystal grain size of the crystalline silicon layer on the gate electrode has a negative correlation with the gate capacitance of the gate insulating layer on the gate electrode.
- the half width of the Raman scattering spectrum peak near 520 cm ⁇ 1 in the crystalline silicon layer on the gate electrode is equal to the gate capacitance of the gate insulating layer on the gate electrode. It has a positive correlation.
- a display device is a display device including a liquid crystal panel or an EL panel, comprising the thin film transistor array according to any one of the seventeenth to nineteenth aspects, wherein the thin film transistor array is the liquid crystal panel or the EL panel. Drive.
- FIG. 2 is a cross-sectional view showing a thin film transistor that constitutes a thin film transistor array used in the display device according to the embodiment of the present invention.
- a thin film transistor 100 illustrated in FIG. 2 is a bottom gate thin film transistor, and includes a substrate 10, an undercoat layer 11, a gate electrode 12, a gate insulating layer 13, a crystalline silicon layer 15, and an amorphous silicon layer 16. And an n + silicon layer 17 and source / drain electrodes 18.
- the substrate 10 is an insulating substrate made of, for example, transparent glass or quartz.
- the undercoat layer 11 is formed on the substrate 10 and is composed of, for example, a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, and a stacked layer thereof.
- the undercoat layer 11 is preferably made of silicon oxide (SiOx) of 1.5 ⁇ x ⁇ 2.0 and having a thickness of 300 nm to 1500 nm.
- a more preferable thickness range of the undercoat layer 11 is 500 nm or more and 1000 nm or less. This is because if the thickness of the undercoat layer 11 is increased, the thermal load on the substrate 10 can be reduced, but if it is too thick, film peeling or cracking occurs.
- the gate electrode 12 is formed on the undercoat layer 11 and is typically made of a metal such as molybdenum (Mo) or a metal such as Mo alloy (for example, MoW (molybdenum / tungsten alloy)).
- Mo molybdenum
- Mo alloy for example, MoW (molybdenum / tungsten alloy)
- the gate electrode 12 only needs to be a metal that can withstand the melting point temperature of silicon. Therefore, those containing W (tungsten), Ta (tantalum), Nb (niobium), Ni (nickel), Cr (chromium), and Mo. It may be made of an alloy of
- the film thickness of the gate electrode 12 is preferably 30 nm or more and 300 nm or less, and more preferably 50 nm or more and 100 nm or less.
- the thickness of the gate electrode 12 is small, the transmittance of the gate electrode 12 increases, and the reflection of laser light described below tends to decrease. Further, when the thickness of the gate electrode 12 is large, the coverage of the gate insulating layer 13 described below is lowered. In particular, the gate insulating film is disconnected at the end of the gate electrode, so that the gate electrode 12 and the n + silicon are separated. This is because the characteristics of the thin film transistor 100 are likely to deteriorate, for example, the layer 17 is electrically connected.
- the gate insulating layer 13 is formed so as to cover the gate electrode 12 and has, for example, a silicon oxide layer, a silicon nitride layer, or a stacked structure of a silicon oxide layer and a silicon nitride layer.
- the gate insulating layer is typically formed by a CVD apparatus. Due to the characteristics of the CVD apparatus, the distribution in the substrate surface of the film thickness of the gate insulating layer 13 corresponding to each gate electrode 12 on the substrate 10 may vary by about ⁇ 15% with respect to the target film thickness.
- an equivalent oxide thickness of the gate insulating layer 13 on each gate electrode 12 of the laser beam of the amorphous silicon layer 14 on the gate electrode 12 The film thickness is in the film thickness range having a positive correlation with the light absorption rate.
- the equivalent oxide film thickness is a value obtained by converting the physical thickness of the gate insulating layer into an electrical film thickness equivalent to the SiO 2 film.
- the gate capacitance of the gate insulating layer 13 on each gate electrode 12 is within a film thickness range in which the amorphous silicon layer 14 on the gate electrode 12 has a negative correlation with the optical absorptance with respect to laser light.
- the gate insulating layer 13 is formed with a thickness of. That is, the thickness distribution (or the center value of the film thickness distribution) of the gate insulating layer 13 has a suitable range when the crystalline silicon layer 15 is formed by the laser annealing crystallization method. The details of this preferable range will be described later, but are expressed by a certain relational expression according to the structure of the gate insulating layer 13 and the type of the constituent layers.
- the crystalline silicon layer 15 is formed on the gate insulating layer 13 and is formed of a polycrystalline silicon layer (Poly-Si layer).
- the crystalline silicon layer 15 is polycrystalline by irradiating the amorphous silicon layer 14 with a laser after an amorphous silicon layer 14 (not shown) made of a-Si is formed on the gate insulating layer 13. It is formed by crystallization (including microcrystallization).
- polycrystal has a broad meaning including not only a polycrystal in a narrow sense consisting of crystals of 50 nm or more but also a microcrystal in a narrow sense consisting of crystals of 50 nm or less.
- polycrystal is described in a broad sense.
- the laser light source used for laser irradiation is a laser having a wavelength in the visible light region.
- the laser having a wavelength in the visible light region is a laser having a wavelength of about 380 nm to 780 nm, and preferably a laser having a wavelength of 400 nm to 600 nm.
- the reason why this range is preferable is that when the wavelength of the laser light is less than 400 nm, the effect of multiple interference is reduced, and the laser light of the amorphous silicon layer with respect to the change in the film thickness of the gate insulating layer 13 is reduced. This is because there is almost no change in the absorption rate, and the effect expected in the present invention cannot be obtained.
- the wavelength of the laser light is larger than 600 nm, the absorption of the laser light with respect to the amorphous silicon layer 14 is remarkably lowered, and the crystallization efficiency is lowered in laser crystallization. It is.
- the laser having a wavelength in the visible light region may be in any of pulse oscillation, continuous oscillation, or pseudo continuous oscillation mode.
- the amorphous silicon layer 14 is made of amorphous silicon, that is, a-Si, and is formed on the gate insulating layer 13.
- the amorphous silicon layer 14 is formed with a film thickness within a film thickness range in which the optical absorptance of the amorphous silicon on the gate electrode 12 with respect to the laser beam changes little with respect to variations in the film thickness of the amorphous silicon layer 14.
- the film thickness distribution of the amorphous silicon layer 14 (the center value of the film thickness distribution) has a suitable range when the crystalline silicon layer 15 is formed by the laser annealing crystallization method. Although details of this preferable range will be described later, it is expressed by a certain relational expression according to the refractive index of the amorphous silicon layer 14 and the wavelength of the laser beam used for laser crystallization.
- the amorphous silicon layer 16 is formed on the crystalline silicon layer 15.
- the thin film transistor 100 has a channel layer having a structure in which the amorphous silicon layer 16 is stacked on the crystalline silicon layer 15.
- n + silicon layer 17 is formed so as to cover the side surfaces of the amorphous silicon layer 16 and the crystalline silicon layer 15 and the gate insulating layer 13.
- the source / drain electrodes 18 are formed on the n + silicon layer 17 and, for example, a metal such as Mo or Mo alloy, a metal such as titanium (Ti), aluminum (Al) or Al alloy, copper (Cu) or Cu alloy, etc. Or a metal material such as silver (Ag), chromium (Cr), tantalum (Ta), or tungsten (W).
- a metal such as Mo or Mo alloy
- a metal such as titanium (Ti), aluminum (Al) or Al alloy, copper (Cu) or Cu alloy, etc.
- a metal material such as silver (Ag), chromium (Cr), tantalum (Ta), or tungsten (W).
- the thin film transistor 100 is configured.
- FIG. 3 is a diagram showing an example of an equivalent circuit of a unit repeating cell of a thin film transistor array used in the display device according to the embodiment of the present invention.
- the equivalent circuit shown in FIG. 3 includes a switching transistor 1, a drive transistor 2, a data line 3, a scanning line 4, a current supply line 5, a capacitance 6, and a light emitting element 7.
- the switching transistor 1 is connected to the data line 3, the scanning line 4, and the capacitance 6.
- the driving transistor 2 corresponds to, for example, the thin film transistor 100 shown in FIG. 2 and is connected to the current supply line 5, the capacitance 6, and the light emitting element 7.
- the data line 3 is a wiring through which data (the magnitude of the voltage value) that determines the brightness of the pixel of the light emitting element 7 is transmitted to the pixel of the light emitting element 7.
- the scanning line 4 is a wiring through which data for determining a pixel switch (ON / OFF) of the light emitting element 7 is transmitted to the pixel of the light emitting element 7.
- the current supply line 5 is a wiring for supplying a large current to the drive transistor 2.
- Capacitance 6 holds a voltage value (charge) for a certain period of time.
- the display device is configured as described above.
- FIG. 4 is a flowchart showing a manufacturing process of a thin film transistor constituting the thin film transistor array used in the display device according to the embodiment of the present invention.
- a plurality of the thin film transistors 100 are manufactured on the substrate at the same time, but in the following description, a method of manufacturing one thin film transistor will be described in order to simplify the description.
- 5A to 5J are diagrams for explaining a method of manufacturing a thin film transistor array used in the display device according to the embodiment of the present invention.
- FIG. 6 is a diagram schematically showing laser annealing in S14 of FIG.
- the substrate 10 is prepared, the undercoat layer 11 is formed on the substrate 10 (S10), and then the gate electrode is formed on the undercoat layer 11 (S11).
- an undercoat layer 11 is formed on the substrate 10 by plasma CVD, and then a metal film to be a gate electrode is deposited by sputtering, and the gate electrode 12 in the thin film transistor 100 is formed by photolithography and etching.
- the gate electrode 12 is typically formed of a metal material such as Mo or an Mo alloy (for example, MoW (molybdenum / tungsten alloy)).
- a gate insulating layer 13 is formed on the gate electrode 12 (S12). Then, an amorphous silicon layer 14 is formed on the gate insulating layer 13 (S13).
- a silicon oxide film or a silicon nitride film, or a stack of a silicon oxide film and a silicon nitride film is formed by plasma CVD so as to cover the undercoat layer 11 and the gate electrode 12 on the gate electrode 12.
- a gate insulating layer 13 is formed by forming a film (FIG. 5B), and an amorphous silicon layer 14 is continuously formed on the formed gate insulating layer 13 (FIG. 5C).
- the amorphous silicon layer 14 is turned into a crystalline silicon layer 15 by laser annealing (S14). Specifically, the amorphous silicon layer 14 is crystallized using laser light emitted from a predetermined laser to generate the crystalline silicon layer 15. More specifically, first, a dehydrogenation process is performed on the formed amorphous silicon layer 14. As the dehydrogenation treatment, a method of heating at a temperature of 450 ° C. or higher in an annealing furnace in a nitrogen atmosphere is common. Thereafter, the amorphous silicon layer 14 is made polycrystalline (including microcrystals) by laser annealing to form a crystalline silicon layer 15 (FIG. 5D).
- the laser light source used for laser irradiation is a laser having a wavelength in the visible light region as described above.
- the laser having a wavelength in the visible light region is a laser having a wavelength of about 380 nm to 780 nm, and preferably a laser having a wavelength of 400 nm to 600 m.
- the laser having a wavelength in the visible light region may be in a pulse oscillation mode, a continuous oscillation mode, or a pseudo continuous oscillation mode.
- the laser having a wavelength in the visible light region may be constituted by a solid-state laser device or a laser device using a semiconductor laser element.
- the laser having a wavelength in the visible light region has a variation in irradiation energy density of less than about 5% when irradiated on the amorphous silicon layer 14.
- step of S14 that is, the steps of FIGS. 5C to 5D, as shown in FIG. Is generated.
- the laser beam is irradiated while moving relative to the amorphous silicon layer 14. As described above, the amorphous silicon layer 14 irradiated with the laser light is crystallized by absorbing the energy of the laser light and rising in temperature to become the crystalline silicon layer 15.
- a laser beam other than the laser beam condensed in a linear shape may be used, and a spot-shaped laser beam (including a circle, an ellipse, etc.) may be used. In that case, it is preferable to perform laser light irradiation by a scanning method suitable for crystallization.
- a second amorphous silicon layer 16 is formed (S15), and the silicon layer in the channel region of the thin film transistor 100 is patterned (S16).
- a second amorphous silicon layer 16 is formed on the gate insulating layer 13 by plasma CVD (FIG. 5E). Then, the silicon layer film layer (the crystalline silicon layer 15 and the amorphous silicon layer 16) is patterned so that the channel region of the thin film transistor 100 remains, and the amorphous silicon layer 16 and the crystalline silicon layer 15 to be removed are patterned. Are removed by etching (FIG. 5F). Accordingly, a desired channel layer can be formed in the thin film transistor 100.
- n + silicon layer 17 and the source / drain electrodes 18 are formed (S17).
- an n + silicon layer 17 is formed by plasma CVD so as to cover the side surfaces of the amorphous silicon layer 16 and the crystalline silicon layer 15 and the gate insulating layer 13 (FIG. 5G).
- a metal to be the source / drain electrode 18 is deposited on the deposited n + silicon layer 17 by sputtering (FIG. 5H).
- the source / drain electrodes are a metal such as Mo or Mo alloy, a metal such as titanium (Ti), aluminum (Al) or Al alloy, a metal such as copper (Cu) or Cu alloy, or silver (Ag). , Chromium (Cr), tantalum (Ta), or tungsten (W).
- the source / drain electrode 18 is patterned (S18). Then, the n + silicon layer 17 is etched, and in the process, the second amorphous silicon layer 16 is partially etched (S19).
- the source / drain electrodes 18 are formed by photolithography and wet etching (FIG. 5I). Further, the n + silicon layer 17 is etched, and the amorphous silicon layer 16 in the channel region of the thin film transistor 100 is partially etched (FIG. 5J). In other words, the amorphous silicon layer 16 is channel etched so as to leave a part of the amorphous silicon layer 16 in the channel region of the thin film transistor 100.
- the thin film transistor 100 is manufactured.
- FIG. 7 is a diagram showing an example of a cross section of an equivalent circuit of the unit repeating cell of the thin film transistor array according to the embodiment of the present invention. Elements similar to those in FIG. 3 and FIGS. 5A to 5J are denoted by the same reference numerals, and detailed description thereof is omitted.
- a silicon nitride film is formed as an interlayer insulating film by plasma CVD on the entire surface of the substrate 10 for protection and passivation of the thin film transistor 100. Subsequently, contact holes are opened on the source / drain electrodes 18. This is performed by photolithography and dry etching. Thereafter, a metal thin film mainly made of Al or Cu is formed on the entire surface of the substrate 10 by sputtering, and the data lines 3 and the current supply lines 5 are formed by photolithography and wet etching.
- the thin film transistor 100 in this embodiment is formed as a Poly-Si TFT having a bottom gate structure.
- the gate insulating layer 13 and the amorphous silicon layer 14 are formed in a thickness range that satisfies the above-described relationship.
- the amorphous silicon layer 14 is crystallized by laser annealing with a laser beam having a wavelength in the visible light region, more preferably 400 nm to 600 nm, whereby the amorphous silicon layer 14 is crystallized.
- the crystallinity of the crystalline silicon layer 15 in the channel region where the thin film transistor is formed can be changed according to the gate capacitance of the gate insulating layer 13.
- the crystalline silicon layer 15 can be formed on the entire surface of the substrate so that the crystallinity of the crystalline silicon layer 15 has a negative correlation with the gate capacitance of the gate insulating layer 13.
- the crystalline silicon layer 15 is formed on the entire surface of the substrate so that the average crystal grain size of the crystalline silicon layer 15 on the gate electrode has a negative correlation with the gate capacitance of the gate insulating layer 13.
- the crystalline silicon has a positive correlation with the gate capacitance of the gate insulating layer 13 so that the half width of the peak near 520 cm ⁇ 1 in the Raman scattering spectrum of the crystalline silicon layer 15 on the gate electrode has a positive correlation.
- Layer 15 can be formed over the entire surface of the substrate.
- the thin film transistor 100 provided with the crystalline silicon layer 15 formed in this way in the channel has a driving capacity corresponding to the gate capacity corresponding to the film thickness of the gate insulating layer 13. Since it can be canceled by the conduction capability, it is possible to reduce variations in on characteristics between thin film transistors including the gate insulating layer 13 having different capacities with different film thicknesses. Therefore, a thin film transistor array including such thin film transistors 100 has a uniform in-plane distribution of on characteristics.
- the film thicknesses of the gate insulating layer 13 and the amorphous silicon layer 14 are formed so as to satisfy the above-described conditions, and the amorphous silicon layer 14 is crystallized using the laser beam described above.
- the crystalline silicon layer 15 is used as a channel layer of the thin film transistor.
- each film thickness fluctuates from the target film thickness (target film thickness).
- the gate insulating layer 13 and the amorphous silicon layer 14 are continuously formed on the gate electrodes 12 formed in large numbers on the substrate 10.
- the target film thickness of the gate insulating layer 13 is d GI and the target film thickness of the amorphous silicon layer 14 is da -Si .
- the gate insulating layer 13 and the amorphous silicon layer 14 are formed on the substrate 10 with respective target film thicknesses by a CVD apparatus, for example. In that case, the gate insulating layer 13 and the amorphous silicon layer 14 vary from the target film thickness within the plane.
- This fluctuation depends on the fluctuation of the gas flow in the film forming chamber of the CVD apparatus and how the plasma standing wave is formed.
- D a-Si ⁇ ⁇ d a-Si (decoding arbitrary) can be considered to be formed on the substrate with a probability that it is not zero.
- the absorptance A of the amorphous silicon layer 14 corresponding to the variable film thickness group including the target film thickness group (d GI , d a-Si ) will be considered.
- the absorption rate A is the absorption rate of the amorphous silicon layer 14 on the gate electrode 12 with respect to laser light having a wavelength ⁇ . Since the absorption rate A is a function of the film thickness of the gate insulating layer 13 and the film thickness of the amorphous silicon layer 14, the absorption rate A is set for each set of target film thicknesses (a set of variable film thicknesses). Can be calculated uniquely.
- the gate insulating layer 13 is composed of a plurality of types of films (for example, the film 131 and the film 132), the film 131 has a thickness d GI1 and the film 132 has a film thickness d GI2 .
- the film 131 has a thickness d GI1
- the film 132 has a film thickness d GI2 .
- ⁇ d GI1 and ⁇ d GI2 for the membrane. The same can be considered when there are more types of membranes.
- the absorptivity A of the amorphous silicon layer on the gate electrode 12 in the variable film thickness group (including the target film thickness group) corresponding to the target film thickness group (d GI , d a-Si ) is calculated.
- the correlation between the absorption rate A and the fluctuation film thickness (d GI ⁇ ⁇ d GI , d a-Si ⁇ ⁇ d a-Si ) can be defined.
- the gate combination of the variation of the insulating layer 13 may be replaced by a set of variations in the gate capacitance of the gate insulating layer 13 (defined as C GI ⁇ ⁇ C GI).
- (d GI ⁇ ⁇ d GI , d a-Si ⁇ ⁇ d a-Si ) can be considered to be replaced with (C GI ⁇ ⁇ C GI , d a-Si ⁇ ⁇ d a-Si ).
- the correlation between A and the gate capacitance variation set can be defined.
- the thickness of the gate insulating layer 13 corresponding to each of the plurality of gate electrodes 12 (specifically, the equivalent oxide thickness of the gate insulating layer 13), and the amorphous silicon layer on the gate electrode 12
- the film thickness range of the region in which the absorptance with respect to 14 laser beams has a positive correlation is defined by the combination of the laser light wavelength ⁇ and the variable film thickness (d GI ⁇ ⁇ d GI , d a-Si ⁇ ⁇ d a-Si )
- the amorphous silicon layer 14 corresponding to each of the plurality of gate electrodes 12 is formed in a film thickness range in which the light absorptance is small with respect to the film thickness change of the amorphous silicon layer 14.
- This film thickness range has a good correlation between the absorption rate A and the gate capacitance (C GI ⁇ ⁇ C GI ) defined at this time (for example, when an approximate straight line is drawn, the R-square value is larger than 0 and the lowest)
- C GI ⁇ ⁇ C GI gate capacitance
- the film thickness ranges of the gate insulating layer 13 and the amorphous silicon layer 14 that can obtain the effects of the present invention can be calculated as follows.
- the absorptance A with respect to the laser beam having the wavelength ⁇ is calculated.
- the correlation between the absorption rate A and the fluctuation capacity obtained from the imaginary fluctuation film thickness is examined, and the approximate straight line of the correlation has a negative inclination, and the R square value of the film thickness is a value greater than zero.
- the gate insulating layer 13 is formed of a laminated film of an insulating film 1301 and an insulating film 1302. Specifically, description will be made on the assumption that an insulating film 1301 is formed on the gate electrode 12 and an insulating film 1302 is formed on the insulating film 1301 to form the gate insulating layer 13.
- the calculation procedure of the absorptance of the amorphous silicon layer 14 on the gate electrode 12 with respect to the laser beam having the wavelength ⁇ will be described below.
- the light absorptance of the multilayer thin film constituting the thin film transistor 100 can be obtained by calculating the amplitude reflectance and the amplitude transmittance for each constituent film.
- FIG. 8 is a diagram for explaining a method of calculating the amplitude reflectance and the amplitude transmittance.
- FIG. 8 is a diagram showing a model structure of a multilayer structure in which the structure of the thin film transistor 100 shown in FIG. 2 is modeled.
- a layer 401 composed of a complex refractive index N1
- a layer 402 composed of a complex refractive index N2
- a layer 403 composed of a complex refractive index N3,
- a layer 404 composed of a complex refractive index N4, and a complex refractive index.
- a substrate layer 405 (not shown) made of N5.
- a layer 404, a layer 403, a layer 402, and a layer 401 are stacked on the substrate layer 405 in this order.
- the region of the complex refractive index N0 shown in the figure is outside the model structure and indicates the side on which the laser light is incident on the model structure. This region is, for example, air or N 2 gas.
- the substrate layer 405 is an insulating substrate made of, for example, transparent glass or quartz, and corresponds to the substrate 10 shown in FIG. 5A.
- the layer 404 is made of a metal thin film having a film thickness of 1% or less with respect to the laser beam.
- the layer 404 is made of a refractory metal such as Mo, Cr, or W.
- the gate electrode 12 shown in FIG. Corresponding to The layer 403 is composed of an insulating film 1301, and the layer 402 is composed of an insulating film 1302.
- the insulating film 1301 and the insulating film 1302 are, for example, dielectric thin films such as silicon nitride and silicon oxide.
- a stacked film of these two layers corresponds to the gate insulating layer 13 shown in FIG. 5A.
- the layer 401 corresponds to the amorphous silicon layer 14.
- the layer corresponding to the undercoat layer 11 is omitted in the model structure shown in FIG.
- the amplitude reflection coefficient for light incident on the layer 401 from the outside is r01
- the amplitude reflection coefficient for light incident on the layer 402 from the layer 401 is r12
- the amplitude reflection coefficient is incident on the layer 401 from the layer 402.
- the amplitude reflection coefficient for the incident light is r23
- the amplitude reflection coefficient for the light incident on the layer 404 from the layer 403 is r34.
- the amplitude transmission coefficient of light incident on the layer 401 from the outside is t01
- the amplitude transmission coefficient of light incident on the layer 402 from the layer 401 is t12
- the amplitude transmission coefficient of light incident on the layer 402 from the layer 402 is t23
- the amplitude transmission coefficient of light incident on the layer 404 from the layer 403 is t34.
- the amplitude reflection coefficients of the entire layers above the region where the layer 404 corresponding to the gate electrode 12 is formed are r01234 (R1), r1234 (R2), and r234 (R3), respectively.
- the amplitude reflection coefficient when the layers 404 and 403 are regarded as one layer is r234 (R3).
- the amplitude reflection coefficient when the layers 404, 403, and 402 are regarded as one layer is r1234 (R2)
- the amplitude reflection when the layers 404, 403, 402, and 401 are regarded as one layer.
- the coefficient is r01234 (R1).
- T1 t01234
- T234 t234
- the amplitude reflection coefficient and amplitude transmission coefficient of the entire layer above the region where the layer 404 corresponding to the gate electrode 12 is formed can be expressed by the following (Expression 1) to (Expression 6).
- d n is the film thickness of each layer
- theta n the angle of incidence and transmission angles of each layer
- lambda the wavelength of the laser beam.
- ⁇ can be calculated as shown in the following (Expression 7) from Snell's law of the following expression.
- the amplitude reflection coefficients r01, r12, r23, r34 and the amplitude transmission coefficients t01, t12, t12, t34 of each layer can be calculated using the following (Expression 8) to (Expression 15).
- the light is monochromatic laser light, and the polarization is assumed to be P-polarized light.
- the amplitude reflection coefficient and amplitude transmission coefficient of the entire layer above the region where the layer 404 corresponding to the gate electrode 12 is formed are calculated as follows. That is, first, r234 is calculated by substituting (Equation 10) and (Equation 11) into (Equation 3). Next, r1234 is calculated by substituting (Equation 9) and r234 into (Equation 2). Next, r01234 is calculated by substituting (Equation 8) and r1234 into (Equation 3). Next, t234 is calculated by substituting (Expression 10), (Expression 11), (Expression 14), and (Expression 15) into (Expression 6).
- t1234 is calculated by substituting (Equation 9), (Equation 13), r234, and t234 into (Equation 5).
- t01234 is calculated by substituting (Equation 8), (Equation 12), r1234, and t1234 into (Equation 4).
- the reflectances R1, R2 and R3 and the transmittances T1, T2 and T3 in the respective layers above the region where the layer 404 corresponding to the gate electrode 12 is formed are calculated by (Expression 16) to (Expression 21). To do.
- the light absorption rate of the amorphous silicon layer on the gate electrode can be calculated.
- the calculation result is the same even if the polarization of the laser beam is S polarization.
- the amorphous silicon layer 14 has a thickness of da -Si .
- the insulating film 1301 constituting the gate insulating layer 13 is a silicon nitride film and the insulating film 1302 is a silicon oxide film.
- the film thickness (thickness of the silicon nitride film: d SiN, silicon oxide film having a thickness: d SiO) is used to calculate the absorptivity to laser light of the amorphous silicon layer 14 on the gate electrode 12 be able to.
- the insulating film 1301 and the insulating film 1302 are made of the same material, for example, so that the gate insulating layer 13 is formed of a single-layer insulating film.
- the absorption rate of the amorphous silicon layer 14 on the electrode 12 with respect to the laser beam can be calculated.
- the film thickness of the amorphous silicon layer 14 for obtaining the effects of the present invention has a suitable range.
- FIG. 9 is a diagram for explaining that there is a preferable film thickness range for the amorphous silicon layer when the crystalline silicon layer is formed by the laser annealing crystallization method.
- FIG. 9 is definitive when the gate insulating layer 13 is formed of a silicon oxide film monolayer, standardized by the laser beam wavelength lambda, the optical thickness of the amorphous silicon layer 14 (n a -Si ⁇ d a-Si / ⁇ ) and the absorption of the laser beam wavelength lambda of the amorphous silicon layer 14, which is normalized by the optical thickness of the normalized silicon oxide film with a laser beam wavelength lambda (a / (N SiO xd SiO 2 / ⁇ )).
- Each curve shown in FIG. 9 corresponds to the value of the optical film thickness (n SiO ⁇ d SiO / ⁇ ) of the silicon oxide film normalized by the laser light wavelength ⁇ .
- the relationship shown in FIG. 9 is derived by the above-described method for calculating the absorptance of the amorphous silicon layer 14 on the gate electrode 12 with respect to the laser light when the wavelength range of the laser light is 400 nm to 600 nm.
- n a-Si ⁇ d a-Si / ⁇ that gives the maximum of the curve is shifted according to n SiO ⁇ d SiO / ⁇ .
- the amorphous silicon layer 14 is a film in which the influence of the variation in the thickness of the amorphous silicon layer 14 on the variation in the absorption rate of the amorphous silicon layer 14 on the gate electrode is reduced. It is necessary to form in the thickness range.
- the range of the film thickness where the influence of the variation in the thickness of the amorphous silicon layer 14 on the variation in the absorption rate of the amorphous silicon layer 14 on the gate electrode is any n SiO xd SiO 2.
- the curve of / ⁇ also corresponds to the film thickness range of the amorphous silicon layer 14 in the vicinity of n a-Si ⁇ d a-Si / ⁇ that gives the maximum. That is, the preferable film thickness range of the amorphous silicon layer 14 is a film corresponding to a region within a predetermined range with respect to the maximum value for any curve of n SiO xd SiO / ⁇ . It is in the thickness range.
- the film thickness range corresponding to the range where the differential coefficient is ⁇ 5 to +5 can be given by (Equation 23).
- the gate insulating layer 13 As long as the insulating film constituting the gate insulating layer 13 is transparent to laser light, that is, the extinction coefficient of the insulating film constituting the gate insulating layer 13 is small enough not to affect multiple interference ( 0.01 or less), the gate insulating layer 13 does not absorb laser light. Therefore, a preferable range of the film thickness of the amorphous silicon layer 14 is established regardless of its configuration.
- the gate insulating layer 13 is described as being composed of a single silicon oxide layer for the sake of simplicity, but the present invention is not limited thereto. As long as the gate insulating layer 13 is composed of a transparent insulating film, the optical film thickness (sum of the product of the refractive index and the film thickness of the insulating layer) is replaced with the optical film thickness of the silicon oxide layer described above. This is true.
- the wavelength range of the laser light is 400 nm to 600 nm, and the range of na -Si ⁇ da -Si / ⁇ is 0.426 to 0.641.
- the insulating film 1301 constituting the gate insulating layer 13 described above is described as a silicon nitride film, for example, and the insulating film 1302 is described as a silicon oxide film, for example.
- the gate capacitance CGI of the gate insulating layer 13 is a combined capacitance of the capacitance of the silicon oxide film and the capacitance of the silicon nitride film, and can be calculated by (Equation 24).
- the relative dielectric constant of the silicon oxide film is ⁇ SiO 2
- the relative dielectric constant of the silicon nitride film is ⁇ SiN
- the dielectric constant of vacuum is ⁇ 0 .
- thickness variation of the set (d a-Si ⁇ ⁇ d a -Si, d SiO ⁇ ⁇ d SiO, d SiN ⁇ ⁇ d SiN) ( decoding optional), as described above, when the laser beam wavelength is lambda, This is a set of film thicknesses when the target film thickness (da -Si , dSiO , dSiN ) varies by 15% from the film thickness.
- FIG. 10A is a diagram for showing that there is a preferable film thickness range for the film thickness of the insulating film constituting the gate insulating layer 13 when the crystalline silicon layer 15 is formed by the laser annealing crystallization method.
- FIG. 10A plots the coefficients of the approximate line in the correlation between the absorption rate A and the normalized gate capacitance CGI ′ as a contour map.
- FIG. 10B is a diagram showing that there is a preferable film thickness range for the film thickness of the insulating film constituting the gate insulating layer 13 when the crystalline silicon layer 15 is formed by the laser annealing crystallization method.
- FIG. 10B the R2 squared value of the approximation straight line in the correlation between the absorption factor A and the normalized gate capacitance C GI ', which is a plot as a contour plot.
- the horizontal axis X represents the optical film thickness of the silicon oxide layer, that is, the value obtained by multiplying the refractive index n SiO of the silicon oxide layer by the film thickness d SiO of the silicon oxide layer, and the wavelength ⁇ of the laser beam.
- a value obtained by dividing by X, that is, X (n SiO ⁇ d SiO ) / ⁇ .
- the values shown in FIGS. 10A and 10B are generalized with respect to the laser light wavelength and the optical constant of the gate insulating layer 13.
- the optical constants of the material of the gate electrode 12, specifically the refractive index n and the extinction coefficient k, affect the absolute value of the absorption rate A of the amorphous silicon layer 14 on the gate electrode 12.
- the correlation with the normalized gate capacitance C GI ' is not affected.
- the values shown in FIGS. 10A and 10B are generalized for the material of the gate electrode 12.
- Region A and region B shown in FIG. 10A are regions where the coefficient of the approximate straight line in the correlation between the absorption rate A and the normalized gate capacitance C GI ′ is negative. Specifically, the region A is a region expressed by (Expression 25) and (Expression 26), and the region B is a region expressed by (Expression 27) and (Expression 28).
- the film thicknesses of the silicon oxide film and the silicon nitride film satisfying the mathematical formulas represented by (Formula 25) and (Formula 26) or (Formula 27) and (Formula 28) as the target film thickness, Even if the film thickness varies in the substrate plane, the absorption rate A of the amorphous silicon layer 14 on each gate electrode 12 and the gate capacitance at each gate electrode 12 have a negative correlation.
- the gate insulating layer 13 can be formed.
- region 1 and region 2 shown in FIG. 10B are regions in which the R-square value of the approximate line in the correlation between the absorption rate A and the normalized gate capacitance C GI ′ is 0.3 or more.
- the region 1 is a region represented by (Equation 29) and (Equation 30)
- the region 2 is a region represented by (Equation 31) and (Equation 32).
- FIG. 10B shows the area A and the area B calculated in FIG. 10A. Therefore, as shown in FIG. 10B, it can be seen that region 1 and region 2 are included in region A and region B.
- the gate insulating layer 13 can be formed so that the gate capacitance at 12 has a negative correlation.
- the region 1 and the region 2 are the most preferable film thickness ranges of the gate insulating layer 13 and the amorphous silicon layer 14 in which the effects of the present invention can be obtained.
- the case where the silicon oxide film and the silicon nitride film are stacked in this order as the gate insulating layer 13 is not necessarily described.
- the above-described film thickness range may be derived again after exchanging X and Y described above.
- the gate insulating layer 13 may be composed of a single layer.
- the absorption rate A of the amorphous silicon layer 14 on each gate electrode 12 and the gate capacitance at each gate electrode 12 have a negative correlation by the same calculation method as described above.
- the target film thickness range of the gate insulating layer 13 can be derived.
- d GI represents the average film thickness of the gate insulating layer
- ⁇ represents the laser beam wavelength
- n GI represents the refractive index of the gate insulating layer 13 with respect to the laser beam having the wavelength ⁇ .
- the gate insulating layer 13 By forming the gate insulating layer 13 within this range, when the gate insulating layer 13 is formed of a single layer insulating film, the film thicknesses of the gate insulating layer 13 and the amorphous silicon layer 14 are within the substrate plane. Even if it fluctuates, the absorptivity A of the amorphous silicon layer 14 on each gate electrode 12 and the gate capacitance at each gate electrode 12 can have a negative correlation. That is, the range of the film thickness represented by (Expression 35) or (Expression 36) is the most preferable range of the target film thickness of the gate insulating layer 13 in which the effect of the present invention can be obtained.
- the film thicknesses of the amorphous silicon layer 14 and the gate insulating layer 13 that can obtain the effects of the present invention are derived. I was able to.
- this derivation method can be used regardless of whether the gate insulating layer 13 has a laminated structure or a single layer structure. That is, by using this derivation method, it is possible to derive the film thicknesses of the amorphous silicon layer 14 and the gate insulating layer 13 that can obtain the effects of the present invention regardless of the configuration of the gate insulating layer 13.
- the gate insulating layer 13 includes a silicon nitride film and a silicon oxide film
- the gate insulating layer 13 has a structure in which a silicon nitride film and a silicon oxide film are laminated in order from the gate electrode 12.
- FIG. 11 is a diagram showing a specific example of a film thickness range suitable for the film thickness of the insulating film constituting the gate insulating layer 13 when the crystalline silicon layer 15 is formed by the laser annealing crystallization method.
- the range from 0 to 0.8 in X and Y shown in FIG. 10B is expanded, and X and Y are converted into actual silicon oxide film and silicon nitride film thicknesses.
- the refractive index of the silicon oxide film is 1.467
- the refractive index of the silicon nitride film is 1.947.
- the refractive index of the amorphous silicon layer 14 is 5.07, and the extinction coefficient is 0.61.
- the target film thickness range of the amorphous silicon layer 14 is assumed to be 44.7 nm to 67.3 nm. This film thickness range is derived from the above (Expression 23) to (Expression 32).
- the structural conditions (conditions 1 to 3) of the gate insulating layer 13 were examined.
- conditions 1 to 3 that is, the configuration conditions of the three gate insulating layers 13 are set so that the equivalent oxide film thickness is approximately 120 nm.
- Condition 1 is included in the most suitable region 1 and Condition 2 is included in at least the region A.
- the condition 3 is not included in either the region 1 or the region A. Therefore, in conditions 1 to 3, condition 1 is the most preferable condition, and condition 2 is the preferable condition.
- Condition 3 is an unfavorable conventional condition.
- 12A to 12C are diagrams showing the relationship between the capacitance formed by the varying film thickness and the absorptance of the amorphous silicon layer 14.
- the film thickness on the gate electrode 12 is the film thickness when the film thickness varies ⁇ 15% from the target film thickness.
- 3 shows the correlation between the absorption rate of the laser beam of the amorphous silicon layer 14 and the gate capacity of the gate insulating layer 13.
- the horizontal axis of FIG. 12A indicates the normalized gate capacitance that is a value normalized by the gate capacitance of the gate insulating layer 13 having the target film thickness, and the vertical axis indicates the absorption rate.
- the target film thickness of the amorphous silicon layer 14 was set to 60 nm.
- FIG. 12B is a diagram when the target film thickness of the gate insulating layer 13 is configured under condition 2
- FIG. 12C is a diagram when the target film thickness of the gate insulating layer 13 is configured under condition 3. .
- the relationship between the gate capacitance and the absorption rate of the amorphous silicon layer 14 on the gate electrode 12 is an approximate straight line. Is almost zero. This indicates that the film thickness condition does not change the absorption rate of the amorphous silicon layer 14 on the gate electrode 12 with respect to the film thickness fluctuation of the gate insulating layer 13. It means that it is one mode of the film thickness condition as disclosed in Document 2. Further, the R-square value is almost 0, and it can be seen that the film thickness variation of the amorphous silicon layer 14 has a great influence on the absorption rate variation.
- FIGS. 13A to 13C are diagrams showing the relationship between the capacitance formed by the varying film thickness and the crystallinity of the amorphous silicon layer 14.
- the film thickness on the gate electrode 12 is the film thickness when the film thickness varies ⁇ 15% from the target film thickness.
- 3 shows the correlation between the half width of the peak of the Raman shift spectrum around 520 cm ⁇ 1 when the region of the amorphous silicon layer 14 is measured by Raman scattering spectroscopy and the gate capacitance of the gate insulating layer 13.
- the horizontal axis of FIG. 12 indicates the normalized gate capacitance that is a value normalized by the gate capacitance of the gate insulating layer 13 having the target film thickness
- the vertical axis indicates the crystalline silicon obtained when the target film thickness is obtained. It is normalized by the half width of the layer 15.
- FIG. 13B is a diagram when the target film thickness of the gate insulating layer 13 is configured under condition 2
- FIG. 13C is a diagram when the target film thickness of the gate insulating layer 13 is configured under condition 3. .
- an increase in the half width indicates that the crystallinity of the crystalline silicon layer 15 is deteriorated, and conversely, a decrease in the half width indicates that the crystallinity of the crystalline silicon layer 15 is improved.
- the target film thickness of the gate insulating layer 13 is configured under the condition 1
- the crystallinity of the crystalline silicon layer 15 on the gate electrode 12 deteriorates. It can be seen that when the capacitance decreases, the crystallinity of the crystalline silicon layer 15 on the gate electrode 12 is improved. Therefore, by setting the target film thickness conditions so as to be included in the most preferable region 1, as confirmed in FIG. 12A, as the gate capacitance increases, the amorphous silicon layer 14 on the gate electrode 12 increases. It is possible to reduce the absorption rate. Thereby, the correlation between the gate capacitance and the crystallinity of the crystalline silicon layer 15 formed on the gate electrode 12 by laser light irradiation can be made negative (the correlation between the gate capacitance and the Raman half width is positive). .
- FIGS. 14A to 14C are diagrams showing the relationship between the capacitance formed by the varying film thickness and the on-current of the thin film transistor 100 using the crystalline silicon layer 15 as a channel.
- FIG. 14A shows the crystalline silicon obtained by crystallizing the amorphous silicon layer 14 with the capacitance formed by the varying film thickness when the target film thickness of the gate insulating layer 13 is configured under the condition 1. It is a figure which shows the relationship with the ON current of the thin-film transistor 100 which used the layer 15 as the channel.
- the thin film transistor array used for the evaluation is formed on the glass substrate using the crystalline silicon layer 15 obtained by crystallizing the amorphous silicon layer 14 under the laser annealing conditions described above. The on-current was evaluated for one of the thin film transistors 100 of this thin film transistor array.
- the capacitance formed by the varying film thickness was evaluated by a gate capacitance evaluation TEG (Test Element Group) formed in the vicinity of the corresponding thin film transistor 100.
- TEG Test Element Group
- the gate capacitance and the on-current are aimed at and standardized by the characteristics of the thin film transistor 100 under the film thickness condition.
- FIG. 14B is a diagram when the target film thickness of the gate insulating layer 13 is configured under condition 2
- FIG. 14C is a diagram when the target film thickness of the gate insulating layer 13 is configured under condition 3. .
- condition 1 the maximum and minimum of the on-current are within ⁇ 20% of the center value, and there is the least variation in on-current compared to other conditions. Further, as shown in FIG. 14B, in condition 2, the maximum and minimum of the on-current are slightly over ⁇ 20% with respect to the center value.
- the maximum and minimum of the on-current are ⁇ 30% or more with respect to the center value, and the on-current of the thin film transistor constituting the channel region of the thin film transistor is varied.
- the variation is large. Therefore, in the prior art, when using a film thickness condition that minimizes the variation in the absorption rate of the amorphous silicon layer 14 on the gate electrode 12, when the layer thickness of the channel layer of the thin film transistor 100 varies, The variation in crystallinity of the crystalline silicon layer 15 on the gate electrode 12 can be reduced to some extent. However, it can be seen that when a plurality of thin film transistors 100 are formed in the substrate surface, it is difficult to reduce the variation in their on-currents.
- the aim is to satisfy the region A (and the region B) derived as the film thickness region in which the effect of the present invention is obtained, and the region 1 (and the region 2) which is a further preferable range.
- the film thickness By setting the film thickness, the crystallinity of the crystalline silicon layer 15 on the gate electrode 12 can be reduced with respect to the increased increase in gate capacitance. As a result, even if the film thickness varies from the target film thickness, the ON characteristics of the plurality of thin film transistors 100 can be kept uniform.
- the target film thicknesses of the gate insulating layer 13 of the thin film transistor 100 and the amorphous silicon layer 14 before laser annealing crystallization are calculated as described above.
- the absorption rate of the amorphous silicon layer 14 on the gate electrode 12 and the gate formed by the gate insulating layer 13 are formed.
- Correlation with capacity can be negative.
- the variation in the absorption rate of the amorphous silicon layer 14 on the gate electrode 12 with respect to the variation in the film thickness of the amorphous silicon layer 14 can be reduced.
- the present invention it is possible to realize a thin film transistor array manufacturing method, a thin film transistor array, and a display device using the thin film transistor array that can be configured with thin film transistors having uniform on characteristics.
- the crystalline silicon layer 15 whose crystallinity is intentionally changed according to the change in the gate capacitance of the thin film transistor 100 can be formed using a laser having a wavelength in the visible light region.
- a thin film transistor array manufacturing method, a thin film transistor array, and a display device using the same can be realized in which the ON characteristics of the respective thin film transistors 100 constituting the thin film transistor array thus manufactured are made uniform.
- the amorphous silicon layer 14 and the gate insulating layer 13 so that each film thickness satisfies a predetermined condition, a gate capacitance is obtained using a laser having a wavelength in the visible light region.
- the crystalline silicon layer 15 having a negative correlation with the crystallinity of the crystalline silicon layer 15 on the gate electrode 12 can be formed.
- the thin film transistor array of the present invention when used in the display device shown in FIG. 15, a high-quality display device having uniform transistor characteristics can be realized. Further, the yield can be improved and the cost can be reduced by improving the display quality.
- the effect can be realized by taking the film thickness condition within the above range without changing the pattern shape of the gate electrode 12 and the like, in particular, the structure of the thin film transistor and the circuit configuration. Therefore, for example, even when a higher-definition display device is manufactured, it can be said that the design flexibility can be maintained over the conventional technology.
- the present invention can be used for a method of manufacturing a thin film transistor array, a thin film transistor array, a liquid crystal panel using the thin film transistor array, or a display device including an EL panel such as an organic EL panel. Even if the film thickness of the channel constituent layer (amorphous silicon layer, gate insulating layer) varies, the on-state characteristics of each thin film transistor constituting the thin film transistor array are uniform, high-quality liquid crystal panel, organic EL panel, etc. It can be used for manufacturing a display device including an EL panel.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
まず、ゲート絶縁層、および非晶質シリコン層を形成する場合、それぞれの膜厚は狙った膜厚(狙い膜厚)から変動する。
Y≦49.9X6-131X5+127X4-56.8X3+11.8X2-2.01X+0.736 (式26)
Y≧-7.34X6+8.48X5+8.65X4-16.0X3+7.24X2-2.04X+0.961 (式27)
Y≦-3.75X6+11.8X5-13.1X4+6.09X3-1.12X2-0.87X+1.20 (式28)
Y≦23.7X6-4.56X5-35.4X4+27.2X3-5.75X2-0.973X+0.619 (式30)
Y≧7.46X6-32.4X5+50.8X4-35.7X3+11.0X2-2.20X+1.04 (式31)
Y≦-5.34X6+16.7X5-18.7X4+9.18X3-1.96X2-0.821X+1.13 (式32)
0.96≦nGI×dGI/λ≦1.20 (式34)
1.04≦nGI×dGI/λ≦1.13 (式36)
2 駆動トランジスタ
3 データ線
4 走査線
5 電流供給線
6 キャパシタンス
7 発光素子
10 基板
11 アンダーコート層
12 ゲート電極
13 ゲート絶縁層
14、16 非晶質シリコン層
15 結晶質シリコン層
17 n+シリコン層
18 ソース・ドレイン電極
100 薄膜トランジスタ
401、402、403、404 層
405 基板層
1301、1302 絶縁膜
Claims (20)
- 基板を準備する第1工程と、
前記基板上に複数のゲート電極を形成する第2工程と、
前記複数のゲート電極上にゲート絶縁層を形成する第3工程と、
前記ゲート絶縁層上に非晶質性シリコン層を形成する第4工程と、
レーザーから照射されるレーザー光を用いて前記非晶質性シリコン層を結晶化させて結晶性シリコン層を生成する第5工程と、
前記複数のゲート電極の各々に前記結晶性シリコン層上の領域にソース電極およびドレイン電極を形成する第6工程と、を含み、
前記第3工程において、前記複数のゲート電極上の前記ゲート絶縁層の膜厚を、前記ゲート電極上の前記非晶質性シリコン層の前記レーザー光に対する光吸収率と前記ゲート絶縁層の等価酸化膜厚とが正の相関にある領域の膜厚範囲で形成し、
前記第4工程において、前記複数のゲート電極上の前記非晶質性シリコン層の膜厚を、前記非晶質性シリコン層の膜厚変化に対する前記光吸収率の変動が第1基準から所定の範囲内にある領域の膜厚範囲で形成する、
薄膜トランジスタアレイの製造方法。 - 前記レーザーは、固体レーザー装置で構成される、
請求項1に記載の薄膜トランジスタアレイの製造方法。 - 前記レーザーは、半導体レーザー素子を用いたレーザー装置で構成される、
請求項1に記載の薄膜トランジスタアレイの製造方法。 - 前記第5工程において、前記レーザー光の前記非晶質性シリコン層上における照射エネルギー密度の変動は、5%程度未満である、
請求項1~3のいずれか1項に記載の薄膜トランジスタアレイの製造方法。 - 前記レーザーの波長範囲は、400nm以上600nm以下である、
請求項1~4のいずれか1項に記載の薄膜トランジスタアレイの製造方法。 - 前記第4工程において、
前記非晶質性シリコン層の膜厚を、前記第1基準から所定の範囲内にある領域の膜厚範囲として、前記レーザー光の波長λで規格化された前記ゲート絶縁層の光学膜厚によって規格化された非晶質シリコン層のレーザー光波長λの吸収率を、前記レーザー光の波長λで規格化された、前記非晶質シリコン層の光学膜厚で微分したときの微分係数が-5以上、+5以下となる膜厚範囲で形成する、
請求項1~5のいずれか1項に記載の薄膜トランジスタアレイの製造方法。 - 前記第4工程において、前記非晶質性シリコン層は、
前記複数のゲート電極上の前記非晶質シリコン層の平均膜厚が、下記の式1)で表される範囲に含まれるように、形成されている、
請求項1~6のいずれか1項に記載の薄膜トランジスタアレイの製造方法。
式1)0.426≦na-Si×da-Si/λSi≦0.641、ここで、da-Siは前記非晶質シリコン層の平均膜厚を表し、λSiは前記レーザー光波長を表し、na-Siは前記非晶質シリコン層の波長λのレーザー光に対する屈折率を表す。 - 前記第3工程において、前記ゲート絶縁層は、前記レーザー光の波長に対する前記ゲート絶縁層の消衰係数が0.01以下で形成されている、
請求項1~7のいずれか1項に記載の薄膜トランジスタアレイの製造方法。 - 前記ゲート絶縁層は、酸化珪素膜である、
請求項1~8のいずれか1項に記載の薄膜トランジスタアレイの製造方法。 - 前記ゲート絶縁層は、窒化珪素膜である、
請求項1~8のいずれか1項に記載の薄膜トランジスタアレイの製造方法。 - 前記ゲート絶縁層は、酸化珪素膜と窒化珪素膜との積層膜から構成される、
請求項1~8のいずれか1項に記載の薄膜トランジスタアレイの製造方法。 - 前記第3工程において、前記ゲート絶縁層は、
前記複数のゲート電極上の前記ゲート絶縁層の平均膜厚が、下記の式2)で表される範囲または下記の式3)で表される範囲に含まれるように形成される、
請求項1~10のいずれか1項に記載の薄膜トランジスタアレイの製造方法。
式2)0.44≦nGI×dGI/λ≦0.74、
式3)0.96≦nGI×dGI/λ≦1.20、
ここで、dGIは前記ゲート絶縁層の平均膜厚を表し、λは前記レーザー光波長を表し、nGIは前記ゲート絶縁層の波長λのレーザー光に対する屈折率を表す。 - 前記第3工程において、前記ゲート絶縁層は、
前記複数のゲート電極上の前記ゲート絶縁層の平均膜厚が、下記の式4)で表される範囲または下記の式5)で表される範囲に含まれるように形成される、
請求項1~12のいずれか1項に記載の薄膜トランジスタアレイの製造方法。
式4)0.47≦nGI×dGI/λ≦0.62、
式5)1.04≦nGI×dGI/λ≦1.13、
ここで、dGIは前記ゲート絶縁層の平均膜厚を表し、λは前記レーザー光波長を表し、nGIは前記絶縁層の波長λのレーザー光に対する屈折率を表す。 - 前記第3工程において、前記ゲート絶縁層は、
前記複数のゲート電極上の前記酸化珪素膜の平均膜厚と前記複数のゲート電極上の前記窒化珪素膜の平均膜厚とが、下記の式6)および式7)で表される領域、または式8)および式9)で表される領域に含まれるように形成される、
請求項1~11のいずれか1項に記載の薄膜トランジスタアレイの製造方法。
式6)Y≧-1070X6+1400X5-688X4+153X3-12.90X2-1.02X+0.439、
式7)Y≦49.9X6-131X5+127X4-56.8X3+11.8X2-2.01X+0.736、
式8)Y≧-7.34X6+8.48X5+8.65X4-16.0X3+7.24X2-2.04X+0.961、
式9)Y≦-3.75X6+11.8X5-13.1X4+6.09X3-1.12X2-0.87X+1.20、
ここで、X=dSiO×nSiO/λ、かつ、Y=dSiN×nSiN/λであり、dSiOは前記酸化珪素膜の平均膜厚を表し、dSiNは前記窒化珪素膜の平均膜厚を表し、λは前記レーザー光波長を表し、nSiOは前記酸化珪素膜の波長λのレーザー光に対する屈折率を表し、nSiNは前記窒化珪素膜の波長λのレーザー光に対する屈折率を表す。 - 前記第3工程において、前記ゲート絶縁層は、
前記複数のゲート電極上の前記酸化珪素膜の平均膜厚と前記複数のゲート電極上の前記窒化珪素膜の平均膜厚とが、下記の式10)および式11)で表される領域、または、式12)および式13)で表される領域に含まれるように形成される、
請求項1~14のいずれか1項に記載の薄膜トランジスタアレイの製造方法。
式10)Y≧-132.6X6+181X5-93.8X4+21.3X3-1.33X2-1.04X+0.473、
式11)Y≦23.7X6-4.56X5-35.4X4+27.2X3-5.75X2-0.973X+0.619、
式12)Y≧7.46X6-32.4X5+50.8X4-35.7X3+11.0X2-2.20X+1.04、
式13)Y≦-5.34X6+16.7X5-18.7X4+9.18X3-1.96X2-0.821X+1.13、
ここで、X=dSiO×nSiO/λ、かつ、Y=dSiN×nSiN/λであり、dSiOは前記酸化珪素膜の平均膜厚を表し、dSiNは前記窒化珪素膜の平均膜厚を表し、λは前記レーザー光波長を表し、nSiOは前記酸化珪素膜の波長λのレーザー光に対する屈折率を表し、nSiNは前記窒化珪素膜の波長λのレーザー光に対する屈折率を表す。 - 前記第2工程は、
前記基板上に透明絶縁膜からなるアンダーコート層を形成する工程と、前記アンダーコート層上に複数のゲート電極を形成する工程とを含む、
請求項1~15のいずれか1項に記載の薄膜トランジスタ装置の製造方法。 - 基板と、
前記基板上に形成された複数のゲート電極と、
前記複数のゲート電極上に共通に形成されたゲート絶縁層と、
前記ゲート絶縁層上に形成された結晶性シリコン層と、
前記複数のゲート電極の各々の前記結晶性シリコン層上の領域に形成されたソース電極およびドレイン電極とを備え、
前記結晶性シリコン層は、前記ゲート絶縁層上に形成された非晶質性シリコン層を、レーザーから照射されるレーザー光を用いて結晶化させて形成され、
前記複数のゲート電極上の前記ゲート絶縁層の膜厚は、前記ゲート電極上の前記非晶質性シリコン層の前記レーザー光に対する光吸収率と前記等価酸化膜厚とが正の相関にある領域の膜厚範囲で形成され、
前記複数のゲート電極上の前記非晶質性シリコン層の膜厚は、前記非晶質性シリコン層の膜厚変化に対する前記光吸収率の変動が第1基準から所定の範囲内にある領域の膜厚範囲で形成されている、
薄膜トランジスタアレイ。 - 前記ゲート電極上における前記結晶性シリコン層の平均結晶粒径は、前記ゲート電極上の前記ゲート絶縁層のゲート容量に対して、負の相関を有している、
請求項17に記載の薄膜トランジスタアレイ。 - 前記ゲート電極上における前記結晶性シリコン層における520cm-1付近のラマン散乱スペクトルピークの半値幅は、前記ゲート電極上の前記ゲート絶縁層のゲート容量に対して、正の相関を有している、
請求項17に記載の薄膜トランジスタアレイ。 - 液晶パネルまたはELパネルを含む表示装置であって、
請求項17~19のいずれか1項に記載の薄膜トランジスタアレイを備え、
前記薄膜トランジスタアレイは、前記液晶パネルまたはELパネルを駆動させる、
表示装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2011/004769 WO2013030865A1 (ja) | 2011-08-26 | 2011-08-26 | 薄膜トランジスタアレイの製造方法、薄膜トランジスタアレイおよび表示装置 |
KR1020127008728A KR20140051753A (ko) | 2011-08-26 | 2011-08-26 | 박막 트랜지스터 어레이의 제조 방법, 박막 트랜지스터 어레이 및 표시 장치 |
CN2011800041383A CN103109360A (zh) | 2011-08-26 | 2011-08-26 | 薄膜晶体管阵列的制造方法、薄膜晶体管阵列以及显示装置 |
US13/438,954 US8679907B2 (en) | 2011-08-26 | 2012-04-04 | Thin-film transistor array manufacturing method, thin-film transistor array, and display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2011/004769 WO2013030865A1 (ja) | 2011-08-26 | 2011-08-26 | 薄膜トランジスタアレイの製造方法、薄膜トランジスタアレイおよび表示装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/438,954 Continuation US8679907B2 (en) | 2011-08-26 | 2012-04-04 | Thin-film transistor array manufacturing method, thin-film transistor array, and display device |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2013030865A1 true WO2013030865A1 (ja) | 2013-03-07 |
Family
ID=47742345
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2011/004769 WO2013030865A1 (ja) | 2011-08-26 | 2011-08-26 | 薄膜トランジスタアレイの製造方法、薄膜トランジスタアレイおよび表示装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8679907B2 (ja) |
KR (1) | KR20140051753A (ja) |
CN (1) | CN103109360A (ja) |
WO (1) | WO2013030865A1 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016001722A (ja) * | 2014-04-08 | 2016-01-07 | 株式会社半導体エネルギー研究所 | 半導体装置及び該半導体装置を含む電子機器 |
CN109976596A (zh) * | 2014-06-27 | 2019-07-05 | 宸盛光电有限公司 | 触控感应单元 |
CN106898655B (zh) * | 2017-03-22 | 2019-09-03 | 上海天马微电子有限公司 | 薄膜晶体管、阵列基板及显示面板 |
CN108732833A (zh) * | 2018-05-24 | 2018-11-02 | 京东方科技集团股份有限公司 | 阵列基板及其制作方法、显示装置 |
KR20220022016A (ko) * | 2020-08-14 | 2022-02-23 | 삼성디스플레이 주식회사 | 디스플레이 장치의 제조 장치 및 디스플레이 장치의 제조 방법 |
CN113314424B (zh) * | 2021-05-27 | 2022-09-02 | 惠科股份有限公司 | 薄膜晶体管及其制备方法和阵列基板、显示器件 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10189450A (ja) * | 1996-12-27 | 1998-07-21 | Sony Corp | 半導体装置の製造方法 |
WO2011033718A1 (ja) * | 2009-09-17 | 2011-03-24 | パナソニック株式会社 | 結晶シリコン膜の形成方法、それを用いた薄膜トランジスタおよび表示装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007220918A (ja) | 2006-02-16 | 2007-08-30 | Ulvac Japan Ltd | レーザアニール方法、薄膜半導体装置及びその製造方法、並びに表示装置及びその製造方法 |
US7662703B2 (en) * | 2006-08-31 | 2010-02-16 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing crystalline semiconductor film and semiconductor device |
US9082857B2 (en) * | 2008-09-01 | 2015-07-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device comprising an oxide semiconductor layer |
-
2011
- 2011-08-26 CN CN2011800041383A patent/CN103109360A/zh active Pending
- 2011-08-26 KR KR1020127008728A patent/KR20140051753A/ko not_active Application Discontinuation
- 2011-08-26 WO PCT/JP2011/004769 patent/WO2013030865A1/ja active Application Filing
-
2012
- 2012-04-04 US US13/438,954 patent/US8679907B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10189450A (ja) * | 1996-12-27 | 1998-07-21 | Sony Corp | 半導体装置の製造方法 |
WO2011033718A1 (ja) * | 2009-09-17 | 2011-03-24 | パナソニック株式会社 | 結晶シリコン膜の形成方法、それを用いた薄膜トランジスタおよび表示装置 |
Also Published As
Publication number | Publication date |
---|---|
CN103109360A (zh) | 2013-05-15 |
US20130049004A1 (en) | 2013-02-28 |
KR20140051753A (ko) | 2014-05-02 |
US8679907B2 (en) | 2014-03-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8865529B2 (en) | Thin-film transistor device manufacturing method, thin-film transistor device, and display device | |
WO2013030865A1 (ja) | 薄膜トランジスタアレイの製造方法、薄膜トランジスタアレイおよび表示装置 | |
US9929274B2 (en) | Thin-film transistor, method for fabricating thin-film transistor, and display device | |
WO2013051221A1 (ja) | 薄膜素子、薄膜素子アレイ及び薄膜素子の製造方法 | |
WO2011161714A1 (ja) | シリコン薄膜の結晶化方法およびシリコンtft装置の製造方法 | |
JP5309387B2 (ja) | 半導体層とこの半導体層を用いた半導体装置および表示装置 | |
US8785302B2 (en) | Crystal silicon film forming method, thin-film transistor and display device using the crystal silicon film | |
JP2020004860A (ja) | 薄膜トランジスタ、表示装置及び薄膜トランジスタの製造方法 | |
JP2020004859A (ja) | 薄膜トランジスタ、表示装置及び薄膜トランジスタの製造方法 | |
US8884296B2 (en) | Thin-film transistor device manufacturing method, thin-film transistor device, and display device | |
JP2012114131A (ja) | 薄膜トランジスタ、その製造方法、および表示装置 | |
US8778746B2 (en) | Thin-film transistor device manufacturing method, thin-film transistor, and display device | |
JP2013161963A (ja) | 薄膜トランジスタ、薄膜トランジスタの製造方法、及び表示装置 | |
US8518763B2 (en) | Thin-film transistor device manufacturing method, thin-film transistor device, and display device | |
JP2013232548A (ja) | 薄膜トランジスタ装置の製造方法、薄膜トランジスタ装置および表示装置 | |
US8530900B2 (en) | Method for selectively forming crystalline silicon layer regions above gate electrodes | |
JPWO2013030865A1 (ja) | 薄膜トランジスタアレイの製造方法、薄膜トランジスタアレイおよび表示装置 | |
JPWO2013069045A1 (ja) | 薄膜トランジスタ装置の製造方法、薄膜トランジスタ装置および表示装置 | |
WO2012060104A1 (ja) | トランジスタの製造方法、トランジスタ、および、表示装置 | |
Sugawara et al. | The uniform crystallization process towards the bottom-gated LTPS TFT back-plane technology for large-sized AM-OLED displays by CW green laser annealing | |
WO2013018123A1 (ja) | 薄膜トランジスタ及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 201180004138.3 Country of ref document: CN |
|
ENP | Entry into the national phase |
Ref document number: 2011554296 Country of ref document: JP Kind code of ref document: A |
|
ENP | Entry into the national phase |
Ref document number: 20127008728 Country of ref document: KR Kind code of ref document: A |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 11871714 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 11871714 Country of ref document: EP Kind code of ref document: A1 |