WO2013026291A1 - Procédé de codage et codeur pour codage parallèle extensible quasi cyclique à entrelacement de blocs de code ldpc - Google Patents

Procédé de codage et codeur pour codage parallèle extensible quasi cyclique à entrelacement de blocs de code ldpc Download PDF

Info

Publication number
WO2013026291A1
WO2013026291A1 PCT/CN2012/075198 CN2012075198W WO2013026291A1 WO 2013026291 A1 WO2013026291 A1 WO 2013026291A1 CN 2012075198 W CN2012075198 W CN 2012075198W WO 2013026291 A1 WO2013026291 A1 WO 2013026291A1
Authority
WO
WIPO (PCT)
Prior art keywords
matrix
bit
coding
ldpc code
check
Prior art date
Application number
PCT/CN2012/075198
Other languages
English (en)
Chinese (zh)
Inventor
耿敏明
陈为刚
董同昕
葛超
Original Assignee
中兴通讯股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中兴通讯股份有限公司 filed Critical 中兴通讯股份有限公司
Publication of WO2013026291A1 publication Critical patent/WO2013026291A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1191—Codes on graphs other than LDPC codes
    • H03M13/1194—Repeat-accumulate [RA] codes
    • H03M13/1197—Irregular repeat-accumulate [IRA] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/611—Specific encoding aspects, e.g. encoding by means of decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations

Definitions

  • the present invention relates to the field of error control coding techniques, and more particularly to a packet interleaving quasi-cyclic extended parallel coding LDPC code coding method and encoder. Background technique
  • the decoding of LDPC codes mainly adopts soft decision decoding algorithm.
  • the soft decision decoding algorithm can be realized by iterative decoding based on Belief Propagation (BP) algorithm, and good bit error rate performance can be obtained.
  • BP Belief Propagation
  • the LDPC code can implement the decoding process within linear complexity, and the decoding can be performed in parallel, which is suitable for implementation in hardware.
  • a major problem encountered in LDPC codes in applications is the high coding complexity. In general, the codes have complex 0(n 2 ), where n is the code length of the LDPC code, which is the constraint on LDPC codes in high-speed data services.
  • An important factor in the application is that in high signal-to-noise ratio regions, LDPC codes have a bit error platform phenomenon.
  • the so-called error platform refers to a phenomenon in which the bit error rate does not significantly decrease with an increase in the signal-to-noise ratio in a high signal-to-noise ratio region.
  • LDPC code error floor phenomenon occurs, and many applications, such as satellite digital broadcasting, digital fiber optic communication and storage systems, requires the bit error decoder The rate is lower than io- 7 .
  • One type of method is to restrict the check matrix of the LDPC code to achieve linear or approximate linear coding of the LDPC code.
  • the LDPC code designed by this method can obtain better error correction performance, and the coding complexity is moderate.
  • Another method is to use a structured LDPC code construction method, that is, a quasi-loop construction method such as an LDPC code based on European geometry or projective geometry.
  • the constructed LDPC code has a low coding complexity and is well suited for implementation with shift registers.
  • the LDPC code specified in the IEEE 802.16e standard adopts the above two basic ideas from the perspective of simplifying coding complexity.
  • the matrix structure uses a quasi-cyclic shift and matrix blocking technique to decompose a large check matrix / into multiple small matrices.
  • the LDPC code in the IEEE 802.16e standard is a set of one or more basic LDPC codes, where each basic LDPC code is a systematic linear block code.
  • the check matrix of the LDPC code is:
  • ⁇ is a set of zxz permutation matrix or zero matrix, where ⁇ has a value range of 0, 1, 2, (m b -l); _ has a value range of 0, 1 , 2, (n b -l); check matrix / extended by m 3 ⁇ 4 dimensional basic matrix, thus, code length
  • the permutation matrix is generated by cyclically shifting the unit matrix of zxz by a right shift. Therefore, the permutation matrix can be determined by the cyclic right shift factor.
  • the information bits, 3 ⁇ 4 2 correspond to the check bits.
  • 3 ⁇ 4 2 can be further decomposed into two as shown in formula (2)
  • the part is a 3 ⁇ 4 dimension vector, where there are 3 non-zero elements, which are double diagonal matrices.
  • the loop right shift factor corresponding to ⁇ m b -l , and i ⁇ x. 1 ⁇ 40) and (m fc -l) must be the same. Is the row index of the element with a median of 1. 1 1 ⁇ 2 in constructing H, are extended as a unit matrix.
  • the IEEE 802.16e standard provides a fast coding algorithm using check matrix partitioning.
  • the algorithm divides the check matrix H into the following form:
  • ⁇ zX(mz) / are extensions corresponding to h b and H b2 respectively
  • an effective solution that can be implemented according to the existing error control coding technology is to design a serial concatenated code based on LDPC codes, using the outer code. To reduce or eliminate the error platform of the LDPC code.
  • the transmission code efficiency is not excessively sacrificed, and the outer code rate of the concatenated code is required to be high, so that the error correction capability of the outer code is limited. Therefore, to design an efficient serial concatenated code based on LDPC codes, it is required that the number of error bits in the error code word of the LDPC code as the inner code is small, and the error type is a random error.
  • the LDPC code specified in the IEEE 802.16e standard has too many error bits in the error codeword under high SNR. If it is used as the inner code, it is difficult to design an efficient serial concatenated code. . This has become another important factor that restricts the application of LDPC codes specified in the IEEE 802.16e standard in high data rate communications. Summary of the invention
  • the main purpose of the embodiments of the present invention is to provide a coding method and an encoder for a packet-interleaved quasi-cyclic extended parallel coding LDPC code, so as to solve the problem that the coding efficiency of the LDPC code is not high, and the error is high at a high SNR. There are many errors in the codeword.
  • Embodiments of the present invention provide a quasi-cyclic extended parallel coding LDPC code of packet interleaving.
  • An encoding method the method comprising:
  • the check matrix of the low density parity check (LDPC) code is divided into a submatrix corresponding to the information bits and a square matrix corresponding to the check bits;
  • the parity bits of the LDPC code are encoded by parallel random interleaving single-bit accumulation coding.
  • the configuration of the sub-matrix of the corresponding information bit includes:
  • the information bit base matrix is extended by a quasi-cyclical method to obtain an information bit extension matrix; the information bit extension matrix is group-interleaved to obtain a sub-matrix of corresponding information bits.
  • the basic matrix of information bits is a binary matrix containing element 0 and element 1.
  • the quasi-cyclical method is used to extend the information bit basic matrix to obtain an information bit extension matrix, including: replacing the element 0 in the information bit basic matrix with a zero matrix, and replacing the element 1 in the information bit basic matrix with the permutation matrix to obtain the information bit. Expansion matrix.
  • Performing packet interleaving on the information bit extension matrix to obtain a sub-matrix of the corresponding information bits including: dividing the information bit extension matrix into rows into a plurality of block row matrices;
  • Random row interleaving is performed on each of the block row matrices to obtain a submatrix corresponding to the information bits.
  • the performing random row interleaving for each of the block row matrices separately includes:
  • Each of the block row matrices is left-multiplied by a different random row interleaving matrix.
  • the square matrix corresponding to the risk location is a block diagonal matrix; the block submatrix on the diagonal of the partition diagonal matrix is a double diagonal matrix; in the double diagonal matrix, the diagonal The elements on the line and the elements in the next line of the diagonal are 1 and the elements in the remaining positions are 0.
  • the check bit code of the LDPC code is composed of a plurality of parallel check bit coding branches.
  • the check bits of the LDPC code are encoded by using a parallel random interleaving single bit accumulation coding manner, including:
  • Blocking row moments of the information bit spreading matrix in each of the check bit encoding branches The left bit is multiplied by the input information bit vector to obtain a result vector;
  • the sub-code vectors of each of the check bit coding branches are input to a single bit accumulator for accumulation, and the coding of the LDPC code is completed.
  • An embodiment of the present invention further provides an LDPC code encoder, including: a construction module and an encoding module, where:
  • the constructing module is configured to construct a check matrix comprising a sub-matrix corresponding to the information bits and a packet-interleaved quasi-cyclic extended parallel coded LDPC code of the square matrix corresponding to the check bits;
  • the encoding module is configured to encode the check bits of the LDPC code by using a parallel random interleaving single bit accumulating encoding manner according to the check matrix.
  • the constructing module includes: a sub-matrix construction sub-module, configured to expand the information bit basic matrix by using a quasi-cyclic manner to obtain an information bit expansion matrix; and perform packet interleaving on the information bit extension matrix to obtain a sub-matrix of the corresponding information bits.
  • the sub-matrix construction sub-module is further configured to replace the element 0 in the basic matrix of the information bit with a zero matrix, replace the element 1 in the basic matrix of the information bit with a permutation matrix, to obtain an information bit extension matrix; and further set to expand the information bits
  • the matrix is divided into a plurality of block row matrices by rows; each of the block row matrices is randomly interleaved to obtain a submatrix corresponding to the information bits.
  • the construction module further includes a square matrix construction sub-module, which is configured to construct an element on the diagonal and a double diagonal matrix of elements of the lower row of the diagonal line and the remaining position of the element is 0;
  • the square matrix corresponding to the check digit is constructed as a block diagonal matrix.
  • the check bit code of the LDPC code is composed of a plurality of parallel check bit coding branches; correspondingly, the coding module is configured to use the information bits in each of the check bit coding branches
  • the block row matrix of the extended matrix is multiplied by the input information bit vector to obtain a result vector; And multiplying the result vector by a random row interleaving matrix to obtain a sub-coding vector of each check bit encoding branch; and inputting the sub-coding vector of each check bit encoding branch into a single-bit accumulator for accumulating , complete the encoding of the LDPC code.
  • the check matrix of the LDPC code can be divided into a sub-matrix of the corresponding information bits and a square matrix of the corresponding check bits, wherein the corresponding information
  • the sub-matrices of the bits are obtained by expanding the basic matrix of the information bits by using a quasi-cyclical method, then dividing the expanded matrix by rows, and respectively performing random row interleaving on each of the block-row matrixes;
  • the square matrix of bits is a block diagonal matrix, and the block submatrix on the diagonal is a double diagonal square matrix.
  • the quasi-cyclic extended parallel coding LDPC code of packet interleaving adopts multi-channel parallel random interleaving single-bit accumulative coding method, the coding method is simple, the coding time is linear with the code length, and the throughput rate is high; at high SNR, the packet interleaving The number of error bits in the error codeword of the quasi-cyclic extended parallel coded LDPC code is small, and can be used as an inner code of an efficient serial concatenated code.
  • FIG. 1 is a schematic diagram of a school insurance matrix structure of a quasi-cyclic extended parallel coded LDPC code of packet interleaving according to an embodiment of the present invention
  • Example interleaving is performed; block row of the matrix H;.
  • FIG. 4 is a schematic block diagram of an encoder of a quasi-cyclic extended parallel coding LDPC code of packet interleaving according to an embodiment of the present invention
  • FIG. 5 is a non-zero element distribution diagram of an information bit extension matrix H m of a quasi-cyclic extended parallel coded LDPC code of a packet interleaving having a code length of 576 bits and a code rate of 1/2 according to an embodiment of the present invention
  • FIG. 6 is a schematic diagram of packet interleaving with a code length of 576 bits and a code rate of 1/2 according to an embodiment of the present invention; Cyclic expansion of the bit error rate of the parallel coded LDPC code;
  • FIG. 7 is a cumulative distribution diagram of error bit numbers in an error codeword when a signal-to-noise ratio is 4.5 dB with a signal-to-noise ratio of 4.5 dB, which is a packet interleaving quasi-cyclic extended parallel coded LDPC code with a code length of 576 bits and a code rate of 1/2 in the embodiment of the present invention. . detailed description
  • the sub-matrix of the corresponding information bits in the check matrix of the packet-interleaved parallel-coded LDPC code proposed by the embodiment of the present invention is to expand the basic matrix by using a quasi-cyclical manner, and the corresponding school-bit position in the check matrix
  • the square matrix is a block diagonal matrix, and the block sub-matrices on the diagonal are double diagonal matrices.
  • the check bits of the LDPC code defined by the check matrix can be obtained by random interleaving single bit accumulation coding, which reduces the coding complexity.
  • the quasi-cyclic extended parallel coding LDPC code check matrix of the packet interleaving according to the embodiment of the present invention is divided into a sub-matrix of corresponding information bits and a square matrix of corresponding check bits; according to the check matrix, parallel random interleaving single bit accumulation is adopted.
  • the coding mode encodes the check bits of the LDPC code.
  • the sub-matrix of the corresponding information bit comprises: expanding the information bit basic matrix by using a quasi-cyclic method to obtain an information bit expansion matrix; and performing packet interleaving on the information bit extension matrix to obtain a sub-matrix corresponding to the information bit.
  • the square matrix corresponding to the school risk position is a block diagonal matrix; the block submatrix on the diagonal of the block diagonal matrix is a double diagonal matrix; in the double diagonal matrix, the elements and pairs on the diagonal The element in the next line of the corner is 1 and the element in the remaining position is 0.
  • the check bit coding of the LDPC code is composed of a plurality of parallel check bit coding branches.
  • the parallel random interleaving single-bit accumulating encoding method is used to encode the check bits of the LDPC code, including:
  • the information bit vector of the information bit spreading matrix is multiplied by the input information bit vector to obtain a result vector; Multiplying the result vector by left multiplication and randomization by a random row interleaving matrix to obtain a sub-coding vector of each parity-coding branch;
  • the sub-code vector of each check bit coding branch is input to a single bit accumulator for accumulation, and the coding of the LDPC code is completed.
  • H c as shown in FIG. 1 , where is a sub-matrix of mxfc corresponding to the information bit, and H c is a square matrix corresponding to the x of the school risk.
  • the sub-matrix H m of the corresponding information bits in the parity check matrix H is obtained by spreading the information bit basic matrix H fc of m 3 ⁇ 4 and performing block-line interleaving.
  • the information bit basic matrix H fc is a binary matrix containing element 0 and element 1.
  • the row interleaving of the block row matrix H/ is performed by using the random row interleaving matrix ⁇ ;
  • the information bit basic matrix H b of m fc x is expanded in a quasi-cyclic manner to obtain an information bit expansion matrix H m .
  • the expansion method is: replacing the element 0 in the basic matrix of the information bit with the zero matrix of zxz, and replacing the element 1 in the basic matrix of the information bit with the permutation matrix of zxz to obtain the information bit expansion matrix H m .
  • the information bit basis matrix H b and the information bit extension matrix H m can be associated by the information bit model matrix ⁇ of m b x k b .
  • an information bit model matrix H fcm can be obtained.
  • the information bit extension matrix can be obtained by extending the information bit model matrix H bm directly with the zero matrix and the permutation matrix.
  • the interleaving method is:
  • the information bit extension matrix is divided into rows by a plurality of block row matrices:
  • the information bit expansion matrix / admir is divided into rows to obtain H ⁇ ' iH Hv'Hj , where Hj ⁇ j ⁇ L ) is zxk Block line matrix;
  • a 6x6 row interleaving matrix is used to perform row interleaving on a 6x18 information bit extension matrix/'s block row matrix H/, that is, a row transformation is performed, wherein the block row matrix is sequentially looped from left to right.
  • the right shift factor 3, the cyclic right shift factor 4 and the cyclic right shift factor 2 are composed of three 6x6 permutation matrices, and the result of row interleaving is r ; . . . . . .
  • the interleaved matrix is group interleaved.
  • the form of H m is as shown in the formula (8).
  • the square matrix H c of the corresponding parity bit in the parity check matrix H of the packet-interleaved parallel coding LDPC code proposed by the embodiment of the present invention is a block diagonal matrix of mxm, as shown in the formula (9),
  • the block submatrix on the diagonal is a double diagonal matrix, the elements on the diagonal and the elements in the next row of the diagonal are 1, and the elements in the remaining positions are 0.
  • other positions 0', 0
  • the structure of the check matrix H is such that the LDPC code proposed by the embodiment of the present invention can implement parity bit coding by using parallel random interleave single bit accumulation coding.
  • H: 1 is also a block diagonal matrix of mxm, as shown in formula (11), the submatrix on the diagonal line / ⁇ is the lower triangular matrix of zxz; as shown in formula (12), - diagonal
  • This structure of / ⁇ can be implemented by a single-bit accumulator, that is, multiply / ⁇ left by a vector of length z, and the s (l ⁇ s ⁇ z) components in the resulting vector are the former in the original vector. The sum of the s components.
  • H: 1 and HJ structures check digit vector /? The expression is as shown in equation (13). Therefore, the check digit vector /? can be divided into L segments, /?
  • the coded LDPC code can be implemented by parallel random interleaving single bit accumulation.
  • the information bit extension matrix H zxfc is used to block the row matrix matrix and multiply the input information bit vector M to obtain the result vector H,
  • the sub-coding vector m. of each check bit encoding branch is input into a single-bit accumulator for accumulation, and the encoding of the LDPC code is completed. Specifically:
  • the single-bit accumulator outputs one check bit each time, and the single-bit accumulator of each check bit encoding branch accumulates a total time in one encoding process, and outputs a sub-check bit vector Pj of length, sub-check bits.
  • the advantage of the packet-interleaved quasi-cyclic extended parallel-coded LDPC code proposed by the embodiment of the present invention is that, on the one hand, the coding mode is parallel random interleaving single-bit accumulation coding, The code mode is simple, the coding time is linear with the code length, and the coding throughput is high due to the parallel coding.
  • the quasi-cyclic extended parallel coding LDPC code of the packet interleaving according to the embodiment of the present invention has fewer error bits in the error codeword under high SNR, and if it is used as the inner code of the serial concatenation code, Then, when the error correction capability of the outer code is limited, the bit error rate and the frame error rate can be effectively reduced.
  • the LDPC code encoding method of the embodiment of the present invention is described below by using a specific embodiment.
  • the embodiment of the present invention takes the design of a quasi-cyclic extended parallel coding LDPC code with a code length of 576 bits and a code rate of 1/2 as an example, and introduces a check matrix construction method of a quasi-cyclic extended parallel coding LDPC code for packet interleaving. And check bit coding method.
  • a 12x12 information bit model matrix H fcm is designed for a quasi-cyclic extended parallel coded LDPC code with a code length of 576 bits and a code rate of 1/2, such that the spreading factor z The value is 24.
  • a sub-matrix corresponding to information bits in a model matrix of an LDPC code having a code length of 576 bits and a code rate of 1/2 is used in the IEEE 802.16e standard, as a quasi-cyclic extended parallel coding LDPC code of packet interleaving in the embodiment.
  • the information bit model matrix H fcm which is shown in equation (14).
  • (1 ⁇ ; ⁇ 12) is a 12x12 random row interleaving matrix.
  • the code length of the packet design is 576 bits
  • the quasi-cyclic extended parallel coding LDPC code of the packet interleaving rate of 1/2 is implemented by 12 parallel random interleaving single bit accumulation coding mode, and the encoder is implemented.
  • the encoding steps are:
  • the encoded code length obtained after encoding is 576 bits
  • the quasi-cyclical spreading of the 1/2 packet interleaving extends the error bit number distribution characteristic of the parallel coded LDPC code in the error codeword at a high SNR.
  • Quasi-cyclic extended parallel coding of packet interleaving designed in the embodiment The bit error rate performance of the LDPC code is shown in Figure 6.
  • the bit error rate is 1.52X10" 6 ; when the signal-to-noise ratio is 4.5dB, the cumulative number of error bits in the error code word is as follows. As shown in Fig. 7, in the figure, "the number of error bits in the error code word is indicated, and P ( « ⁇ N) indicates the probability of the number of error bits in the error code word "not greater than N.
  • the number of error bits in the error codeword of the quasi-cyclic extended parallel coded LDPC code of the packet interleaving according to the embodiment of the present invention is much less than that of the IEEE 802.16e standard, which is 576 bits.
  • the code rate is 1/2 LDPC code. Therefore, the quasi-cyclic extended parallel coding LDPC code of the packet interleaving according to the embodiment of the present invention has the characteristics of having fewer error bits in the error codeword under high SNR, and is suitable as an inner code of an efficient serial concatenated code.
  • the embodiment of the present invention is directed to the field of error control coding, including the channel coding in the digital communication system, to implement the coding method of the foregoing LDPC code, and the embodiment of the present invention further provides an LDPC code encoder, including: a construction module and an encoding module, where :
  • a construction module configured to construct a quasi-cyclic extended parallel coding LDPC code of a packet interleaving of a sub-matrix corresponding to the information bit and a square matrix of the corresponding parity bit;
  • the encoding module is configured to encode the LDPC code by using a parallel random interleaving single-bit accumulating encoding method according to the check matrix.
  • the construction module includes: a sub-matrix construction sub-module for expanding in a quasi-cyclic manner The information matrix basic matrix is obtained, and the information bit expansion matrix is obtained; and the information bit extension matrix is group-interleaved to obtain a sub-matrix of the corresponding information bits.
  • the sub-matrix construction sub-module is also used to replace the element 0 in the basic matrix of the information bit with a zero matrix, replace the element 1 in the basic matrix of the information bit with a permutation matrix, to obtain an information bit expansion matrix; and also to press the information bit extension matrix
  • the row is divided into a plurality of block row matrices; each row block matrix is randomly interleaved to obtain a submatrix corresponding to the information bits.
  • the construction module also includes a square matrix construction sub-module, which is used to construct an element on the diagonal and an element of the lower line of the diagonal line is 1 , and the remaining position element is a double diagonal matrix of 0; also used to construct a diagonal
  • the square matrix is constructed as a block diagonal matrix.
  • the check bit code of the LDPC code is composed of a plurality of parallel check bit coding branches; correspondingly, the coding module is configured to use the block line matrix of the information bit extension matrix in each of the check bit coding branches Multiply the input information bit vector to obtain a result vector; use a random row interleaving matrix to multiply the left multiplication result vector to obtain a sub-coding vector of each check bit encoding branch; and encode the sub-coding vector of each check bit encoding branch Input a single-bit accumulator to accumulate and complete the encoding of the LDPC code.

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Error Detection And Correction (AREA)

Abstract

L'invention porte sur un procédé de codage et un codeur pour codage parallèle extensible quasi cyclique à entrelacement de blocs d'un code de contrôle de parité à faible densité (LDPC). Le procédé comprend les opérations suivantes : une matrice de contrôle de code LDPC est divisée en une sous-matrice correspondant aux bits d'informations et en une matrice carrée correspondant aux bits de contrôle ; et application d'un procédé de codage à accumulation de bits uniques entrelacés aléatoire parallèle pour coder les bits de contrôle du code LDPC. Le procédé de codage pour codage parallèle extensible quasi cyclique à entrelacement de blocs d'un code LDPC est simple, et la relation entre temps de codage et longueur de code est linéaire, et le débit est élevé ; et en présence d'un rapport signal sur bruit élevé, il existe un plus petit nombre de bits d'erreur dans des mots de code erreur dans le codage parallèle extensible quasi cyclique entrelacé d'un code LDPC, qui peut servir de codes internes de codes concaténés série à rendement élevé.
PCT/CN2012/075198 2011-08-24 2012-05-08 Procédé de codage et codeur pour codage parallèle extensible quasi cyclique à entrelacement de blocs de code ldpc WO2013026291A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201110244269.0A CN102394660B (zh) 2011-08-24 2011-08-24 分组交织的准循环扩展并行编码ldpc码的编码方法和编码器
CN201110244269.0 2011-08-24

Publications (1)

Publication Number Publication Date
WO2013026291A1 true WO2013026291A1 (fr) 2013-02-28

Family

ID=45861870

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/075198 WO2013026291A1 (fr) 2011-08-24 2012-05-08 Procédé de codage et codeur pour codage parallèle extensible quasi cyclique à entrelacement de blocs de code ldpc

Country Status (2)

Country Link
CN (1) CN102394660B (fr)
WO (1) WO2013026291A1 (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102394660B (zh) * 2011-08-24 2017-06-13 中兴通讯股份有限公司 分组交织的准循环扩展并行编码ldpc码的编码方法和编码器
CN103036577B (zh) * 2012-12-28 2015-09-30 东南大学 一种低复杂度的低密度奇偶校验ldpc码编码电路结构
CN104779961B (zh) * 2014-01-09 2019-02-26 上海数字电视国家工程研究中心有限公司 一种ldpc结构、码字及对应的编码器、解码器和编码方法
CN104821830B (zh) * 2014-02-05 2019-02-26 上海数字电视国家工程研究中心有限公司 一种ldpc结构、码字及对应的编码器、解码器和编码方法
CN105024703B (zh) * 2014-04-30 2018-12-18 上海数字电视国家工程研究中心有限公司 基于准循环的中短码长ldpc及编解码器和编码方法
CN105429645B (zh) * 2014-09-17 2019-03-08 上海数字电视国家工程研究中心有限公司 针对低码率ldpc码的校验矩阵、ldpc码字及编码方法
CA3214526A1 (fr) 2015-03-02 2016-09-09 Samsung Electronic Co., Ltd. Emetteur et procede de permutation de parite de celui-ci
KR102426419B1 (ko) * 2015-03-02 2022-07-29 삼성전자주식회사 송신 장치 및 그의 패리티 퍼뮤테이션 방법
CN107026654B (zh) * 2016-02-02 2019-06-18 中国科学院声学研究所 一种准循环多进制低密度奇偶校验码的快速频域编码方法
WO2018128559A1 (fr) 2017-01-09 2018-07-12 Huawei Technologies Co., Ltd. Code qc-ldpc pouvant être décodé efficacement
CN109150192B (zh) * 2017-06-16 2023-02-28 上海交通大学 一种ldpc码字结构及码字编码方法
CN107888334B (zh) * 2017-09-30 2020-11-10 西安空间无线电技术研究所 基于lt码与ldpc码级联的随机编、译码器及方法
CN110830048B (zh) * 2019-11-14 2021-10-12 天津大学 基于奇偶校验矩阵分解构造全分集ldpc码的纠错方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080270872A1 (en) * 2007-04-20 2008-10-30 Samsung Electronics Co. Ltd. Apparatus and method for encoding low density parity check codes in a communication system
CN101399554A (zh) * 2007-09-30 2009-04-01 华为技术有限公司 一种基于ldpc码的交织方法和解交织方法及其装置
CN102394660A (zh) * 2011-08-24 2012-03-28 中兴通讯股份有限公司 分组交织的准循环扩展并行编码ldpc码的编码方法和编码器

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101043483A (zh) * 2006-03-20 2007-09-26 松下电器产业株式会社 一种基于低密度校验码的高阶编码调制方法
EP2179620A4 (fr) * 2007-08-01 2014-05-07 Sirius Xm Radio Inc Procédé et dispositif d'entrelacement de codes de contrôle de parité faible densité (codes ldpc) sur canaux de communications mobiles par satellite
CN101242188B (zh) * 2008-03-10 2011-05-11 清华大学 基于哈密尔顿图的低密度奇偶校验码的纠错编码方法
CN101764668A (zh) * 2008-11-04 2010-06-30 西安新邮通信设备有限公司 一种网络低密度校验码的编码方法及其编码器

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080270872A1 (en) * 2007-04-20 2008-10-30 Samsung Electronics Co. Ltd. Apparatus and method for encoding low density parity check codes in a communication system
CN101399554A (zh) * 2007-09-30 2009-04-01 华为技术有限公司 一种基于ldpc码的交织方法和解交织方法及其装置
CN102394660A (zh) * 2011-08-24 2012-03-28 中兴通讯股份有限公司 分组交织的准循环扩展并行编码ldpc码的编码方法和编码器

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
OENNING, T.R. ET AL.: "A low-density generator matrix interpretation of parallel concatenated single bit parity codes", MAGNETICS, IEEE TRANSACTIONS ON., vol. 37, no. ISS. 2, March 2001 (2001-03-01), pages 737 - 741 *
YOKOKAWA TAKASHI ET AL.: "A Low Complexity and Programmable Encoder Architecture of the LDPC Codes for DVB-S2. Turbo Codes&Related Topics", 6TH INTERNATIONAL ITG-CONFERENCE ON SOURCE AND CHANNEL CODING (TURBOCODING), 2006 4TH INTERNATIONAL SYMPOSIUM ON., 3 April 2006 (2006-04-03) *

Also Published As

Publication number Publication date
CN102394660B (zh) 2017-06-13
CN102394660A (zh) 2012-03-28

Similar Documents

Publication Publication Date Title
WO2013026291A1 (fr) Procédé de codage et codeur pour codage parallèle extensible quasi cyclique à entrelacement de blocs de code ldpc
JP7372369B2 (ja) 構造的ｌｄｐｃの符号化、復号化方法および装置
EP3110009B1 (fr) Procédé de codage, procédé de décodage, dispositif de codage et dispositif de décodage pour codes de type ldpc structurés
CN102638274B (zh) 利用向量行分组的结构化ldpc设计操作发送器的设备及方法
US8631299B2 (en) Error correction encoding method and device, and communication system using the same
KR101211433B1 (ko) 낮은 복잡도를 가지는 고속의 ｑｃ－ｌｄｐｃ 부호의 부호화 장치 및 방법
CN100592639C (zh) 低密度奇偶校验编码方法、装置及奇偶校验矩阵生成方法
CN101141133A (zh) 一种结构化低密度校验码的编码方法
JP2010532129A (ja) パリティ検査行列の生成
CN104779961B (zh) 一种ldpc结构、码字及对应的编码器、解码器和编码方法
CN101488760B (zh) 一种低码率ldpc码的编码方法
CN108832936A (zh) 一种ldpc码的构造方法及系统
CN102904686B (zh) 用于编码调制的qc-ldpc码的构造方法及编码调制方法
CN102055485A (zh) 准循环低密度奇偶校验码及其修正和线性编码方法
CN105024703B (zh) 基于准循环的中短码长ldpc及编解码器和编码方法
CN105871385B (zh) 一种ldpc卷积码构造方法
WO2011144161A1 (fr) Procédé, dispositif et système de correction d'erreur sans voie de retour
CN104821830B (zh) 一种ldpc结构、码字及对应的编码器、解码器和编码方法
CN112367088A (zh) 一种基于索引矩阵的编码方法及装置
CN107204777A (zh) Ldpc码的编码方法和编码器
CN105322970B (zh) 针对下一代无线广播的ldpc码字及编码方法和编解码器
CN116054844B (zh) 校验矩阵构造方法、系统、电子设备及计算机存储介质
KR20110070730A (ko) 효율적인 ｌｄｐｃ 고속 부호화 방법 및 이를 이용하는 장치
CN101635573A (zh) 基于准循环ra码构造的多元ldpc码及其实现装置
CN109936380B (zh) 无需后向迭代的qc-ldpc编码方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12825297

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12825297

Country of ref document: EP

Kind code of ref document: A1