WO2013020853A1 - Schaltungsanordnung zum schutz gegen elektrostatische entladungen - Google Patents
Schaltungsanordnung zum schutz gegen elektrostatische entladungen Download PDFInfo
- Publication number
- WO2013020853A1 WO2013020853A1 PCT/EP2012/064887 EP2012064887W WO2013020853A1 WO 2013020853 A1 WO2013020853 A1 WO 2013020853A1 EP 2012064887 W EP2012064887 W EP 2012064887W WO 2013020853 A1 WO2013020853 A1 WO 2013020853A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- terminal
- effect transistor
- field effect
- circuit arrangement
- voltage
- Prior art date
Links
- 230000005669 field effect Effects 0.000 claims abstract description 50
- 230000009849 deactivation Effects 0.000 claims description 17
- 239000003990 capacitor Substances 0.000 claims description 7
- 230000015556 catabolic process Effects 0.000 claims description 7
- 230000000694 effects Effects 0.000 claims description 3
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 238000009795 derivation Methods 0.000 description 2
- 238000007599 discharging Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 206010012289 Dementia Diseases 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/044—Physical layout, materials not provided for elsewhere
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/0285—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
Definitions
- the invention relates to a circuit arrangement for protection against electrostatic discharges.
- An object to be solved is to specify a more reliable concept for protection against electrostatic discharges. This object is achieved by the subject matter of the independent Pa ⁇ tent threads. Embodiments and developments are the subject of the dependent claims.
- an embodiment of a circuit arrangement for protection against electrostatic discharges in addition to a discharge device which is adapted to discharge an electrostatic ⁇ cal discharge between a first terminal contact and a second terminal contact additionally comprises a compensation device which is connected between the first and second terminal contact.
- the discharge device has, for example, a discharge transistor with separate or integrated triggering.
- the compensation device is configured, for example, to monitor a voltage curve between the first and the second terminal contact and to derive overvoltages, for example due to charges in the preliminary stage of an electrostatic discharge.
- an actual electrostatic discharge is preferably discharged through the discharge device. In particular, that is Improved response of the diverter because of the derived pre-charges.
- the compensation device has a series circuit of a first
- a surge for example due to a pre-charge of the first connection contact, via the first resistor and the controlled path of Feldef ⁇ Anlagentransistors controlled to give ⁇ to the second terminal contact be directed.
- a derivative via a leakage current which is determined in particular by a value of the first resistor. For example, a value of at most one kiloohm is selected for the first resistor in order to both achieve a current limit for the field effect transistor and to enable a sufficient and reliable Ablei ⁇ tion of the overvoltage.
- the overvoltage or precharge voltage due to a pre-charge of the first terminal contact is on the order of a few tens of volts, for example. In the worst case In this case, the bias voltage can rise to just below the breakdown voltage of the ESD protection circuit.
- the capacitor of the RC series circuit acts as a Miller capacity, which causes low-frequency voltages on the first terminal contact can control the field effect transistor, while higher-frequency signals are filtered out or filtered out and thereby do not lead to a Aufberichtn the field effect transistor.
- a pre-charge voltage acts in time compared to a
- the voltage at the first terminal contact is discharged to at least the threshold voltage of the field effect transistor.
- the RC series circuit is dimensioned such that a pulse of an electrostatic discharge at the first connection contact with respect to the gate terminal of the field effect transistor is filtered out or filtered away.
- the rise time of an ESD pulse is about 20 nanoseconds.
- the capacitor and the second resistor can in this case be dimensioned such that a time constant of the RC series circuit results, which is longer than a usual rise time of an ESD pulse.
- the RC series circuit is dimensioned such that an edge of a useful signal, in particular ⁇ special with a known rate of rise, filtered out at the first terminal contact with respect to the gate terminal of the field effect transistor or filtered away.
- the first connecting terminal is an input / output port are on the pulsed useful signals übertra ⁇ gen.
- the waveform of such pulse-shaped useful signals is usually defined within certain limits, so that the rise time of a signal edge of the useful signal is at least un ⁇ dangerous known.
- the capacitor and the second resistor may be selected accordingly so that the pulsförmi ⁇ ge useful signal does not reach due to the slope of the Ga-th terminal of the field effect transistor, and thus a guard steering of the field effect transistor is excluded because of the useful signal.
- the dimensioning of the RC series circuit in particular with regard to a cut-off frequency of the low-pass filter, can be carried out in particular both with respect to an ESD pulse and with respect to a pulse-shaped useful signal, so that the desired behavior is achieved for both cases.
- the second connection contact is a reference potential connection or a supply potential connection.
- the field effect transistor is designed as an n-channel field effect transistor, in which case a discharge from the first connection contact to a second connection contact is performed, which is designed as a reference potential terminal or ground terminal.
- the field effect transistor is designed as a p-channel field effect transistor, in which case a derivation to a supply potential connection takes place.
- the field effect transistor may be suitable for low voltage applications or for high voltage applications.
- low-voltage applications involve maximum voltages at the gate terminal of the field effect transistor of 5 volts, 3.3 volts, or 1.8 volts.
- a high-voltage range as opposed to the low-voltage range can be defined by the fact that an expected operating voltage of a circuit, in particular of an integrated circuit, lies above the breakdown voltage of the gate oxide of the field-effect transistor. In the case of a high-voltage application, it may therefore be desirable to make a voltage limitation at the gate terminal of the field effect Transis ⁇ sector.
- the compensation device on a voltage limiter, which is connected between the gate terminal of the Feldef ⁇ Maschinentransistors and the second terminal contact.
- the voltage limiter is adapted to maintain a gate voltage of the field effect transistor is smaller than a gate ⁇ breakdown voltage of the field effect transistor.
- the voltage limiter has a series circuit of a plurality of diodes or transistors connected as a diode.
- Each of these diodes or each of these diode-connected transistors has a defined throughput in this case. Lassbond, resulting in the sum of the individual forward voltages as limit value at the gate terminal of the field effect transistor. Consequently, on the basis of a desired limiting voltage and a known forward voltage, the number of necessary diodes or diode-connected transistors can be determined.
- the circuit arrangement is adapted to protect an integrated circuit, in particular in the non-installed state, while in the installed state, no such protection is desired or necessary.
- the circuit arrangement has, for example, a deactivation device which is set up to connect, in particular to connect in a low-impedance manner, the gate terminal of the field effect transistor and the second terminal contact on the basis of a deactivation signal.
- a deactivation device which is set up to connect, in particular to connect in a low-impedance manner, the gate terminal of the field effect transistor and the second terminal contact on the basis of a deactivation signal.
- the deactivation device on a transistor switch that connects the gate terminal of the Feldef ⁇ Anlagentransistors to the second terminal contact.
- the compensation device is deactivated when the transistor switch is turned on.
- the transistor switch can be controlled by a bias current.
- a bias current is supplied by a bias current source, which may be part of an integrated circuit to be protected, for example.
- the bias current that drives the switching transistor is provided when a sufficient operating voltage is present.
- the transistor switch may also be controllable based on a voltage at a supply potential terminal.
- a power-on-reset, POR circuit is vorgese ⁇ hen, which supplies a corresponding digital signal in the presence of a sufficient operating voltage, indicating that egg NEN operating state of the circuit.
- the transistor switch can be controlled by this digital signal who ⁇ the to disable the compensation device.
- Show it: 1 shows an embodiment of a circuit arrangement for protection against electrostatic discharges
- FIG. 3 shows another embodiment of a circuit arrangement for protection against electrostatic discharge
- FIG. 4 shows a further embodiment of a circuit arrangement for protection against electrostatic Entla ⁇ applications.
- FIG. 1 shows an embodiment of a circuit arrangement for protection against electrostatic discharges, in which a discharge device ECL is connected between a first connection contact 10 and a second connection contact VSS.
- the first connection contact is, for example, an input / output connection
- the second connection contact VSS is, for example, a reference potential connection or ground connection.
- a compensation device 1 is switched between the first and the second connection contact 10, VSS, which has a series connection of a first resistor RS and an n-channel field effect transistor Tl.
- the first resistor is connected to a first connection to the first connection contact 10 and a second connection to the drain connection of the transistor Tl, while the source connection of the transistor Tl is connected to the second connection contact VSS.
- a connecting node K1 between the first resistor RS and the transistor T1 is connected via a series connection RC from a second resistor.
- the resistor RF and a capacitor CF connected to the gate terminal Gl of the transistor Tl.
- the discharge device ECL is set up, an electrostatic discharge, for example due to an ESD
- the discharge device has, for example, a conventional discharge transistor in field-effect or bipolar technology, or another known semiconductor element for deriving high voltages.
- a discharge device may include a corresponding triggering device, which causes the discharge element to be actuated when a corresponding voltage is applied or when a corresponding pulse at the first connection contact 10 occurs.
- a so-called pre-charge may occur at the first connection contact 10, for example by approaching a charged source, resulting in a precharge voltage at the first connection contact first terminal 10 is formed.
- a pre-charge voltage in comparison to ei ⁇ nem commonly induce fast ESD pulse to only low frequency components.
- the RC series circuit RF, CF is dimensioned such that the lower Fre ⁇ quenzanmaschine the precharge voltage via the capacitor CF, which acts as a Miller capacitance, get to the gate terminal of the Tran ⁇ transistor Tl and the controlled path of the transistor Tl open.
- the pre-charge or the pre-charge voltage can then flow away via the first resistor RS and the open-controlled transistor Tl to the second terminal contact VSS. Accordingly, the voltage at the first Connection contact reduced at least to the threshold voltage of the transistor Tl.
- the RC circuit RF, CF is dimensioned in various embodiments, in particular such that neither an ESD pulse nor an edge of a pulse-like information signal at ers ⁇ th terminal contact 10 leads to a supervisor control of the transistor Tl.
- Low-pass filter RC series circuit RF, CF selected by appropriate dimensioning of the resistor and the capacitance so that this time constant is greater or longer than an expected rise time of a clock edge or an ESD pulse. Further, in the dimensioning of the RC series circuit RF, CF, a capacitance between gate and drain of transistor Tl can be into account Untitled ⁇ .
- the RC series circuit RF, CF acts accordingly as a low-pass filter, in particular between the first connection contact and the gate connection Eq.
- Figure 2 shows a further embodiment of a circuit arrangement ⁇ for protection against electrostatic discharges, which forms in particular a development of the Darge in Figure 1 ⁇ presented embodiment.
- the compensation device 1 a voltage limiter 2, which is connected between the gate terminal Gl of the transistor Tl and the second Anschlußkon ⁇ clock VSS.
- the voltage limiter 2 has a series connection of a plurality of diode-connected transistors T2, T3, T4.
- the transistors T2, T3, T4 are designed, for example, as n-channel field-effect transistors.
- the compensation device 1 further comprises a deactivation device 3 which comprises a transistor switch T5 which connects the gate connection G1 to the second connection contact VSS.
- the transistor switch T5 is connected in a current mirror to a further transistor T6, the controlled path of which is controlled by a bias current source 4. is fed.
- the bias current source 4 is connected to a supply potential terminal VDD.
- the gate voltage at the gate terminal Gl can only increase to a value which corresponds to the sum of the forward voltages of the transistors T2, T3, T4.
- the gate voltage at the gate terminal G1 can be prevented from rising higher than an allowable gate breakdown voltage at which a gate oxide layer of the transistor T1 is damaged or destroyed.
- Such a voltage limitation may be desirable, in particular, if voltages can occur in the regular operation of the circuit arrangement or an integrated circuit to be protected which are higher than the said gate breakdown voltage of the transistor T1.
- the compensation device 1 is deactivated with respect to Abieitschreib. For example, it is desired to prevent a discharge of voltages at the first terminal contact 10 during operation of the ⁇ to protect the integrated circuit. For this purpose, a corresponding bias current is generated when to put ⁇ a corresponding supply voltage at the VDD pensionable potential terminal via the bias current source 4 which causes a guard steering of transistor T6 and because of the current mirror circuit of the transistor T5. Consequently, the compensation device 1 in the presence of an appropriate bias current is deactivated activation signal or the presence of an ent ⁇ speaking supply voltage as the de.
- the deactivation device 3 may also be advantageous, in particular, if the compensation device 2 is to be functional only in the non-installed state of a circuit to be protected. In the non-installed state, there is no deactivation signal because of the missing supply voltage, so that the compensation device 1 is active. Overvoltages due to pre-charges in the run-up to an actual ESD pulse can thus be dissipated, while after installation or during operation of the integrated circuit with the Wegungsanord ⁇ tion automatic deactivation of the compensation device 1 due to the present supply voltage.
- the series connection of the first resistor RS and the field effect transistor Tl is connected between an input / output terminal and a reference potential terminal, wherein the transistor Tl is designed as an n-channel field effect transistor.
- a p-channel field effect transistor may be used, taking into account a corresponding adjustment of the polarities.
- FIG. 4 shows an embodiment of a circuit for protection against electrostatic discharges, which is a modification of the embodiment shown in FIG.
- the field effect transistor Tl is designed as p-channel Feldef ⁇ maschinetransistor whose source terminal is connected to the supply potential terminal VDD.
- the supply potential terminal VDD simultaneously forms the second connection contact, while the first connection contact 10 in turn is formed by an input / output connection.
- the first resistor RS, the diverter ECL and the RC series circuit RF, CF correspond to the respective elements illustrated in the previously explained embodiments. Accordingly, the mode of operation and effect of the embodiment illustrated in FIG. 4 is the same or similar to the embodiment shown in FIG. 1, taking into account the changed polarity.
- the modifications and extensions shown in Figure 2 and Figure 3, in particular the voltage limiter 2 and the deactivation device 3, can also be supplemented in the embodiment shown in Figure 4.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/237,165 US9397495B2 (en) | 2011-08-05 | 2012-07-30 | Circuit arrangement for protecting against electrostatic discharges |
KR1020147004874A KR101606298B1 (ko) | 2011-08-05 | 2012-07-30 | 정전 방전 보호용 회로 장치 |
CN201280037950.0A CN103765715B (zh) | 2011-08-05 | 2012-07-30 | 用于防止静电放电的电路装置 |
JP2014523299A JP5771330B2 (ja) | 2011-08-05 | 2012-07-30 | 静電気放電保護用回路装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102011109596.2 | 2011-08-05 | ||
DE102011109596.2A DE102011109596B4 (de) | 2011-08-05 | 2011-08-05 | Schaltungsanordnung zum Schutz gegen elektrostatische Entladungen |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2013020853A1 true WO2013020853A1 (de) | 2013-02-14 |
Family
ID=46724356
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2012/064887 WO2013020853A1 (de) | 2011-08-05 | 2012-07-30 | Schaltungsanordnung zum schutz gegen elektrostatische entladungen |
Country Status (6)
Country | Link |
---|---|
US (1) | US9397495B2 (de) |
JP (1) | JP5771330B2 (de) |
KR (1) | KR101606298B1 (de) |
CN (1) | CN103765715B (de) |
DE (1) | DE102011109596B4 (de) |
WO (1) | WO2013020853A1 (de) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105449654B (zh) * | 2014-08-27 | 2018-09-04 | 瑞昱半导体股份有限公司 | 静电放电保护电路 |
US9954356B2 (en) | 2015-05-15 | 2018-04-24 | Analog Devices, Inc. | Electrostatic discharge protection circuits for radio frequency communication systems |
KR102397866B1 (ko) * | 2015-12-28 | 2022-05-12 | 엘지디스플레이 주식회사 | 정전기 방전회로 및 이를 포함하는 표시장치 |
DE102017203001A1 (de) * | 2017-02-24 | 2018-08-30 | Robert Bosch Gmbh | Schaltventil, Sensorbaugruppe oder Aktorbaugruppe mit Schutzbeschaltung |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US20060250732A1 (en) * | 2005-05-06 | 2006-11-09 | Peachey Nathaniel M | Transient pulse, substrate-triggered biCMOS rail clamp for ESD abatement |
US20090128969A1 (en) * | 2007-11-21 | 2009-05-21 | Philippe Deval | Adaptive electrostatic discharge (esd) protection of device interface for local interconnect network (lin) bus and the like |
DE102008001368A1 (de) * | 2008-04-24 | 2009-10-29 | Robert Bosch Gmbh | Flächenoptimierte ESD-Schutzschaltung |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS58147068A (ja) * | 1982-02-24 | 1983-09-01 | Mitsubishi Electric Corp | 入力保護回路 |
US5255146A (en) * | 1991-08-29 | 1993-10-19 | National Semiconductor Corporation | Electrostatic discharge detection and clamp control circuit |
US5946177A (en) | 1998-08-17 | 1999-08-31 | Motorola, Inc. | Circuit for electrostatic discharge protection |
TW410459B (en) * | 1999-01-04 | 2000-11-01 | Taiwan Semiconductor Mfg | Gate-coupled electrostatic discharge protection circuit without transient leakage |
US6249410B1 (en) * | 1999-08-23 | 2001-06-19 | Taiwan Semiconductor Manufacturing Company | ESD protection circuit without overstress gate-driven effect |
US6844597B2 (en) | 2003-02-10 | 2005-01-18 | Freescale Semiconductor, Inc. | Low voltage NMOS-based electrostatic discharge clamp |
DE102004007241A1 (de) | 2004-02-13 | 2005-09-01 | Austriamicrosystems Ag | Schaltungsanordnung und Verfahren zum Schutz einer integrierten Halbleiterschaltung |
KR100914790B1 (ko) | 2004-02-13 | 2009-09-02 | 오스트리아마이크로시스템즈 아게 | 반도체 집적 회로를 보호하기 위한 회로 장치 및 보호 방법 |
US7212387B2 (en) | 2004-09-17 | 2007-05-01 | Texas Instruments Incorporated | Electrostatic discharge protection device including precharge reduction |
US20070024772A1 (en) | 2005-07-28 | 2007-02-01 | Childers Winthrop D | Display with sub-region backlighting |
JP2007096150A (ja) * | 2005-09-30 | 2007-04-12 | Toshiba Corp | Esd保護回路 |
WO2007124079A2 (en) * | 2006-04-21 | 2007-11-01 | Sarnoff Corporation | Esd clamp control by detection of power state |
JP2008251755A (ja) * | 2007-03-30 | 2008-10-16 | Eudyna Devices Inc | 半導体装置 |
JP2009152484A (ja) | 2007-12-21 | 2009-07-09 | Fujifilm Corp | 電源保護回路及び集積回路 |
US8958184B2 (en) * | 2010-12-28 | 2015-02-17 | Infineon Technologies Ag | ESD protection devices and methods |
-
2011
- 2011-08-05 DE DE102011109596.2A patent/DE102011109596B4/de not_active Expired - Fee Related
-
2012
- 2012-07-30 WO PCT/EP2012/064887 patent/WO2013020853A1/de active Application Filing
- 2012-07-30 KR KR1020147004874A patent/KR101606298B1/ko active IP Right Grant
- 2012-07-30 US US14/237,165 patent/US9397495B2/en active Active
- 2012-07-30 CN CN201280037950.0A patent/CN103765715B/zh not_active Expired - Fee Related
- 2012-07-30 JP JP2014523299A patent/JP5771330B2/ja not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060250732A1 (en) * | 2005-05-06 | 2006-11-09 | Peachey Nathaniel M | Transient pulse, substrate-triggered biCMOS rail clamp for ESD abatement |
US20090128969A1 (en) * | 2007-11-21 | 2009-05-21 | Philippe Deval | Adaptive electrostatic discharge (esd) protection of device interface for local interconnect network (lin) bus and the like |
DE102008001368A1 (de) * | 2008-04-24 | 2009-10-29 | Robert Bosch Gmbh | Flächenoptimierte ESD-Schutzschaltung |
Also Published As
Publication number | Publication date |
---|---|
CN103765715B (zh) | 2016-08-24 |
KR101606298B1 (ko) | 2016-04-01 |
US20140240877A1 (en) | 2014-08-28 |
KR20140040279A (ko) | 2014-04-02 |
JP2014523145A (ja) | 2014-09-08 |
CN103765715A (zh) | 2014-04-30 |
JP5771330B2 (ja) | 2015-08-26 |
DE102011109596A1 (de) | 2013-02-07 |
DE102011109596B4 (de) | 2018-05-09 |
US9397495B2 (en) | 2016-07-19 |
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