JP5771330B2 - 静電気放電保護用回路装置 - Google Patents
静電気放電保護用回路装置 Download PDFInfo
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- JP5771330B2 JP5771330B2 JP2014523299A JP2014523299A JP5771330B2 JP 5771330 B2 JP5771330 B2 JP 5771330B2 JP 2014523299 A JP2014523299 A JP 2014523299A JP 2014523299 A JP2014523299 A JP 2014523299A JP 5771330 B2 JP5771330 B2 JP 5771330B2
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- circuit device
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- 230000005669 field effect Effects 0.000 claims description 54
- 239000003990 capacitor Substances 0.000 claims description 11
- 230000015556 catabolic process Effects 0.000 claims description 7
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/044—Physical layout, materials not provided for elsewhere
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
- H01L27/0285—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Emergency Protection Circuit Devices (AREA)
Description
Claims (13)
- 第1の接続端子(IO)と第2の接続端子(VDD,VSS)との間での静電気放電のバイパスに適したバイパス装置(ECL)と、
補償装置(1)であって、第1の抵抗(RS)および電界効果トランジスタ(T1)の直列回路が前記第1の接続端子(IO)と前記第2の接続端子(VDD,VSS)との間に接続され、前記第1の抵抗(RS)と前記電界効果トランジスタ(T1)との間の接続ノード(K1)がRC直列回路(RF,CF)を介して前記電界効果トランジスタ(T1)のゲート端子(G1)に接続され、前記RC直列回路(RF,CF)は第2の抵抗(RF)とコンデンサ(CF)とを有し、前記接続ノード(K1)と前記ゲート端子(G1)との間でローパスフィルタとして作用し、前記RC直列回路(RF,CF)の時定数が前記第1の接続端子(IO)での静電気放電で予測されるパルスの立ち上がり時間より長くなるようにスケーリングされる補償装置と、
を備えることを特徴とする静電気放電保護用の回路装置。 - 請求項1に記載の回路装置において、
前記補償回路(1)は、電圧リミッタ(2)を備え、
前記電圧リミッタは、前記電界効果トランジスタ(T1)の前記ゲート端子(G1)と前記第2の接続端子(VDD,VSS)との間に接続され、前記電界効果トランジスタ(T1)のゲート電圧を前記電界効果トランジスタ(T1)のゲート絶縁破壊電圧より小さく維持することを特徴とする回路装置。 - 請求項2に記載の回路装置において、
前記電圧リミッタ(2)は複数の、ダイオードとして接続されたトランジスタ(T2,T3,T4)を備えることを特徴とする回路装置。 - 請求項1乃至3のいずれか1項に記載の回路装置において、
前記回路装置は、停止装置(3)を備え、
前記停止装置は、停止信号に基づいて、前記電界効果トランジスタ(T1)の前記ゲート端子(G1)と前記第2の接続端子(VDD,VSS)とを接続することを特徴とする回路装置。 - 請求項4に記載の回路装置において、
前記停止装置(3)は、前記電界効果トランジスタ(T1)の前記ゲート端子(G1)を前記第2接続端子(VDD,VSS)に接続するトランジスタスイッチ(T5)を備えることを特徴とする回路装置。 - 請求項5に記載の回路装置において、
前記トランジスタスイッチ(T5)は、バイアス電流によって制御可能であることを特徴とする回路装置。 - 請求項5または6に記載の回路装置において、
前記トランジスタスイッチ(T5)は、電源電位端子(VDD)における電圧に基づいて制御可能であることを特徴とする回路装置。 - 請求項1乃至7のいずれか1項に記載の回路装置において、
前記第1の接続端子(IO)における静電気放電のパルスが、前記電界効果トランジスタ(T1)の前記ゲート端子(G1)に対してフィルタ除去されるように、前記RC直列回路(RF,CF)はスケーリングされていることを特徴とする回路装置。 - 請求項1乃至8のいずれか1項に記載の回路装置において、
前記第1の接続端子(IO)における有効信号のエッジが、前記電界効果トランジスタ(T1)の前記ゲート端子(G1)に対してフィルタ除去されるように、前記RC直列回路(RF,CF)はスケーリングされていることを特徴とする回路装置。 - 請求項1乃至9のいずれか1項に記載の回路装置において、
前記RC直列回路(RF,CF)の時定数が前記第1の接続端子(IO)での有効信号のエッジの立ち上がり時間より長くなるようにスケーリングされていることを特徴とする回路装置。 - 請求項1乃至10のいずれか1項に記載の回路装置において、
前記第1の接続端子(IO)は、入力/出力端子であり、前記第2の接続端子は基準電位端子(VSS)または電源電位端子(VDD)であることを特徴とする回路装置。 - 請求項1乃至11のいずれか1項に記載の回路装置おいて、
前記第1の抵抗(RS)は、最大で1kΩの値を有することを特徴とする回路装置。 - 請求項1乃至12のいずれか1項に記載の回路装置おいて、
前記予測されるパルスの立ち上がり時間は、20nsであることを特徴とする回路装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102011109596.2A DE102011109596B4 (de) | 2011-08-05 | 2011-08-05 | Schaltungsanordnung zum Schutz gegen elektrostatische Entladungen |
DE102011109596.2 | 2011-08-05 | ||
PCT/EP2012/064887 WO2013020853A1 (de) | 2011-08-05 | 2012-07-30 | Schaltungsanordnung zum schutz gegen elektrostatische entladungen |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014523145A JP2014523145A (ja) | 2014-09-08 |
JP5771330B2 true JP5771330B2 (ja) | 2015-08-26 |
Family
ID=46724356
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014523299A Expired - Fee Related JP5771330B2 (ja) | 2011-08-05 | 2012-07-30 | 静電気放電保護用回路装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US9397495B2 (ja) |
JP (1) | JP5771330B2 (ja) |
KR (1) | KR101606298B1 (ja) |
CN (1) | CN103765715B (ja) |
DE (1) | DE102011109596B4 (ja) |
WO (1) | WO2013020853A1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105449654B (zh) * | 2014-08-27 | 2018-09-04 | 瑞昱半导体股份有限公司 | 静电放电保护电路 |
US9831666B2 (en) | 2015-05-15 | 2017-11-28 | Analog Devices, Inc. | Apparatus and methods for electrostatic discharge protection of radio frequency interfaces |
KR102397866B1 (ko) * | 2015-12-28 | 2022-05-12 | 엘지디스플레이 주식회사 | 정전기 방전회로 및 이를 포함하는 표시장치 |
DE102017203001A1 (de) * | 2017-02-24 | 2018-08-30 | Robert Bosch Gmbh | Schaltventil, Sensorbaugruppe oder Aktorbaugruppe mit Schutzbeschaltung |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58147068A (ja) | 1982-02-24 | 1983-09-01 | Mitsubishi Electric Corp | 入力保護回路 |
US5255146A (en) * | 1991-08-29 | 1993-10-19 | National Semiconductor Corporation | Electrostatic discharge detection and clamp control circuit |
US5946177A (en) * | 1998-08-17 | 1999-08-31 | Motorola, Inc. | Circuit for electrostatic discharge protection |
TW410459B (en) * | 1999-01-04 | 2000-11-01 | Taiwan Semiconductor Mfg | Gate-coupled electrostatic discharge protection circuit without transient leakage |
US6249410B1 (en) * | 1999-08-23 | 2001-06-19 | Taiwan Semiconductor Manufacturing Company | ESD protection circuit without overstress gate-driven effect |
US6844597B2 (en) | 2003-02-10 | 2005-01-18 | Freescale Semiconductor, Inc. | Low voltage NMOS-based electrostatic discharge clamp |
WO2005078798A2 (de) | 2004-02-13 | 2005-08-25 | Austriamicrosystems Ag | Schaltungsanordnung und verfahren zum schutz einer integrierten halbleiterschaltung |
DE102004007241A1 (de) | 2004-02-13 | 2005-09-01 | Austriamicrosystems Ag | Schaltungsanordnung und Verfahren zum Schutz einer integrierten Halbleiterschaltung |
US7212387B2 (en) | 2004-09-17 | 2007-05-01 | Texas Instruments Incorporated | Electrostatic discharge protection device including precharge reduction |
US20060250732A1 (en) * | 2005-05-06 | 2006-11-09 | Peachey Nathaniel M | Transient pulse, substrate-triggered biCMOS rail clamp for ESD abatement |
US20070024772A1 (en) | 2005-07-28 | 2007-02-01 | Childers Winthrop D | Display with sub-region backlighting |
JP2007096150A (ja) | 2005-09-30 | 2007-04-12 | Toshiba Corp | Esd保護回路 |
WO2007124079A2 (en) * | 2006-04-21 | 2007-11-01 | Sarnoff Corporation | Esd clamp control by detection of power state |
JP2008251755A (ja) | 2007-03-30 | 2008-10-16 | Eudyna Devices Inc | 半導体装置 |
US7876540B2 (en) * | 2007-11-21 | 2011-01-25 | Microchip Technology Incorporated | Adaptive electrostatic discharge (ESD) protection of device interface for local interconnect network (LIN) bus and the like |
JP2009152484A (ja) | 2007-12-21 | 2009-07-09 | Fujifilm Corp | 電源保護回路及び集積回路 |
DE102008001368A1 (de) | 2008-04-24 | 2009-10-29 | Robert Bosch Gmbh | Flächenoptimierte ESD-Schutzschaltung |
US8958184B2 (en) * | 2010-12-28 | 2015-02-17 | Infineon Technologies Ag | ESD protection devices and methods |
-
2011
- 2011-08-05 DE DE102011109596.2A patent/DE102011109596B4/de not_active Expired - Fee Related
-
2012
- 2012-07-30 KR KR1020147004874A patent/KR101606298B1/ko active IP Right Grant
- 2012-07-30 US US14/237,165 patent/US9397495B2/en active Active
- 2012-07-30 JP JP2014523299A patent/JP5771330B2/ja not_active Expired - Fee Related
- 2012-07-30 WO PCT/EP2012/064887 patent/WO2013020853A1/de active Application Filing
- 2012-07-30 CN CN201280037950.0A patent/CN103765715B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
WO2013020853A1 (de) | 2013-02-14 |
DE102011109596B4 (de) | 2018-05-09 |
US20140240877A1 (en) | 2014-08-28 |
DE102011109596A1 (de) | 2013-02-07 |
JP2014523145A (ja) | 2014-09-08 |
KR101606298B1 (ko) | 2016-04-01 |
US9397495B2 (en) | 2016-07-19 |
CN103765715B (zh) | 2016-08-24 |
CN103765715A (zh) | 2014-04-30 |
KR20140040279A (ko) | 2014-04-02 |
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