WO2013007066A1 - 薄膜晶体管的制造方法以及薄膜晶体管 - Google Patents

薄膜晶体管的制造方法以及薄膜晶体管 Download PDF

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WO2013007066A1
WO2013007066A1 PCT/CN2011/080158 CN2011080158W WO2013007066A1 WO 2013007066 A1 WO2013007066 A1 WO 2013007066A1 CN 2011080158 W CN2011080158 W CN 2011080158W WO 2013007066 A1 WO2013007066 A1 WO 2013007066A1
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Prior art keywords
semiconductor layer
amorphous semiconductor
insulating layer
thin film
film transistor
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English (en)
French (fr)
Inventor
覃事建
贺成明
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/376,970 priority Critical patent/US8629507B2/en
Publication of WO2013007066A1 publication Critical patent/WO2013007066A1/zh
Priority to US14/071,284 priority patent/US8829523B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes

Definitions

  • the present invention relates to the field of liquid crystal display manufacturing, and more particularly to a method of fabricating a thin film transistor and a thin film transistor.
  • OLEDs Organic light-emitting diodes
  • OLED screens are usually driven by amorphous silicon thin film transistors, while amorphous silicon thin film transistor switching devices have low electron mobility and cannot meet the current driving mode of OLED panels. Therefore, it is particularly important to convert amorphous silicon into polycrystalline silicon and improve the electron mobility to improve the electrical characteristics of the TFT switching device.
  • a disadvantage of the prior art is that the thin film transistor is directly formed on the surface of the transparent substrate, and a multilayer stacked structure needs to be grown, and an electrical connection structure between the thin film transistor and the external component is also required, and the process is cumbersome and costly.
  • the invention provides a method for manufacturing a thin film transistor and a thin film transistor, which can save process cost.
  • the present invention provides a method of fabricating a thin film transistor, comprising the steps of: providing a transparent substrate; forming a gate and a data line on a surface of the transparent substrate; forming a surface covering the gate and the surface on the surface of the transparent substrate a first insulating layer of the data line; an amorphous semiconductor layer is formed on a surface of the first insulating layer corresponding to the gate; and a through hole is formed in a surface of the first insulating layer corresponding to the data line Forming a conductive layer covering the amorphous semiconductor layer and the via hole on a surface of the first insulating layer; removing a portion of the conductive layer corresponding to the gate to divide a conductive layer, thereby forming a thin film transistor a source electrode and a drain electrode; forming a second insulating layer covering the amorphous semiconductor layer, the via hole, and the source electrode and the drain electrode on a surface of the first insulating layer; and irradiating the amorphous region
  • the present invention further provides a thin film transistor comprising: a transparent substrate; a gate and a data line, the gate and the data line being disposed on a surface of the transparent substrate; a first insulating layer, the first insulating layer Covering the gate and the data line; an amorphous semiconductor layer disposed on a surface of the first insulating layer corresponding to the gate; a through hole, the through hole being disposed at the a region of the first insulating layer corresponding to the data line; a source electrode and a drain electrode, the source electrode and the drain electrode being disposed at both ends of the amorphous semiconductor layer, a source electrode and a drain One of the electrodes is connected to the data line through the through hole; and a second insulating layer on a surface of the first insulating layer covering the amorphous semiconductor layer, the via hole, and the source Electrode and drain electrodes.
  • the present invention still further provides a thin film transistor comprising: a transparent substrate; a gate and a data line, the gate and the data line being disposed on a surface of the transparent substrate; a first insulating layer, the first insulating a layer covering the gate and the data line; an amorphous semiconductor layer disposed on a surface of the first insulating layer corresponding to the gate, the amorphous semiconductor layer including a stacked arrangement a first amorphous semiconductor layer and a second amorphous semiconductor layer of the same conductivity type, the first amorphous semiconductor layer is bonded to the first insulating layer, and the conductivity of the second amorphous semiconductor layer is higher than Conductivity of the first amorphous semiconductor layer; a via hole disposed in a region of the surface of the first insulating layer corresponding to the data line; a source electrode and a drain electrode, the source electrode And a drain electrode disposed at both ends of the amorphous semiconductor layer, one of the source electrode and the drain electrode being connected to the
  • the source electrode or the drain electrode of the thin film transistor is directly electrically connected to the data line during the formation process, which saves process cost.
  • the source electrode and the drain electrode are also prepared by using a polysilicon material instead of the metal material in the prior art, which simplifies the process steps, thereby further saving process cost.
  • 1 is a flow chart showing the steps of the method of the specific embodiment of the present invention.
  • FIGS. 2A to 2J are schematic views showing the process of the method of the embodiment of the present invention.
  • step S100 providing a transparent substrate
  • step S110 forming a gate and a data line on the surface of the transparent substrate
  • step S120 a surface of the transparent substrate is formed with a first insulating layer covering the gate and the data line
  • step S130 an amorphous semiconductor layer is formed on a surface of the first insulating layer corresponding to the gate, wherein The amorphous semiconductor layer includes a first amorphous semiconductor layer and a second amorphous semiconductor layer, and a second amorphous semiconductor layer is stacked on the first amorphous semiconductor layer
  • step S140 on the surface of the first insulating layer a region corresponding to the data line forms a via hole
  • step S150 a conductive layer covering the amorphous semiconductor layer and the via hole is formed on a surface of the first insulating layer
  • step S160 the conductive layer and the second layer are formed a
  • FIGS. 2A to 2J are schematic views showing the process of the method of the embodiment of the present invention.
  • a transparent substrate 200 is provided.
  • the material of the transparent substrate 200 may be any common material including glass.
  • a gate 210 and a data line 230 are formed on the surface of the transparent substrate 200.
  • the material of the gate 210 and the data line 230 may be a conductive material such as polysilicon or metal.
  • the gate electrode 210 and the data line 230 are simultaneously fabricated in this step, and in the subsequent step, by process integration, the data line 230 and the source electrode or the drain electrode of the thin film transistor are formed while forming the thin film transistor. Electrical connections to save process steps.
  • a first insulating layer 251 covering the gate electrode 210 and the data line 230 is formed on the surface of the transparent substrate 200.
  • the material of the first insulating layer 251 may be silicon oxide, silicon nitride or other insulating material, and the forming method may be any common processing method such as chemical vapor deposition or physical vapor deposition.
  • an amorphous semiconductor layer 270 is formed on a surface of the first insulating layer 251 corresponding to the gate electrode 210.
  • the material of the amorphous semiconductor layer 270 may be, for example, amorphous silicon, or other common semiconductor materials such as gallium arsenide or germanium silicon.
  • the formation method may be first to epitaxially or deposit a continuous amorphous semiconductor layer on the surface of the first insulating layer 251, and to retain a specified region by photolithographic etching to form the amorphous semiconductor layer 270 shown in FIG. 2D.
  • the doping concentration of the amorphous semiconductor layer 270 can be adjusted by controlling the amount of dopant supply in the epitaxial or deposition process.
  • the amorphous semiconductor layer 270 further includes a first amorphous semiconductor layer 271 and a second amorphous semiconductor layer 272 of the same conductivity type stacked in a stack, the first amorphous semiconductor layer 271 Bonding with the first insulating layer 251, the second amorphous semiconductor layer 272 is exposed to the surface in this step, and is bonded to the source electrode and the drain electrode in a subsequent step.
  • the electrical conductivity of the second amorphous semiconductor layer 272 is higher than the electrical conductivity of the first amorphous semiconductor layer 271.
  • High conductivity means high doping concentration, such as high doping concentration of N-type doped amorphous silicon, while high doping concentration facilitates good ohmic contact of homologous electrode and drain electrode, low doping concentration
  • the semiconductor layer is more susceptible to gate control to change the conductivity type. Therefore, the present embodiment selectively further decomposes the amorphous semiconductor layer 270 into a low-doped first amorphous semiconductor layer 271 and a highly doped second amorphous semiconductor. Layer 272.
  • a via hole 231 is formed in a region of the surface of the first insulating layer 251 corresponding to the data line 230.
  • the step of forming the via hole 231 may be a method of etching by photolithography.
  • the via 231 functions to form an electrical connection for the subsequent data line 230 with the source or drain electrode.
  • a conductive layer 290 covering the amorphous semiconductor layer 270 and the via 231 is formed on the surface of the first insulating layer 251.
  • the material of the conductive layer 290 may be, for example, one selected from the group consisting of indium tin oxide (ITO) and indium zinc oxide (IZO), and the formation method may be, for example, a spin coating method or a spray coating method.
  • the conductive layer 290 covers the through hole 231 and is bonded to the data line 230 under the through hole 231 to realize electrical connection.
  • step S160 a portion of the conductive layer 290 and the second amorphous semiconductor layer 272 corresponding to the gate 210 is removed to divide the conductive layer 290 and the second amorphous semiconductor layer 272, Thereby, the source electrode 291 and the drain electrode 292 of the thin film transistor are formed, and the first amorphous semiconductor layer 271 at the corresponding position is thinned.
  • the positions of the source electrode 291 and the drain electrode 292 may be interchanged.
  • the process of dividing the conductive layer 290 and the second amorphous semiconductor layer 272, and thinning the first amorphous semiconductor layer 271 can be realized by photolithographic etching. Since the conductive layer 290 has been electrically connected to the data line 230 in the foregoing steps, the source electrode 291 formed in the present embodiment does not need to additionally fabricate an electrical connection structure with the data line 230.
  • a second insulating layer 252 covering the amorphous semiconductor layer 270, the via 231, and the source electrode 291 and the drain electrode 292 is formed on the surface of the first insulating layer 251.
  • the material of the second insulating layer 252 may be any insulating material including silicon oxide and silicon nitride, and functions to protect the covered amorphous semiconductor layer 270, the via 231, and the source electrode 291 and the drain electrode 292. .
  • step S180 the portion of the second insulating layer 252 between the source electrode 291 and the drain electrode 292 is removed. This step is used to form a pixel electrode pattern.
  • the amorphous semiconductor layer 270 is irradiated with a laser to increase the order of the lattice arrangement of the amorphous semiconductor layer 270.
  • the amorphous semiconductor layer 270 is annealed by laser irradiation, and is converted from an amorphous material to a polycrystalline material.
  • the laser power is sufficiently large and the irradiation time is long enough, the amorphous material can be converted into a polycrystalline material.
  • Polycrystalline materials have better lattice order, so they have higher carrier mobility and can improve the electrical performance of thin film transistors.
  • the laser light is preferably incident from the side of the second insulating layer 252, and the wavelength of the laser light should be able to penetrate the second insulating layer 252 and the conductive layer 290.
  • the material of the second insulating layer 252 is silicon nitride or silicon oxide
  • the material of the conductive layer 290 is ITO or IZO
  • the laser light in the visible light band and the infrared band is transparent to these materials.
  • the thin film transistor obtained after the above steps are completed includes the following structure: a transparent substrate 200; a gate 210 and a data line 230, and a gate 210 and a data line 230 are disposed on the surface of the transparent substrate 200;
  • the insulating layer 251, the first insulating layer 251 covers the gate electrode 210 and the data line 230, and the amorphous semiconductor layer 270 includes a first amorphous semiconductor layer 271 and a second amorphous semiconductor layer 272, and the amorphous semiconductor layer 270 a region corresponding to the gate 210 on the surface of the first insulating layer 251; a via 231 disposed in a region of the surface of the first insulating layer 251 corresponding to the data line 230; a source electrode 291 and a drain The electrode 292, the source electrode 291 and the drain electrode 292 are disposed at both ends of the amorphous semiconductor layer 270, and one of the source electrode 291 and the drain electrode 292 is connected
  • the second insulating layer 252 is located at the source electrode 291.
  • the portion between the drain electrode 292 and the drain electrode 292 is hollowed out
  • the second amorphous semiconductor layer 272 between the source electrode 291 and the drain electrode 292 is hollowed out, and the thickness of the portion of the first amorphous semiconductor layer 271 between the source electrode 291 and the drain electrode 292 is smaller than the first portion.

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  • Thin Film Transistor (AREA)

Abstract

本发明提供了薄膜晶体管的制造方法以及薄膜晶体管，通过在薄膜晶体管的数据线表面设置通孔，使薄膜晶体管的源极电极或者漏极电极在形成过程中直接同数据线电学连接，节省了工艺成本。进一步地，薄膜晶体管的源极电极和漏极电极也采用多晶硅材料制备，而非现有技术中的金属材料，简化了工艺步骤，从而进一步节省了工艺成本。

Description

薄膜晶体管的制造方法以及薄膜晶体管 技术领域
本发明涉及液晶显示器制造领域，尤其涉及薄膜晶体管的制造方法以及薄膜晶体管。
 背景技术
有机发光二极管（OLED）越来越受到人们的关注。OLED屏通常采用非晶硅薄膜晶体管作为驱动，而非晶硅薄膜晶体管开关器件电子迁移率低，不能满足OLED屏的电流驱动方式。因此将非晶硅转换为多晶硅，提高电子迁移率来改善TFT开关器件的电特性显得尤为重要。
现有技术的缺点在于，薄膜晶体管直接形成于透明衬底表面，需要生长多层堆叠结构，并且还需要制作薄膜晶体管与外部组件的电学连接结构，工艺过程繁琐，成本较高。
 技术问题
本发明提供一种薄膜晶体管的制造方法以及薄膜晶体管，能够节省工艺成本。
 技术解决方案
本发明提供了一种薄膜晶体管的制造方法，包括如下步骤：提供透明衬底；在所述透明衬底表面形成栅极和数据线；在所述透明衬底表面形成覆盖所述栅极和所述数据线的第一绝缘层；在所述第一绝缘层表面与所述栅极对应的区域形成非晶半导体层；在所述第一绝缘层表面与所述数据线对应的区域形成通孔；在所述第一绝缘层表面形成覆盖所述非晶半导体层和所述通孔的导电层；将所述导电层与所述栅极对应的部分移除以分割导电层，从而形成薄膜晶体管的源极电极和漏极电极；在所述第一绝缘层表面形成覆盖所述非晶半导体层、通孔以及源极电极和漏极电极的第二绝缘层；以及采用激光照射所述非晶半导体层，以增加非晶半导体层晶格排列的有序度。
本发明进一步提供了一种薄膜晶体管，包括：透明衬底；栅极和数据线，所述栅极和数据线设置在所述透明衬底的表面；第一绝缘层，所述第一绝缘层覆盖所述栅极和所述数据线；非晶半导体层，所述非晶半导体层设置在所述第一绝缘层表面与所述栅极对应的区域；通孔，所述通孔设置在所述第一绝缘层表面与所述数据线对应的区域；源极电极和漏极电极，所述源极电极和漏极电极设置在所述非晶半导体层的两端，源极电极和漏极电极之一通过所述通孔连接至所述数据线；以及第二绝缘层，所述第二绝缘层在所述第一绝缘层表面，并覆盖所述非晶半导体层、通孔以及源极电极和漏极电极。
本发明还进一步提供了一种薄膜晶体管，包括：透明衬底；栅极和数据线，所述栅极和数据线设置在所述透明衬底的表面；第一绝缘层，所述第一绝缘层覆盖所述栅极和所述数据线；非晶半导体层，所述非晶半导体层设置在所述第一绝缘层表面与所述栅极对应的区域，所述非晶半导体层包括堆叠设置的导电类型相同的第一非晶半导体层和第二非晶半导体层，所述第一非晶半导体层与所述第一绝缘层贴合，所述第二非晶半导体层的电导率高于所述第一非晶半导体层的电导率；通孔，所述通孔设置在所述第一绝缘层表面与所述数据线对应的区域；源极电极和漏极电极，所述源极电极和漏极电极设置在所述非晶半导体层的两端，源极电极和漏极电极之一通过所述通孔连接至所述数据线，所述第二非晶半导体层与所述源极电极和漏极电极贴合，所述源极电极和漏极之间的所述第二非晶半导体层是镂空的；以及第二绝缘层，所述第二绝缘层在所述第一绝缘层表面，并覆盖所述非晶半导体层、通孔以及源极电极和漏极电极，所述第二绝缘层位于所述源极电极和漏极电极之间部分是镂空的。
 有益效果
通过在数据线表面设置通孔，使薄膜晶体管的源极电极或者漏极电极在形成过程中直接同数据线电学连接，节省了工艺成本。进一步地，源极电极和漏极电极也采用多晶硅材料制备，而非现有技术中的金属材料，简化了工艺步骤，从而进一步节省了工艺成本。
 附图说明
附图1所示是本发明具体实施方式所述方法的步骤流程图。
附图2A至附图2J所示是本发明具体实施方式所述方法的工艺示意图。
 本发明的最佳实施方式
下面结合附图对本发明提供的薄膜晶体管的制造方法以及薄膜晶体管的具体实施方式做详细说明。
为了让本发明的目的、特征及优点能更明显易懂，下文特举较佳实施例，并配合说明书所附图式，做详细的说明。本发明说明书提供不同的实施例来说明本发明不同实施方式的技术特征。其中，实施例中的各组件的配置是为清楚说明本发明揭示的内容，并非用以限制本发明。且不同实施例中图式标号的部分重复，是为了简化说明，并非意指不同实施例之间的关联性。
附图1所示是本发明具体实施方式所述方法的步骤流程图，包括：步骤S100，提供透明衬底；步骤S110，在所述透明衬底表面形成栅极和数据线；步骤S120，在所述透明衬底表面形成覆盖所述栅极和所述数据线的第一绝缘层；步骤S130，在所述第一绝缘层表面与所述栅极对应的区域形成非晶半导体层，其中，所述非晶半导体层包括第一非晶半导体层和第二非晶半导体层，第二非晶半导体层堆叠于第一非晶半导体层之上；步骤S140，在所述第一绝缘层表面与所述数据线对应的区域形成通孔；步骤S150，在所述第一绝缘层表面形成覆盖所述非晶半导体层和所述通孔的导电层；步骤S160，将所述导电层和第二非晶半导体层与所述栅极对应的部分移除以分割导电层和第二非晶半导体层，从而形成薄膜晶体管的源极电极和漏极电极，并减薄对应位置的第一非晶半导体层；步骤S170，在所述第一绝缘层表面形成覆盖所述非晶半导体层、通孔以及源极电极和漏极电极的第二绝缘层；步骤S180，除去所述第二绝缘层位于所述源极电极和漏极电极之间部分；步骤S190，采用激光照射所述非晶半导体层，以增加非晶半导体层晶格排列的有序度。
附图2A至附图2J所示是本发明具体实施方式所述方法的工艺示意图。
附图2A所示，参考步骤S100，提供透明衬底200。所述透明衬底200的材料可以是包括玻璃在内的任意一种常见材料。
附图2B所示，参考步骤S110，在所述透明衬底200的表面形成栅极210和数据线230。栅极210和数据线230的材料可以是多晶硅或者金属等导电材料。本具体实施方式在此步骤中同时制作了栅极210和数据线230，并在后续步骤中通过工艺整合，在形成薄膜晶体管的同时形成数据线230和薄膜晶体管源极电极或者漏极电极之间的电学连接，以节省工艺步骤。
附图2C所示，参考步骤S120，在所述透明衬底200表面形成覆盖所述栅极210和所述数据线230的第一绝缘层251。所述第一绝缘层251的材料可以是氧化硅、氮化硅或者其他绝缘材料，形成方法可以是化学气相沉积或者物理气相沉积等任何一种常见工艺方法。
附图2D所示，参考步骤S130，在所述第一绝缘层251表面与所述栅极210对应的区域形成非晶半导体层270。所述非晶半导体层270的材料例如可以是非晶硅，也可以是其他常见的半导体材料例如砷化镓或者锗硅等。形成方法可以是首先在第一绝缘层251表面外延或者沉积连续的非晶半导体层，并通过光刻腐蚀的方法保留指定区域而形成附图2D所示的非晶半导体层270。通过控制外延或者沉积工艺中的掺杂物质供给量可以调节非晶半导体层270的掺杂浓度。
继续参考附图2D，本实施方式中，非晶半导体层270进一步包括堆叠设置的导电类型相同的第一非晶半导体层271和第二非晶半导体层272，所述第一非晶半导体层271与所述第一绝缘层251贴合，所述第二非晶半导体层272在本步骤中暴露在表面，并在后续步骤中与所述源极电极和漏极电极贴合。所述第二非晶半导体层272的电导率高于所述第一非晶半导体层271的电导率。高电导率意味着高掺杂浓度，例如高掺杂浓度的N型掺杂非晶硅，而高掺杂浓度有利于同源极电极和漏极电极形成良好的欧姆接触，低掺杂浓度的半导体层则更容易受栅极控制而改变导电类型，故本实施方式选择进一步将非晶半导体层270分解成了低掺杂的第一非晶半导体层271和高掺杂的第二非晶半导体层272。
附图2E所示，参考步骤S140，在所述第一绝缘层251表面与所述数据线230对应的区域形成通孔231。形成通孔231的步骤可以通过光刻腐蚀的方法。通孔231的作用在于为后续数据线230与源极电极或者漏极电极形成电学连接。
附图2F所示，参考步骤S150，在所述第一绝缘层251表面形成覆盖所述非晶半导体层270和所述通孔231的导电层290。导电层290的材料例如可以是选自于铟锡氧化物（ITO）和铟锌氧化物（IZO）中的一种，形成方法例如可以是旋涂法或者喷涂法等。导电层290覆盖通孔231，并与通孔231下方的数据线230贴合，以实现电学连接。
附图2G所示，参考步骤S160，将所述导电层290和第二非晶半导体层272中与所述栅极210对应的部分移除以分割导电层290和第二非晶半导体层272，从而形成薄膜晶体管的源极电极291和漏极电极292，并减薄对应位置的第一非晶半导体层271。其中源极电极291和漏极电极292的位置可以互换。分割导电层290和第二非晶半导体层272，以及减薄第一非晶半导体层271的制程可以采用光刻腐蚀的方法来实现。由于在前述步骤中导电层290已经和数据线230建立了电学连接，故本具体实施方式中形成的源极电极291无需额外制作与数据线230之间的电学连接结构。
附图2H所示，参考步骤S170，在所述第一绝缘层251表面形成覆盖所述非晶半导体层270、通孔231以及源极电极291和漏极电极292的第二绝缘层252。第二绝缘层252的材料可以是包括氧化硅和氮化硅在内的任意一种绝缘材料，作用在于保护被覆盖的非晶半导体层270、通孔231以及源极电极291和漏极电极292。
附图2I所示，参考步骤S180，除去所述第二绝缘层252位于所述源极电极291和漏极电极292之间部分。该步骤用于形成像素电极图案。
附图2J所示，参考步骤S190，采用激光照射所述非晶半导体层270，以增加非晶半导体层270晶格排列的有序度。非晶半导体层270在激光的照射下进行退火，由非晶材料向多晶材料转化，在激光功率足够大，并持续足够长照射时间的情况下，非晶材料甚者可以转化成多晶材料。多晶材料的晶格有序度更好，故具有更高的载流子迁移率，能够提高薄膜晶体管的电学性能。由于第二绝缘层252的厚度通常远远小于透明衬底200的厚度，故激光优选从第二绝缘层252一侧入射，激光的波长应当能够穿透第二绝缘层252和导电层290。在第二绝缘层252的材料是氮化硅或者氧化硅，导电层290的材料是ITO或者IZO的情况下，可见光波段以及红外波段的激光对于这些材料而言都是透明的。
继续参考附图2J，上述步骤实施完毕后所获得薄膜晶体管包括如下结构：透明衬底200；栅极210和数据线230，栅极210和数据线230设置在透明衬底200的表面；第一绝缘层251，所述第一绝缘层251覆盖栅极210和数据线230；非晶半导体层270，包括第一非晶半导体层271和第二非晶半导体层272，所述非晶半导体层270设置在第一绝缘层251表面与栅极210对应的区域；通孔231，所述通孔231设置在第一绝缘层251表面与所述数据线230对应的区域；源极电极291和漏极电极292，所述源极电极291和漏极电极292设置在非晶半导体层270的两端，源极电极291和漏极电极292之一通过通孔231连接至数据线230；以及第二绝缘层252，所述第二绝缘层252在第一绝缘层251表面，并覆盖非晶半导体层270、通孔231以及源极电极291和漏极电极292，第二绝缘层252位于源极电极291和漏极电极292之间部分是镂空的。其中，源极电极291和漏极电极292之间的第二非晶半导体层272是镂空的，第一非晶半导体层271在源极电极291和漏极电极292之间部分的厚度小于第一非晶半导体层271其余部分的厚度。
以上仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。
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  1. 一种薄膜晶体管，其特征在于，包括：
    透明衬底；
    栅极和数据线，所述栅极和数据线设置在所述透明衬底的表面；
    第一绝缘层，所述第一绝缘层覆盖所述栅极和所述数据线；
    非晶半导体层，所述非晶半导体层设置在所述第一绝缘层表面与所述栅极 对应的区域，所述非晶半导体层包括堆叠设置的导电类型相同的第一非晶半导体层和第二非晶半导体层，所述第一非晶半导体层与所述第一绝缘层贴合，所述第二非晶半导体层的电导率高于所述第一非晶半导体层的电导率；
    通孔，所述通孔设置在所述第一绝缘层表面与所述数据线对应的区域；
    源极电极和漏极电极，所述源极电极和漏极电极设置在所述非晶半导体层的两端，源极电极和漏极电极之一通过所述通孔连接至所述数据线，所述第二非晶半导体层与所述源极电极和漏极电极贴合，所述源极电极和漏极之间的所述第二非晶半导体层是镂空的；以及
    第二绝缘层，所述第二绝缘层在所述第一绝缘层表面，并覆盖所述非晶半导体层、通孔以及源极电极和漏极电极，所述第二绝缘层位于所述源极电极和漏极电极之间部分是镂空的。
  2. 根据权利要求1所述的薄膜晶体管，其特征在于，所述第一非晶半导体层在所述源极电极和漏极之间部分的厚度小于所述第一非晶半导体层其余部分的厚度。
  3. 一种薄膜晶体管的制造方法，其特征在于，包括如下步骤：
    提供透明衬底；
    在所述透明衬底表面形成栅极和数据线；
    在所述透明衬底表面形成覆盖所述栅极和所述数据线的第一绝缘层；
    在所述第一绝缘层表面与所述栅极对应的区域形成非晶半导体层；
    在所述第一绝缘层表面与所述数据线对应的区域形成通孔；
    在所述第一绝缘层表面形成覆盖所述非晶半导体层和所述通孔的导电层；
    将所述导电层与所述栅极对应的部分移除以分割导电层，从而形成薄膜晶体管的源极电极和漏极电极；
    在所述第一绝缘层表面形成覆盖所述非晶半导体层、通孔以及源极电极和漏极电极的第二绝缘层；以及
    采用激光照射所述非晶半导体层，以增加非晶半导体层晶格排列的有序度。
  4. 根据权利要求3所述的薄膜晶体管的制造方法，其特征在于，所述非晶半导体层包括堆叠设置的导电类型相同的第一非晶半导体层和第二非晶半导体层，所述第一非晶半导体层与所述第一绝缘层贴合，所述第二非晶半导体层与所述源极电极和漏极电极贴合，所述第二非晶半导体层的电导率高于所述第一非晶半导体层的电导率。
  5. 根据权利要求4所述的薄膜晶体管的制造方法，其特征在于，所述非晶半导体层采用外延的方法形成，并在外延的过程中通过改变掺杂物质的浓度以形成第一非晶半导体层和第二非晶半导体层。
  6. 根据权利要求4所述的薄膜晶体管的制造方法，其特征在于，在分割导电层的步骤中，进一步包括同时移除所述第二非晶半导体层与栅极对应部分的步骤。
  7. 根据权利要求5所述的薄膜晶体管的制造方法，其特征在于，在分割所述第二非晶半导体层的步骤中，进一步包括减薄暴露出来的第一非晶半导体层的步骤。
  8. 根据权利要求3所述的薄膜晶体管的制造方法，其特征在于，在形成第二绝缘层的步骤之后，进一步包括除去所述第二绝缘层位于所述源极电极和漏极电极之间部分的步骤。
  9. 一种薄膜晶体管，其特征在于，包括：
    透明衬底；
    栅极和数据线，所述栅极和数据线设置在所述透明衬底的表面；
    第一绝缘层，所述第一绝缘层覆盖所述栅极和所述数据线；
    非晶半导体层，所述非晶半导体层设置在所述第一绝缘层表面与所述栅极对应的区域；
    通孔，所述通孔设置在所述第一绝缘层表面与所述数据线对应的区域；
    源极电极和漏极电极，所述源极电极和漏极电极设置在所述非晶半导体层的两端，源极电极和漏极电极之一通过所述通孔连接至所述数据线；以及
    第二绝缘层，所述第二绝缘层在所述第一绝缘层表面，并覆盖所述非晶半导体层、通孔以及源极电极和漏极电极。
  10. 根据权利要求9所述的薄膜晶体管，其特征在于，所述非晶半导体层包括堆叠设置的导电类型相同的第一非晶半导体层和第二非晶半导体层，所述第一非晶半导体层与所述第一绝缘层贴合，所述第二非晶半导体层与所述源极电极和漏极电极贴合，所述第二非晶半导体层的电导率高于所述第一非晶半导体层的电导率，所述源极电极和漏极之间的所述第二非晶半导体层是镂空的。
  11. 根据权利要求10所述的薄膜晶体管，其特征在于，所述第一非晶半导体层在所述源极电极和漏极之间部分的厚度小于所述第一非晶半导体层其余部分的厚度。
  12. 根据权利要求9所述的薄膜晶体管，其特征在于，所述第二绝缘层位于所述源极电极和漏极电极之间部分是镂空的。
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