WO2013001692A1 - Dispositif électronique et procédé de suppression du bruit - Google Patents

Dispositif électronique et procédé de suppression du bruit Download PDF

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Publication number
WO2013001692A1
WO2013001692A1 PCT/JP2012/002526 JP2012002526W WO2013001692A1 WO 2013001692 A1 WO2013001692 A1 WO 2013001692A1 JP 2012002526 W JP2012002526 W JP 2012002526W WO 2013001692 A1 WO2013001692 A1 WO 2013001692A1
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WO
WIPO (PCT)
Prior art keywords
conductor
wiring board
conductor pattern
electronic device
external connection
Prior art date
Application number
PCT/JP2012/002526
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English (en)
Japanese (ja)
Inventor
石田　尚志
Original Assignee
日本電気株式会社
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Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Publication of WO2013001692A1 publication Critical patent/WO2013001692A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q15/00—Devices for reflection, refraction, diffraction or polarisation of waves radiated from an antenna, e.g. quasi-optical devices
    • H01Q15/0006—Devices acting selectively as reflecting surface, as diffracting or as refracting device, e.g. frequency filtering or angular spatial filtering devices
    • H01Q15/006—Selective devices having photonic band gap materials or materials of which the material properties are frequency dependent, e.g. perforated substrates, high-impedance surfaces
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0236—Electromagnetic band-gap structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters

Definitions

  • the present invention relates to an electronic device having two wiring boards that overlap each other and a noise suppression method.
  • a semiconductor device such as a large scale integrated circuit (LSI: Large Scale Integration) is usually mounted on a mother board or the like in a form mounted on a package wiring board which is a dedicated wiring board.
  • LSI Large Scale Integration
  • EBG Electromagnetic Band Band Gap
  • the EBG forms a band gap that suppresses propagation of electromagnetic waves in a specific frequency band inside or on a plane by taking a structure in which dielectrics or metals are periodically arranged in two or three dimensions. .
  • Patent Document 1 describes that by providing an EBG pattern inside a motherboard having a multilayer wiring structure, it is possible to suppress interference between connectors on the motherboard.
  • Patent Document 2 describes that an EBG structure is provided in a region located below the semiconductor device in the interposer.
  • connection between two wiring boards that overlap each other is often made with a connection terminal provided between these two wiring boards.
  • noise may be generated from the connection terminal due to a signal transmitted through the connection terminal.
  • the EBG described in the above-mentioned document is formed inside the wiring board. For this reason, it was not possible to block noise propagating in the space between the two wiring boards overlapping each other, such as noise generated from the connection terminal.
  • An object of the present invention is to provide an electronic device and a noise suppression method that can block noise propagating in a space between two wiring boards that overlap each other.
  • a first wiring board A second wiring board connected to the first wiring board; With The first wiring board has a first conductor; The second wiring board has a second conductor at least partially formed in a region facing the first conductor, and a third conductor connected to the second conductor, A repeating structure of the conductor is formed using the second conductor, The first wiring board and the second wiring board are connected to an area where the first conductor and the second conductor overlap in a space between the first wiring board and the second wiring board.
  • An electronic device is provided in which no member is located.
  • the first conductor is provided on the first wiring board on which the electrical component is mounted, A second conductor and a third conductor connected to the second conductor in at least a part of a region facing the first conductor of the second wiring board on which the first wiring board and the electrical component are mounted.
  • a noise suppression method is provided that suppresses the propagation of noise in the space between the first wiring board and the second wiring board by forming a portion.
  • (A) is sectional drawing which shows the structure of the electronic device which concerns on 1st Embodiment
  • (b) is the figure which looked down from the AA 'cross section of (a)
  • (c) is (a) It is the figure which looked at the upper part from the AA 'cross section of).
  • (A) is sectional drawing which shows the structure of the electronic device which concerns on 2nd Embodiment
  • (b) is the figure which looked down from the AA 'cross section of (a)
  • (c) is (a) It is the figure which looked up from the AA 'cross section of ().
  • (A) is sectional drawing which shows the structure of the electronic device which concerns on 3rd Embodiment
  • (b) is the figure which looked down from the AA 'cross section of (a)
  • (c) is (a) It is the figure which looked at the upper part from the AA 'cross section of).
  • (A) is sectional drawing which shows the structure of the electronic device which concerns on 4th Embodiment
  • (b) is the figure which looked down from the AA 'cross section of (a)
  • (c) is (a) It is the figure which looked at the upper part from the AA 'cross section of).
  • (A) is sectional drawing which shows the structure of the electronic device which concerns on 5th Embodiment
  • (b) is the figure which looked down from the AA 'cross section of (a)
  • (c) is (a) It is the figure which looked up from the AA 'cross section of ().
  • (A) is sectional drawing which shows the structure of the electronic device which concerns on 6th Embodiment
  • (b) is the figure which looked down from the AA 'cross section of (a)
  • (c) is (a) It is the figure which looked at the upper part from the AA 'cross section of).
  • (A) is sectional drawing which shows the structure of the electronic device which concerns on 7th Embodiment
  • (b) is the figure which looked down from the AA 'cross section of (a)
  • (c) is (a) It is the figure which looked up from the AA 'cross section of ().
  • FIG. 1A is a cross-sectional view showing the configuration of the electronic device according to the first embodiment.
  • FIG. 1B is a bottom view of the AA ′ cross section of FIG. 1A and shows the configuration of the surface of the mother board 13.
  • FIG. 1C is a top view of the AA ′ cross section of FIG. 1A, and shows the configuration of the surface of the package wiring board 300.
  • FIG. 1A is a cross-sectional view showing the configuration of the electronic device according to the first embodiment.
  • FIG. 1B is a bottom view of the AA ′ cross section of FIG. 1A and shows the configuration of the surface of the mother board 13.
  • FIG. 1C is a top view of the AA ′ cross section of FIG. 1A, and shows the configuration of the surface of the package wiring board 300.
  • This electronic device includes a package 12 and a mother board 13.
  • the package 12 includes a package wiring board 300 and a semiconductor chip 10.
  • the semiconductor chip 10 is mounted on the package wiring board 300.
  • the semiconductor chip 10 is flip-chip mounted on the package wiring board 300, but may be mounted by other mounting formats.
  • a package 12 is mounted on the mother board 13.
  • the package wiring board 300 is an example of a first wiring board
  • the mother board 13 is an example of a second wiring board.
  • the package wiring board 300 has a first conductor pattern 14 as a first conductor, and the mother board 13 has a second conductor pattern 15 as a second conductor.
  • the second conductor pattern 15 is formed in a region facing at least a part of the first conductor pattern, that is, a region at least partially overlapping the first conductor pattern 14 in plan view.
  • a repeating structure of the conductor is formed using at least one of the first conductor pattern 14 and the second conductor pattern 15.
  • at least one of the first conductor pattern 14 and the second conductor pattern 15 has a repeating structure, for example, a periodic structure in a region facing each other.
  • the first conductor pattern 14 and the second conductor pattern 15 constitute at least a part of an EBG (Electromagnetic Band Band Gap) structure 20.
  • the second conductor pattern 15 is electrically connected to other conductors of the mother board 13.
  • the first conductor pattern 14 is a sheet-like conductor pattern
  • the second conductor pattern 15 is a plurality of island-like conductor patterns that are separated from each other.
  • the mother board 13 has a fourth conductor pattern 17 in the wiring layer immediately below the second conductor pattern 15.
  • the fourth conductor pattern 17 is an example of a third conductor.
  • the fourth conductor pattern 17 is one of a ground plane and a power plane, for example, a ground plane, and extends in a region where the second conductor pattern 15 is formed in plan view.
  • the package wiring board 300 has an external connection terminal 320
  • the motherboard 13 has an external connection terminal 220.
  • the external connection terminal 320 is, for example, an electrode pad, and is formed on the surface 302 of the package wiring board 300 that faces the mother board 13.
  • the external connection terminal 220 is, for example, an electrode pad, and is formed on the surface 202 of the mother board 13 that faces the package wiring board 300.
  • the external connection terminals 220 and 320 are connected to each other by the connection member 111.
  • the EBG structure 20 is formed so as to surround the external connection terminals 220 and 320 and the connection member 111 in plan view.
  • a plurality of second conductor patterns 15 and external connection terminals 220 are formed.
  • the first conductor pattern 14 is formed on the surface 302 and is formed using the same conductor layer as the external connection terminal 320.
  • the second conductor pattern 15 is formed on the surface 202 and is formed of the same conductor layer as the external connection terminal 220.
  • the second conductor pattern 15 and the external connection terminals 220 are arranged in a grid pattern.
  • the arrangement period of the second conductor pattern 15 is shorter than the arrangement period of the external connection terminals 220.
  • the area of the second conductor pattern 15 is smaller than that of the external connection terminal 220.
  • the planar shape of both is a square, for example.
  • connection member 111 is a solder ball, and electrically connects the external connection terminal 320 of the package wiring board 300 and the external connection terminal 220 of the motherboard 13.
  • the periphery where the package wiring board 300 and the mother board 13 are connected by the connecting member 111 is sealed with a resin 112. That is, the resin 112 is filled in the space between the first conductor pattern 14 and the second conductor pattern 15.
  • the external connection terminal 320 of the package wiring board 300 is connected to the semiconductor chip 10 via the internal wiring and vias of the package wiring board 300. For this reason, the semiconductor chip 10 is connected to the external connection terminals 220 of the mother board 13 via the internal wiring, vias, and external connection terminals 320 of the package wiring board 300 and the connection member 111. In the semiconductor chip 10, each of the power supply line, the ground line, and the signal line is connected to the mother board 13.
  • the package wiring board 300 and the mother board 13 are multilayer wiring boards, and are formed by alternately laminating dielectric layers and conductor layers.
  • the sheet-like first conductor pattern 14 formed on the package wiring board 300 includes the multilayer wiring (including the third conductor pattern 16 on the inner side of the first conductor pattern 14) and vias of the package wiring board 300, and external connection.
  • the terminal 320, the connecting member 111, and the external connection terminal 220 are connected to the opposite type of the fourth conductor pattern 17, for example, the power plane.
  • the first conductor pattern 14 may be connected to a plane of the same type as the plane to which the above-described fourth conductor pattern 17 is connected among the power plane and the ground plane of the motherboard 13.
  • the second conductor pattern 15 formed on the mother board 13 is connected to the fourth conductor pattern 17 through the through hole 18.
  • the through hole 18 is formed at an arbitrary position in the planar shape of the second conductor pattern 15, and does not need to be formed at the center of the second conductor pattern 15.
  • a resist layer 304 is formed on the surface 302 of the package wiring board 300, and a resist layer 204 is formed on the surface 202 of the mother board 13.
  • the resist layer 304 has an opening 305 for exposing the external connection terminal 320 and the first conductor pattern 14, and the resist layer 204 has an opening 205 for exposing the external connection terminal 220.
  • the size of each capacitor is controlled by the distance between the package wiring board 300 and the mother board 13, the material of the resin 112, the size and arrangement of the island-like second conductor patterns 15, and the material of the mother board 13.
  • the inductance component is controlled by the material of the mother board 13 and the material, length, and thickness of the through hole 18.
  • the distance between the package wiring board 300 and the mother board 13 can be controlled by the shape of the connection member 111. By adjusting these, the band gap band of the EBG structure 20 can be adjusted.
  • the EBG structure 20 is a so-called mushroom type EBG
  • the unit cell 50 includes a fourth conductor pattern 17, an island-like second conductor pattern 15, a through hole 18, a resin 112, and a sheet-like first.
  • the conductive pattern 14 is constituted by a region facing the island-shaped second conductive pattern 15.
  • the first conductor pattern 14 corresponds to the upper conductor plane
  • the fourth conductor pattern 17 corresponds to the lower conductor plane.
  • the through hole 18 corresponds to an inductance portion of the mushroom
  • the second conductor pattern 15 corresponds to a head portion of the mushroom.
  • the unit cells 50 are repeatedly arranged, for example, periodically, whereby the EBG structure 20 is formed.
  • a capacitance is formed between the second conductor pattern 15 and the first conductor pattern 14, thereby suppressing noise propagation between the fourth conductor pattern 17 and the first conductor pattern 14.
  • the second conductor pattern 15 is formed on the mother board 13, and the first conductor pattern 14 is formed on the package wiring board 300.
  • the EBG structure 20 is formed in the space between the mother board 13 and the package wiring board 300. Therefore, noise is prevented from propagating through the space and radiated to the outside.
  • this noise for example, there is a connecting member 111.
  • the EBG structure 20 is designed so that the frequency of noise radiated from the connection member 111 is included in the band gap of the EBG structure 20, the noise radiated from the connection member 111 is a space between the package 12 and the motherboard 13. Leaking from is suppressed.
  • the first conductor pattern 14 is formed on the surface 302 of the package wiring board 300 that faces the mother board 13. For this reason, the distance between the first conductor pattern 14 and the second conductor pattern 15 can be reduced, and the capacitance component of the EBG structure 20 can be increased.
  • the second conductor pattern 15 is also formed on the surface 202 of the mother board 13 facing the package wiring board 300, the distance between the first conductor pattern 14 and the second conductor pattern 15 is further reduced. The capacitance component of the EBG structure 20 can be further increased.
  • the capacitance component can be controlled by adjusting the material characteristics of the resin 112 inserted between the first conductor pattern 14 and the second conductor pattern 15.
  • the resin 112 is inserted between the package 12 and the mother board 13 after assembling. Even after the package 12 is assembled on the mother board 13, the frequency characteristics of the EBG structure 20 can be controlled by adjusting the material characteristics of the resin to be inserted.
  • the interval between the same vias and connection members is within 1 ⁇ 2 of the wavelength ⁇ of the electromagnetic wave assumed as noise. It is preferable that “repetition” includes a case where a part of the configuration is missing in any unit cell 50. When the unit cell 50 has a two-dimensional array, “repetition” includes a case where the unit cell 50 is partially missing. Further, “periodic” includes a case where some of the constituent elements are deviated in some unit cells 50 and a case where the arrangement of some unit cells 50 themselves is deviated.
  • FIG. 2A is a cross-sectional view showing the configuration of the electronic device according to the second embodiment.
  • FIG. 2B is a bottom view of the AA ′ cross section of FIG. 2A and shows the configuration of the surface of the mother board 13.
  • FIG. 2C is a top view of the AA ′ cross section of FIG. 2A and shows the configuration of the surface of the package wiring board 300.
  • This electronic device has the same configuration as the electronic device according to the first embodiment except for the following points.
  • the second conductor pattern 15 and the external connection terminal 220 are arranged to constitute the same lattice. That is, the arrangement period of the second conductor pattern 15 and the arrangement period of the external connection terminal 220 are the same, and the distance between the second conductor pattern 15 and the external connection terminal 220 closest to the external connection terminal 220 is the mutual interval of the external connection terminals 220. Equal to the interval.
  • the second conductor pattern 15 has the same planar shape as the external connection terminal 220, and is, for example, a square.
  • the resin 112 is not inserted between the package wiring board 300 and the mother board 13. In this embodiment, the resin 112 can be added.
  • FIG. 3A is a cross-sectional view showing a configuration of an electronic device according to the third embodiment.
  • FIG. 3B is a bottom view of the AA ′ cross section of FIG. 3A and shows the configuration of the surface of the mother board 13.
  • FIG. 3C is a top view of the AA ′ cross section of FIG. 3A and shows the configuration of the surface of the package wiring board 300.
  • This electronic device has the same configuration as the electronic device according to the first embodiment except for the following points.
  • the semiconductor chip 10 is mounted on the package wiring board 300 using the bonding wires 11.
  • the first conductor pattern 14 is a plurality of island-like conductor patterns that are separated from each other, and the second conductor pattern 15 is a sheet-like conductor pattern.
  • the mother board 13 has a fourth conductor pattern 17 in the wiring layer immediately below the second conductor pattern 15.
  • the fourth conductor pattern 17 is one of a ground plane and a power plane, for example, a ground plane.
  • the first conductor pattern 14 and the external connection terminal 320 are arranged to constitute the same lattice. That is, the arrangement cycle of the first conductor pattern 14 and the arrangement cycle of the external connection terminal 320 are the same, and the distance between the first conductor pattern 14 and the external connection terminal 320 closest to the external connection terminal 320 is the mutual interval of the external connection terminals 320. Equal to the interval.
  • the first conductor pattern 14 has the same planar shape as the external connection terminal 320, and is, for example, a square. However, the first conductor pattern 14 and the external connection terminal 320 may be arranged to form different grids.
  • the connection member 111 is a solder ball, and electrically connects the external connection terminal 320 of the package wiring board 300 and the external connection terminal 220 of the motherboard 13.
  • the periphery where the package wiring board 300 and the mother board 13 are connected by the connecting member 111 is solidified by the resin 116, and the outer periphery thereof is solidified by the resin 117.
  • the space between the first conductor pattern 14 and the second conductor pattern 15 includes a region filled with the resin 116 and a region filled with the resin 117. Resin 116 and resin 117 have different material properties.
  • the package wiring board 300 and the mother board 13 are multilayer wiring boards, and are formed by alternately laminating dielectric layers and conductor layers.
  • the island-shaped first conductor pattern 14 formed on the package wiring board 300 includes the multilayer wiring (including the third conductor pattern 16 on the inner side of the first conductor pattern 14) and vias of the package wiring board 300, and external connection.
  • the terminal 320, the connecting member 111, and the external connection terminal 220 are connected to the opposite type of the fourth conductor pattern 17, for example, the power plane.
  • the first conductor pattern 14 may be connected to a plane of the same type as the plane to which the above-described fourth conductor pattern 17 is connected among the power plane and the ground plane of the motherboard 13.
  • the first conductor pattern 14 formed on the package wiring board 300 is connected to the third conductor pattern 16 through the through hole 19.
  • the through hole 19 is formed at an arbitrary position in the planar shape of the first conductor pattern 14, and does not need to be formed at the center of the first conductor pattern 14.
  • each capacitor of the EBG structure 20 depends on the distance between the package wiring board 300 and the mother board 13, the size and arrangement of the resin 116 and the resin 117, and the island-shaped first conductor pattern 14, and the material of the package wiring board 300.
  • the inductance component is controlled by the material of the package wiring board 300 and the material, length, and thickness of the through hole 19.
  • the distance between the package wiring board 300 and the mother board 13 can be controlled by the shape of the connection member 111. By adjusting these, the band gap band of the EBG structure 20 can be adjusted.
  • the EBG structure 20 is formed so as to surround the external connection terminals 220 and 320 and the connection member 111 with a double structure.
  • an EBG structure 21 surrounding the external connection terminals 220 and 320 and the connection member 111 and an EBG structure 22 surrounding the periphery thereof are formed.
  • the EBG structure 21 is a so-called mushroom type EBG, and has a unit cell 50.
  • the EBG structure 22 is also a so-called mushroom type EBG, and includes a unit cell 51.
  • the unit cells 50 and 51 are opposed to the island-like first conductor pattern 14 among the third conductor pattern 16, the island-like first conductor pattern 14, the through hole 19, and the sheet-like second conductor pattern 15. It is constituted by the area that is.
  • the second conductor pattern 15 corresponds to the upper conductor plane
  • the third conductor pattern 16 corresponds to the lower conductor plane.
  • the through hole 19 corresponds to an inductance portion of the mushroom
  • the first conductor pattern 14 corresponds to a head portion of the mushroom.
  • the unit cells 50 are repeatedly arranged, for example, periodically to form the EBG structure 21, and the unit cells 51 are repeatedly arranged, for example, to periodically form the EBG structure 22.
  • a difference in characteristics between the unit cell 50 and the unit cell 51 appears due to a difference in characteristics between the resin 116 and the resin 117.
  • the same effect as that of the first embodiment can be obtained also by this embodiment.
  • the characteristics of the resin 116 different from the dielectric constant of the resin 117 the capacity components of the unit cells 50 and 51 can be made different from each other.
  • the band gap band of the EBG structure 21 and the band gap band of the EBG structure 22 can be made different from each other. Therefore, it is possible to suppress noise in a plurality of different frequency bands.
  • the resins 116 and 117 can be inserted between the package 12 and the motherboard 13 after being assembled, the frequency characteristics of the EBG structure 20 can be controlled even after the package 12 is assembled on the motherboard 13. Can do.
  • FIG. 4A is a cross-sectional view showing a configuration of an electronic device according to the fourth embodiment.
  • FIG. 4B is a bottom view of the AA ′ cross section of FIG. 4A and shows the configuration of the surface of the mother board 13.
  • FIG. 4C is a top view of the AA ′ cross section of FIG. 4A and shows the configuration of the surface of the package wiring board 300.
  • This electronic device has the same configuration as the electronic device according to the third embodiment except for the following points.
  • the arrangement periods of the first conductor pattern 14 and the external connection terminal 220 are different. Even in the first conductor pattern 14, the size of the island-like planar shape and the arrangement period are different.
  • the resin 112 inserted between the package wiring board 300 and the mother board 13 is one kind.
  • the same effect as that of the third embodiment can be obtained. That is, by arranging multiple first conductor patterns 14 of different sizes, the unit cells 50 and 51 of the EBG structures 21 and 22 having different characteristics can be used without using a plurality of types of resins as the sealing resin. Can be formed. This makes it possible to suppress noise in a plurality of different frequency bands.
  • FIG. 5A is a cross-sectional view showing a configuration of an electronic device according to the fifth embodiment.
  • FIG. 5B is a bottom view of the AA ′ cross section of FIG. 5A and shows the configuration of the surface of the mother board 13.
  • FIG. 5C is a top view of the AA ′ cross section of FIG. 5A, and shows the configuration of the surface of the package wiring board 300.
  • FIG. This electronic device has the same configuration as the electronic device according to the third embodiment except for the following points.
  • the first conductor pattern 14 is formed of a stub instead of an island-like planar shape.
  • the first conductor pattern 14 is an open stub, but may be a short stub.
  • the resin 112 inserted between the package wiring board 300 and the mother board 13 is one kind.
  • the same effect as that of the third embodiment can be obtained.
  • the first conductor pattern 14 is formed of a stub, and the degree of freedom in designing to obtain the characteristics of the unit cell 50 of the EBG structure 20 can be improved.
  • FIG. 6A is a cross-sectional view showing the configuration of the electronic device according to the sixth embodiment.
  • FIG. 6B is a bottom view of the AA ′ cross section of FIG. 6A and shows the configuration of the surface of the mother board 13.
  • FIG. 6C is a top view of the AA ′ cross section of FIG. 6A and shows the configuration of the surface of the package wiring board 300.
  • This electronic device has the same configuration as the electronic device according to the first embodiment except for the following points.
  • the second conductor pattern 15 formed on the mother board 13 is a plurality of island-shaped conductor patterns spaced apart from each other.
  • the package wiring board 300 is not mounted with a semiconductor chip.
  • the package wiring board 300 has the first conductor pattern 14.
  • the first conductor pattern 14 is connected to the conductor pattern 501 of the motherboard 13 through the connection member 111, the external connection layer 502 on the motherboard 13 side, and the through hole 18 in the motherboard 13.
  • the conductor pattern 501 is connected to a power plane or a ground plane, for example, a ground plane.
  • the external connection layer 502 and the first conductor pattern 14 are sheet-like patterns on which two solder terminals are formed.
  • the second conductor pattern 15 is connected to the fourth conductor pattern 17 located in the internal wiring layer of the motherboard 13 through the through hole 18 formed in the motherboard 13.
  • the fourth conductor pattern 17 is the same type of plane as the plane to which the above-described conductor pattern 501 is not connected among the power plane and the ground plane, for example, the power plane.
  • the fourth conductor pattern 17 may be the same type of plane as the plane to which the conductor pattern 501 is connected among the power plane and the ground plane.
  • the unit cell 50 of the EBG structure 20 is configured by a region of the second conductor pattern 15, the through hole 18, the resin 112, and the first conductor pattern 14 facing the second conductor pattern 15.
  • the fourth conductor pattern 17 corresponds to the lower conductor plane
  • the first conductor pattern 14 corresponds to the upper conductor plane.
  • the through hole 18 corresponds to an inductance portion of the mushroom
  • the second conductor pattern 15 corresponds to a head portion of the mushroom.
  • the same effect as that of the first embodiment can be obtained.
  • the package wiring board 300 since the package wiring board 300 is not mounted with a semiconductor chip, the package wiring board 300 can be handled as a noise suppression component. In order to suppress noise generated from the mother board 13, there is an effect that the package wiring board 300 can be mounted at a predetermined location on the mother board 13. It is also possible to mount a plurality of package wiring boards 300 on the mother board 13 side by side.
  • the second conductor pattern 15 may be formed of a stub as shown in the fifth embodiment instead of the island-like planar shape.
  • the control range of the inductor component and the capacitance component of the unit cell 50 of the EBG structure 20 can be expanded.
  • the connection terminals between the package wiring board 300 and the mother board 13 are two places, and the island-like second conductor pattern 15 is also a matrix of two places.
  • the present invention is not limited to this. There is no.
  • the connection member 111 and the island-shaped second conductor pattern 15 may be a pair, or may form more matrices, and can be assembled in an arbitrary arrangement.
  • the EBG structure to comprise was a mushroom structure was shown, it is possible to apply arbitrary EBG structures, without being restricted by this.
  • FIG. 7A is a cross-sectional view showing the configuration of the electronic device according to the seventh embodiment.
  • 7A is a cross-sectional view taken along the line BB ′ of FIG. 7B
  • FIG. 7B is a view looking down from the cross-section AA ′ of FIG.
  • the structure of 13 surfaces is shown.
  • FIG. 7C is a top view of the AA ′ cross section of FIG. 7A and shows the configuration of the surface of the package wiring board 300.
  • This electronic device has the same configuration as the electronic device according to the second embodiment except for the following points.
  • the EBG structure 20 does not surround the external connection terminals 220 and 320 and the connection member 111. Instead, the unit cell 50 and the connecting member 111 constituting the EBG structure 20 are arranged in a confused manner.
  • the first conductor pattern 14 includes an opening 603 in a portion where the external connection terminal 320 is disposed. By providing the opening 603, it is possible to prevent the EBG structure 20 and the connection member 111 from being short-circuited. Thereby, the unit cell 50 and the connection member 111 can be arrange
  • the same effect as that of the second embodiment can be obtained. Furthermore, since the external connection terminals 220 and 320 and the EBG unit cell 50 can be mixed and arranged, the degree of freedom in designing the pin assignment of the external connection terminal 320 of the package 13 and the external connection terminal 220 of the motherboard 13 is increased. Can be improved.
  • the first conductor pattern 14 is formed on the surface 302 of the package wiring board 300 that faces the mother board 13, but the first conductor pattern 14 is formed on the internal wiring layer of the package wiring board 300. You may do it.
  • the second conductor pattern 15 is formed on the surface 202 of the mother board 13 facing the package wiring board 300, but the second conductor pattern 15 may be formed on the internal wiring layer of the mother board 13.
  • the configuration of the EBG structures 20, 21, and 22 is not limited to the above-described embodiment, and any structure that exhibits characteristics as an EBG can be applied as the EBG structures 20, 21, and 22.
  • the semiconductor chip is exemplified as the electronic element mounted on the package wiring board.
  • an electrical component other than the semiconductor chip may be used.
  • the structure shown in each of the above embodiments may be applied to a structure that obtains an electrical connection by mechanically pressing a package against a board, such as a land used in a land grid array.
  • the location of the EBG structure 20 is not limited to the above example.

Landscapes

  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

Un substrat de câblage de boîtier (300) est pourvu d'un premier tracé conducteur (14), et une carte mère (13) est pourvue d'un second tracé conducteur (15). Le second tracé conducteur (15) est formé dans une région qui fait face à au moins une partie du premier tracé conducteur (14), en d'autres termes, dans une région sur laquelle, dans une vue en plan, au moins une partie du premier tracé conducteur (14) est chevauchée. Une structure conductrice répétée est formée à l'aide de l'un ou l'autre tracé parmi le premier tracé conducteur (14) et le second tracé conducteur (15) ou à l'aide des deux tracés. Le premier tracé conducteur (14) et le second tracé conducteur (15) constituent au moins une partie d'une structure EBG (20). Le second tracé conducteur (15) est électriquement connecté à un autre conducteur dont est dotée la carte mère (13).
PCT/JP2012/002526 2011-06-28 2012-04-12 Dispositif électronique et procédé de suppression du bruit WO2013001692A1 (fr)

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JP2011143097 2011-06-28

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020040230A1 (fr) * 2018-08-24 2020-02-27 京セラ株式会社 Structure, antenne, module de communication sans fil et dispositif de communication sans fil
WO2022019148A1 (fr) * 2020-07-21 2022-01-27 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'antenne

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JP2006245193A (ja) * 2005-03-02 2006-09-14 Matsushita Electric Ind Co Ltd 基板間コネクタおよび基板間コネクタを用いた実装体
JP2007531253A (ja) * 2004-03-11 2007-11-01 レイセオン・カンパニー 回路板適用上のマイクロストリップおよびフリップチップにおける電磁結合を抑制する電磁バンドギャップ構造
WO2009082003A1 (fr) * 2007-12-26 2009-07-02 Nec Corporation Elément à bande interdite électromagnétique, et antenne et filtre l'utilisant
JP2011124503A (ja) * 2009-12-14 2011-06-23 Nec Corp 電子装置及びノイズ抑制方法

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Publication number Priority date Publication date Assignee Title
JP2007531253A (ja) * 2004-03-11 2007-11-01 レイセオン・カンパニー 回路板適用上のマイクロストリップおよびフリップチップにおける電磁結合を抑制する電磁バンドギャップ構造
JP2006245193A (ja) * 2005-03-02 2006-09-14 Matsushita Electric Ind Co Ltd 基板間コネクタおよび基板間コネクタを用いた実装体
WO2009082003A1 (fr) * 2007-12-26 2009-07-02 Nec Corporation Elément à bande interdite électromagnétique, et antenne et filtre l'utilisant
JP2011124503A (ja) * 2009-12-14 2011-06-23 Nec Corp 電子装置及びノイズ抑制方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020040230A1 (fr) * 2018-08-24 2020-02-27 京セラ株式会社 Structure, antenne, module de communication sans fil et dispositif de communication sans fil
WO2022019148A1 (fr) * 2020-07-21 2022-01-27 ソニーセミコンダクタソリューションズ株式会社 Dispositif d'antenne

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