WO2012157670A1 - Substrat de carbure de silicium - Google Patents

Substrat de carbure de silicium Download PDF

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Publication number
WO2012157670A1
WO2012157670A1 PCT/JP2012/062507 JP2012062507W WO2012157670A1 WO 2012157670 A1 WO2012157670 A1 WO 2012157670A1 JP 2012062507 W JP2012062507 W JP 2012062507W WO 2012157670 A1 WO2012157670 A1 WO 2012157670A1
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silicon carbide
substrate
stacking fault
transition layer
density
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PCT/JP2012/062507
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Japanese (ja)
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邦明 八木
孝光 河原
弘幸 長澤
圭 中筋
晶郎 廣瀬
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Hoya株式会社
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H01L21/0265—Pendeoepitaxy

Definitions

  • the present invention relates to a silicon carbide substrate used for a high-performance semiconductor element.
  • the present invention relates to a silicon carbide substrate that can be preferably used as a material for a high-efficiency and high-voltage power semiconductor element because the surface defect density at a specific surface of the crystal is low and the warpage of the substrate is small.
  • Silicon carbide has begun to be used as a compound semiconductor crystal serving as a substrate for high-performance semiconductor elements.
  • Lattice defects contained in the silicon carbide substrate greatly affect the performance of the semiconductor element.
  • surface defects such as an anti-phase region boundary surface (APB: Anti-Phase-Boundary) and a stacking fault (SF: Stacking Fault) cause current leakage and dielectric breakdown, which significantly impairs the performance of the power semiconductor device. For this reason, reduction of a surface defect density is desired for a silicon carbide substrate used as a substrate for a semiconductor element.
  • APIB Anti-Phase-Boundary
  • SF stacking fault
  • Patent Document 1 A method for reducing surface defects when forming a silicon carbide substrate will be described below.
  • Patent Document 2 As described in Patent Document 1, Patent Document 2, and Non-Patent Document 1, as a method for effectively reducing both the anti-phase region boundary surface and the stacking fault, which are surface defects in SiC, parallel to one direction.
  • a technique has been developed for growing silicon carbide on a silicon substrate having undulations with a smooth ridge. Below, the defect elimination mechanism using this technique is demonstrated.
  • the polar surface is the same as the growth on the silicon substrate in which the main surface introduced with the off angle is (001).
  • the crystal orientation directions are integrated in one direction, and the antiphase region boundary surface disappears.
  • the stacking fault density is reduced by the following mechanism.
  • Si-SF a stacking fault that exposes the Si polar face on the (001) plane
  • C-SF C polar face
  • C-SF self-extinguishes by reducing the surface area because the surface energy of the C polar face is relatively lower than the surface energy of the (001) face.
  • Si—SF is stable because the surface energy of the Si polar face is relatively higher than the surface energy of the (001) face. Therefore, the Si polar face continues to be exposed on the outermost surface and remains on the surface.
  • stacking faults that occur on the facing slopes are aligned in a mirror-facing positional relationship, and disappear as a result of the growth of silicon carbide.
  • Non-patent Document 2 As a means for extinguishing such Si-SF, SBE (Switch Back Epitaxy) technology (Non-patent Document 2) has been developed. In the following, the SBE technique will be described.
  • 11 is a silicon carbide crystal
  • 12 is a stacking fault
  • 13 is a Si polar plane of stacking fault
  • 14 is a C polar plane of stacking fault.
  • reference numerals are given in the description using the drawings, but the reference numerals are omitted in other cases.
  • symbol is described in a parenthesis.
  • the reference numerals may be described in parentheses or there may be no parentheses, but there is no change in the meaning that each component corresponds to each reference numeral in the drawings. As shown in FIG.
  • the SF-exposed surface of Si—SF is a C-polar surface on the back side of the substrate. That is, if the back side of the substrate is the growth surface, the exposed surface of Si—SF remaining when SiC is grown on the undulations having a ridge parallel to one direction as described above can be converted to a C polarity surface. Since the C-polar plane self-extinguishes due to growth, cubic silicon carbide is homoepitaxially grown on the back side, and in principle, the remaining stacking faults disappear and the stacking faults are completely eliminated.
  • the above-described surface defect reduction technique significantly reduces the stacking fault density, and a low-defect density cubic silicon carbide substrate suitable for highly functional semiconductor elements is produced. Since the stacking faults existing in the cubic silicon carbide crystal are annihilated or self-annihilated in the silicon carbide growth process and the stacking fault reducing means process, the defect density has a rate of change corresponding to the growth film thickness. However, since the lattice spacing is reduced when stacking faults disappear due to each annihilation mechanism, an intrinsic stress corresponding to the stacking fault density change is generated in the crystal lattice. Thus, since the stress resulting from the stacking fault density change is applied to the silicon carbide substrate, the silicon carbide substrate is finally warped.
  • the warpage of the cubic silicon carbide substrate produced by the conventional technique reaches several hundreds ⁇ m with a 3 inch diameter and several mm with a 6 inch diameter.
  • the warpage of the substrate allowed for the semiconductor manufacturing process, particularly the photolithography process is 50 ⁇ m or less, and therefore the silicon carbide substrate manufactured by the prior art is not suitable for the semiconductor manufacturing process due to the large warpage.
  • the present invention has been made in view of the above problems, and the defect density and the warpage of the substrate are required so that both the defect density necessary for realizing a highly functional semiconductor element and the amount of warpage necessary for adaptation of the semiconductor manufacturing process are compatible. It aims at providing the silicon carbide substrate which reduced both the quantity.
  • the stacking fault density was reduced to a desired density with a gradual change rate by making the growth film thickness very thick. Later, there is a method of cutting out the surface layer and repeating this process several times.
  • silicon carbide is a difficult-to-cut and brittle material, it is difficult to process, and the manufacturing cost increases, so industrial advantages can be found. Absent. Therefore, the details of (b) were studied intensively, and the configuration of the present invention was reached.
  • the problem solving means is as follows. (1) In a silicon carbide substrate having two planes parallel to each other of a first surface that is a main surface and a second surface that is a back surface of the first surface, A surface defect is exposed on the first surface and the second surface, and The surface defect density N1 exposed on the first surface is smaller than the surface defect density N2 exposed on the second surface, and
  • the silicon carbide substrate has one or more transition layers substantially parallel to the first surface having a surface defect density gradient in a direction substantially perpendicular to the first surface;
  • the transition layer has a space inside, and A silicon carbide substrate, wherein a surface defect density gradient in the transition layer is 20 ⁇ (N2-N1) / t or more, where t is a distance between the first surface and the second surface.
  • FIG. 2 is an example in which the transition layer is provided on the first surface side.
  • the crystal structure that lowers the stacking fault density change gradient is also referred to as a mother crystal.
  • crystal structure or “other crystal structure”.
  • the surface defect density on the first surface is N1
  • the surface defect density on the second surface is N2
  • the surface defect density at the interface between the transition layer and the mother crystal is N3
  • the thickness of the transition layer is t T
  • the first surface The distance between the first surface and the second surface, that is, the thickness (total film thickness) of the entire region in the silicon carbide substrate is defined as t.
  • gradient in this specification refers to the rate of change when the surface defect density changes in the thickness direction.
  • the change rate of the surface defect density is called a gradient.
  • the change rate of the surface defect density is referred to as a gradient.
  • control of the surface defect density gradient is important.
  • an inclusion region that prevents propagation of stacking faults is provided in the transition layer.
  • “gradient 1”, which is the surface defect density gradient that the transition layer should have, is set to be “20 ⁇ (N2 ⁇ N1) / t or more”, that is, “20 ⁇ gradient 2” or more. is doing.
  • the surface defect density gradient (gradient 1) of the transition layer is set to be 20 times or more the surface defect density gradient (gradient 2) of the entire region.
  • the “transition layer” in the present specification is a layered portion in the silicon carbide substrate, and an inclusion region (substantially refers to a space.
  • the inclusion region is referred to as a space). It refers to the part inside.
  • the inclusion region (space) may be one or plural.
  • each space is distributed substantially parallel to the first surface.
  • the transition layer is a layered portion parallel to the main surface (52) and including the space (53).
  • FIG. 5 is a schematic diagram (cross-sectional view) for illustrating the space provided in the silicon carbide crystal.
  • the space referred to here does not propagate the stacking fault (55) because a mismatched interface is formed at the interface with silicon carbide inside the silicon carbide substrate. This is because stacking faults propagate in a specific direction because they are in a single crystal.
  • a part of the space (53) in FIG. 5 (the lower part and the part on the second surface side) is formed on the main surface of the silicon carbide substrate, and silicon carbide is further grown thereon. Then, silicon carbide is connected at the main surface (52).
  • the film growth direction can be adjusted as appropriate by adjusting the film forming conditions (adjusting the temperature and pressure, particularly the Si / C raw material supply ratio).
  • the stacking fault is prevented from propagating as soon as it comes into contact with the space (53), regardless of the disappearance of the association.
  • the stacking fault density can be significantly reduced on the main surface (52) regardless of the presence or absence of strain.
  • the Young's modulus of the space (53) is lower than that of silicon carbide (51), the thermal strain and lattice strain generated in the silicon carbide crystal lattice are absorbed, and the generation of stacking faults (55) is suppressed. Furthermore, even if the stacking fault (55) occurs, the space (53) prevents the propagation of them, so that it is possible to reduce the stacking fault density in the upper part of the space (53). However, in order to effectively reduce the stacking fault density, it is necessary to satisfy the condition that all stacking faults (55) meet in the space (53).
  • limiting of (Formula 1) is added with respect to height (H).
  • the side wall of the portion that forms the space must not be parallel to the closest dense surface through which the stacking fault (55) propagates, and the inner angle (54: ⁇ ) of the side wall of the portion that forms the stacking fault and the space is 0. More than 90 degrees and less than 90 degrees, the relationship of Equation 1 must be maintained.
  • the silicon carbide substrate is cubic silicon carbide
  • the main surface is the (001) plane
  • the side wall of the portion forming the space is parallel to the ⁇ 110 ⁇ plane
  • ⁇ 35.3 degrees.
  • W is 10 ⁇ m
  • H may be 14.1 ⁇ m or more.
  • FIG. 5 is a cross-sectional view in the substrate specific direction, but each space may be discrete or may be connected to each other in the transition layer.
  • the space and the side wall forming the space are distributed over the entire plane substantially parallel to the first surface in the transition layer. Is preferred.
  • the transition layer has a plurality of spaces, it is preferable that the transition layer is distributed substantially in parallel to the main surface. Even in the case of a single space, the side wall forming the space extends over the entire plane substantially parallel to the main surface. Are preferably distributed.
  • off-angle machining is performed by slightly tilting the surface normal axis in order to reduce the stacking fault density gradient and eliminate the anti-phase region boundary surface.
  • Silicon carbide is grown on the formed silicon substrate to form a mother crystal. By introducing the off-angle, the propagation direction of stacking faults becomes unidirectional, the mechanism of disappearance of their association disappears, and the mechanism of decrease of stacking fault density accompanying growth disappears.
  • silicon carbide grows on a silicon substrate whose main surface (the most exposed part of the crystal surface has the largest exposed area) is the (001) plane, an angle of about several degrees is given in the [110] direction.
  • the stacking fault propagating in parallel to the (111) plane is blocked, and the stacking fault propagation direction is limited to the direction parallel to the ( ⁇ 1-11) plane.
  • the stacking fault propagating in parallel to the ( ⁇ 111) plane is cut off, and the stacking fault propagation direction is limited to the direction parallel to the (1-11) plane.
  • the angle applied in the [110] direction needs to be different from the angle applied in the [ ⁇ 110] direction. As a result, anisotropy occurs in the step flow growth direction, the remaining antiphase boundary is suppressed, and the propagation direction of the remaining stacking faults can be controlled.
  • the warpage of the silicon carbide substrate can be reduced by providing a transition layer with a steep stacking fault density gradient at the beginning of growth and then growing a silicon carbide crystal (mother crystal) that maintains a low stacking fault density. . That is, in this case, a mother crystal is formed from the transition layer to the first surface. Even when this means is used, in order to eliminate the anti-phase region boundary surface, a silicon substrate in which off angles are given in advance to the [110] direction and the [ ⁇ 110] direction is used.
  • the inventors of the present invention have a undulation extending direction and residual Si—SF. It is confirmed that there is a correlation in the propagation direction. Specifically, Si—SF is exposed in the direction perpendicular to the undulation extending direction on the silicon carbide growth surface.
  • the present inventors grew silicon carbide on a substrate having such undulations, the amount of warpage of the obtained silicon carbide film was not isotropic in the plane, and the undulation extending direction and its orthogonal direction And found that there is anisotropy (the curvature radius of the warping amount is different).
  • the presence of an in-plane warp anisotropy in the silicon carbide substrate is considered undesirable in the device manufacturing process. That is, since the same radius of curvature in the silicon carbide substrate surface is preferable, the [110] orientation and the [ ⁇ 110] orientation are used rather than using a substrate having undulations extending in one direction as in Patent Document 2. It is preferable to use a substrate having a different off angle.
  • a silicon carbide substrate having a low warpage and a low defect density can be manufactured without complicating the manufacturing process.
  • FIG. 1 It is a schematic diagram showing a stacking fault structure in cubic silicon carbide It is a figure which shows the stacking fault profile of the board
  • this invention is not limited to this. It is a cubic silicon carbide substrate, a main surface having a stacking fault density of N1 is parallel to the ⁇ 001 ⁇ plane, and is a plate-like crystal having a back surface parallel to this and a stacking fault density of N2.
  • the surface defect density gradient in the transition layer having a space is 20 ⁇ (N2-N1) / t or more, preferably 30 ⁇ (N2-N1) / T or more, more desirably 50 ⁇ (N2-N1) / t or more.
  • the numerical range of N1 is preferably 700 / cm or less.
  • FIG. 3 is a stress distribution in the thickness direction of a typical cubic silicon carbide substrate obtained by numerical analysis.
  • FIG. 4 shows a stacking fault density distribution in the thickness direction of a typical cubic silicon carbide substrate. 3 and 4 show that there is a close correlation between stress and stacking fault density distribution. 3 and 4, it can be seen that the stress changes greatly from the back surface of the substrate to 100 ⁇ m, and the stacking fault density also decreases from the back surface of the substrate to a thickness of about 100 ⁇ m.
  • the stress inside the substrate is determined by a stress of up to about 100 ⁇ m with a change in stacking fault density. If such a transition layer is embodied, there is little influence on the warp of the silicon carbide crystal substrate, and a warp of 50 ⁇ m, which is an allowable amount of the semiconductor manufacturing process, is realized.
  • the transition layer thickness t T is preferably t / 20 or less.
  • the thickness t T of the transition layer is t / 20 or less, there is little influence on the warp of the entire silicon carbide crystal substrate, and a warp of 50 ⁇ m, which is an allowable amount of the semiconductor process, can be realized more reliably.
  • the transition layer thickness t T is desirably t / 30 or less.
  • a plurality of spaces are present uniformly within 0.05 ⁇ t, preferably within 0.04 ⁇ t, more preferably within 0.01 ⁇ t from the main surface to the inside of the substrate. is doing.
  • the layer in which the space is distributed is substantially parallel to the main surface, and the side wall of the portion forming the space is substantially parallel to the ⁇ 110 ⁇ plane.
  • the width (S), interval (W), and height (H) of each space do not need to be exactly the same, but W is 100 nm to 100 ⁇ m, preferably 1 ⁇ m to 50 ⁇ m, and more preferably 2 ⁇ m. Within 20 ⁇ m. This is because, as W becomes narrower, not only processing for forming a space becomes difficult, but also the volume occupancy of the space in the silicon carbide substrate increases, and the substrate resistance when operating as a semiconductor device increases. It is. On the other hand, if W becomes too large, the number of spaces in the transition layer will decrease. Also, in order to prevent the propagation of defects, the height H of the space must be increased. Increasing the height H leads to increasing the thickness of the silicon carbide substrate itself.
  • the volume of the silicon carbide substrate is increased more than the height H is increased and the volume of the space is increased.
  • H is specified from the above W according to (Equation 1), but if it is extremely small, not only the processing becomes difficult, but also the volume occupancy of the space decreases, and thermal strain cannot be absorbed completely. .
  • extremely large processing 100 ⁇ m or more is also difficult, and the volume occupancy of the space increases, increasing the transition layer thickness and inhibiting effective warpage reduction.
  • the width (S) of the space is 100 nm to 100 ⁇ m, preferably 1 ⁇ m to 50 ⁇ m, more preferably 2 ⁇ m to 20 ⁇ m. This is because, as S becomes narrower, the processing for forming the space becomes difficult, and the volume occupancy of the space decreases, making it impossible to absorb the thermal strain. On the other hand, if S becomes extremely large, the volume occupancy of the space increases and the substrate resistance when operating as a semiconductor device increases, and it becomes difficult to set W to a desirable value. Alternatively, the present invention can be realized even when a plurality of spaces are uniformly present at 0.95 ⁇ t or more, preferably 0.96 ⁇ t or more from the main surface to the back surface of the substrate.
  • silicon carbide is applied to the silicon substrate that has been subjected to off-angle processing that slightly tilts the surface normal axis in order to eliminate the anti-phase region boundary surface while reducing the stacking fault density gradient.
  • off-angle processing the surface normal axis of the (001) plane is tilted in the range of 0.1 ° to 54.7 °, preferably 1 ° to 6 ° in the [110] direction.
  • the surface normal axis of the (001) plane is also tilted in the range of 0.1 ° to 54.7 °, preferably 1 ° to 6 ° in the [ ⁇ 110] direction.
  • transition layer is present on the first surface or the second surface.
  • the transition layer is present between the first surface and the second surface. It doesn't matter.
  • a plurality of transition layers may exist. After all, a transition layer having a steep surface defect density change gradient and a mother crystal that lowers the stacking fault density change gradient from the first surface or the second surface to the transition layer may be present.
  • a silicon substrate in which the surface normal axis of the (001) plane is tilted by 4 ° in the [110] direction and the surface normal axis of the (001) plane is also tilted by 2 ° in the [ ⁇ 110] direction is placed in a C 2 H in a CVD apparatus. Heating was performed in a mixed atmosphere of 2 and H 2 to form an ultrathin silicon carbide layer. The diameter of the substrate is 6 inches. The substrate was heated to 1350 ° C. The source gas C 2 H 2 and the carrier gas H 2 were supplied to the substrate surface from room temperature. The supply amount and pressure are as shown in the substrate temperature raising conditions in Table 1.
  • silicon carbide was grown by supplying SiH 2 Cl 2 , C 2 H 2 and H 2 at a temperature of 1350 ° C.
  • the growth conditions in this case are as shown in Table 2. The pressure during the growth was adjusted with a pressure regulating valve installed between the reaction chamber and the pump.
  • Si source gas used for the growth of silicon carbide is SiH 4 , SiCl 4 , SiHCl 3
  • C source gas is CH 4 , C 2 H 4 , C 2 H 6 , C 3 H 8 . It can be used.
  • the silicon substrate was etched with a mixed acid of hydrofluoric acid and nitric acid to produce a single cubic silicon carbide substrate. Near the interface with the silicon substrate, stacking fault layers due to lattice mismatch exist at high density. If this layer is present, the warp cannot be reduced even if the transition layer according to the present invention is provided.
  • a polishing process using 0.1 ⁇ m diamond abrasive grains is performed to remove the 10 ⁇ m stacking fault layer from the silicon substrate interface.
  • it was immersed in molten KOH at 500 ° C. for 5 minutes. Then, when the optical microscope observation was implemented with respect to the board
  • the stacking fault density on the back surface, that is, the second surface was 2.1 ⁇ 10 5 pieces / cm as observed with an optical microscope.
  • the surface defect (stacking defect) density measurement was performed as follows.
  • the (111) plane defect that appears on the (001) surface is mainly parallel to the [ ⁇ 110] direction.
  • the surface defects parallel to the [ ⁇ 110] direction are calculated as the number (unit: lines / cm) intersecting the unit length in the [110] direction perpendicular to the [110] direction. Is calculated as the number (unit: lines / cm) intersecting the unit length in the [ ⁇ 110] direction orthogonal to the surface length, and the average value thereof is defined as the surface defect (stacking defect) density.
  • a metal film layer having a laminated structure of Cr / Au was provided on the main surface using a vacuum deposition method.
  • the thickness of each layer was set to Cr 25 nm and Au 110 nm.
  • a positive resist of 2 ⁇ m was spin-coated on the upper layer, and exposed with ultraviolet rays so as to expose a square pattern array with a photomask.
  • the mask pattern line side was aligned so as to be parallel to the ⁇ 110 ⁇ orientation of the substrate.
  • One side of the square pattern was 2 ⁇ m, and the interval between the patterns was 9 ⁇ m.
  • the resist was developed to provide an opening in the exposed region, and Ni having a thickness of 0.5 ⁇ m was formed in the opening by Ni electroplating.
  • the resist was completely removed by organic cleaning, and a Ni pattern having a thickness of 0.5 ⁇ m was obtained in a square portion with a side of 2 ⁇ m arranged at intervals of 9 ⁇ m.
  • vertical mesa processing was performed by inductively coupled plasma reactive ion etching. Silicon carbide is processed together with chromium and gold other than the square. Thereafter, Cr, Au, and Ni remaining in the square portion were completely removed by wet etching. Further, it was washed with a hydrogen peroxide solution + sulfuric acid mixed solution (1: 1) and an HF solution. After cleaning, a thermal oxide film was formed to a thickness of about 100 nm using a heat treatment apparatus.
  • the formed thermal oxide film was removed with dilute hydrofluoric acid.
  • discrete cubic silicon carbide reference numeral 62 in FIG. 6
  • the start surface of the transition layer is a surface including the bottom of the mesa-processed portion formed by the above method (the bottom of the lower portion of the later space (74)) or the vicinity thereof. It is extremely difficult to measure the stacking fault density of the portion corresponding to the bottom, and there is almost no change in the stacking fault density with a difference of 5 ⁇ m in the thickness direction with respect to the total film thickness of about 300 ⁇ m.
  • the stacking fault density on the main surface before mesa processing is used as the stacking fault density (N3) on the start surface of the transition layer.
  • the “transition layer” includes not only the portion corresponding to the bottom portion but also the vicinity thereof.
  • FIG. 6 shows a cross-sectional structure of the silicon carbide substrate after patterning.
  • 61 is a silicon carbide layer
  • 62 is a discretely arranged silicon carbide.
  • FIG. 7 shows a cross-sectional structure of the silicon carbide grown on the silicon carbide substrate of FIG.
  • Reference numeral 71 denotes a silicon carbide layer
  • 72 denotes silicon carbide discretely grown selectively
  • 73 denotes a silicon carbide layer grown on discretely formed silicon carbide
  • 74 denotes a space.
  • the upper portions of discretely grown silicon carbide (72) are connected to each other, the main surface, that is, the depth of 0.1 ⁇ m below the first surface is 4 ⁇ m wide, 7 ⁇ m apart, A space (74) having a height of 9.9 ⁇ m was formed.
  • 6 and 7 are schematic views only. Originally, when silicon carbide is grown after forming the lower portion of the space as shown in FIG. 6, film growth in both the substrate film thickness direction and the surface in-plane direction occurs, and discretely as shown in FIG. The upper portions of the selectively grown silicon carbide (72) are connected to each other, and the upper portion of the space (74) is also formed.
  • the silicon carbide substrate was immersed in molten KOH at 500 ° C. for 5 minutes.
  • the stacking fault density on the first surface was 525 / cm.
  • a layer that is, a transition layer
  • the stacking fault density is significantly reduced as compared with that before the space is formed. Note that in the region occupying the upper part (the main surface side part) of the space (74) in the transition layer, the propagation of stacking faults is prevented in the space (74) when discretely growing silicon carbide selectively.
  • the stacking fault density is of course greatly reduced. Further, regarding the region that occupies the lower part (the back side part) of the space (74) in the transition layer, a slightly new carbonization is formed in the lower part of the space (74) when silicon carbide is selectively grown discretely. Although silicon is stacked, the stacking fault density is reduced because the propagation of stacking faults is prevented by the space (74) also in this stacked portion. Therefore, in the present specification, a layered portion in the silicon carbide substrate, which is provided with a space (74) therein, is a “transition layer” in which the stacking fault density is sharply reduced.
  • cubic silicon carbide having a (001) plane as the main surface was used as the substrate.
  • the side wall of the portion forming the space is the ⁇ 111 ⁇ plane, ⁇ It is parallel to either the 110 ⁇ plane or the ⁇ 211 ⁇ plane.
  • the ⁇ 0001 ⁇ plane can be selected as the main surface.
  • the side wall of the portion forming the space is parallel to the ⁇ 11-20 ⁇ plane or the ⁇ 1100 ⁇ plane.
  • the most dense surface through which the stacking fault propagates is the (0001) plane, and the stacking fault intersects with the main surface at an angle of 30 to 60 degrees. It is clear that it will result.
  • FIG. 1 the definition of the curvature of a board
  • the substrate surface was scanned horizontally with a laser displacement meter manufactured by Keyence Corporation, and the difference between the maximum value and the minimum value at the substrate height at that time was warped.
  • Table 4 shows the values of the parameters in FIG.
  • t was measured with a micrometer manufactured by Mitutoyo Corporation. N1, N2, and N3 were subjected to a molten KOH treatment (500 ° C. ⁇ 5 min) on the surface of the cubic silicon carbide substrate, and after surface defects were revealed, the number of surface defects per unit length was counted with a microscope. . When the surface defect density gradient was obtained from the obtained numerical value, the gradient 1 was 25.3 times the gradient 2, and the condition of 20 times or more was satisfied. The transition layer thickness t T was about 1/30 of the total film thickness t. It was confirmed by warpage measurement that the warpage of the substrate was 45 ⁇ m.
  • the silicon carbide arranged discretely is formed using the square mask pattern.
  • the silicon carbide arranged discretely may be formed using the mask pattern of the line and space. .
  • a space is formed using discretely arranged silicon carbide formed in this way, a plurality of discrete spaces are formed that are positioned in parallel to each other on a plane substantially parallel to the first surface. . Even in such a form, the effects of the present invention can be sufficiently obtained.
  • ⁇ Comparative Example 1> A silicon substrate in which the surface normal axis of the (001) plane is tilted by 2 ° in the [110] direction and the surface normal axis of the (001) plane is also tilted by 1 ° in the [ ⁇ 110] direction is placed in a C 2 H in a CVD apparatus. Heating was performed in a mixed atmosphere of 2 and H 2 to form an ultrathin silicon carbide layer. The diameter of the substrate is 6 inches. The substrate was heated to 1350 ° C. The source gas C 2 H 2 and the carrier gas H 2 were supplied to the substrate surface from room temperature. The supply amount and pressure are as shown in Table 1. After the substrate surface reached 1350 ° C., the substrate was maintained in the above-described C 2 H 2 and hydrogen atmosphere for 15 minutes.
  • silicon carbide was grown by supplying SiH 2 Cl 2 , C 2 H 2 and H 2 at a temperature of 1350 ° C.
  • the growth conditions in this case are as shown in Table 2.
  • the pressure during the growth was adjusted with a pressure regulating valve installed between the reaction chamber and the pump.
  • Si source gas used for the growth of silicon carbide is SiH 4 , SiCl 4 , SiHCl 3
  • C source gas is CH 4 , C 2 H 4 , C 2 H 6 , C 3 H 8 . It can be used.
  • the silicon substrate was etched with a mixed acid of hydrofluoric acid and nitric acid to produce a single cubic silicon carbide substrate.
  • a polishing process using 0.1 ⁇ m diamond abrasive grains is performed to remove a 10 ⁇ m stacking fault layer from the interface.
  • it was immersed in molten KOH at 500 ° C. for 5 minutes. Thereafter, when the substrate on which the defects were revealed was observed with an optical microscope, the stacking fault density on the front surface, that is, the first surface was 4000 / cm, and the stacking fault density on the back surface, that is, the second surface, was 8000. Book / cm.
  • the surface defect (stacking defect) density measurement is calculated as the number (unit: book / cm) of plane defects parallel to the [ ⁇ 110] direction intersecting the unit length in the [110] direction perpendicular to the [ ⁇ 110] direction.
  • the surface defects parallel to the [110] direction are calculated as the number (unit: lines / cm) intersecting the unit length in the [ ⁇ 110] direction orthogonal to the surface defects, and the average value of these is calculated as the surface defect (stacking defect). Density.
  • Table 5 shows the values of the parameters of the obtained substrate. In this comparative example, since no transition layer is provided, N3 is omitted.
  • t and t T was measured by Mitutoyo micrometer.
  • N1, N2, and N3 the surface of the 3C—SiC substrate was subjected to a molten KOH treatment (500 ° C., 5 minutes), and surface defects were revealed, and then the number of surface defects per unit length was counted with a microscope.
  • the gradient 1 was about 13.7 times the gradient 2, and the condition of 20 times or more was not satisfied. It was confirmed by warpage measurement that the warpage of the substrate was 500 ⁇ m. That is, it was found that when the gradient 1 is less than 20 times the gradient 2, the warpage of the substrate becomes large.
  • Comparative Example 2 was performed by a method basically according to Example 1. Note that one side of the square discrete region is 2 ⁇ m and the interval is 16 ⁇ m. First, 300 ⁇ m cubic silicon carbide was grown on a 6-inch diameter silicon substrate. However, a silicon substrate having a (001) surface normal axis inclined by 3 ° in the [110] direction and a (001) surface normal axis inclined by 2 ° in the [ ⁇ 110] direction was used as the silicon substrate. After the growth, the silicon substrate was etched with a mixed acid of hydrofluoric acid and nitric acid to produce a single cubic silicon carbide substrate.
  • the surface defect (stacking defect) density measurement is calculated as the number (unit: book / cm) of plane defects parallel to the [ ⁇ 110] direction intersecting the unit length in the [110] direction perpendicular to the [ ⁇ 110] direction.
  • the surface defects parallel to the [110] direction are calculated as the number (unit: lines / cm) intersecting the unit length in the [ ⁇ 110] direction orthogonal to the surface defects, and the average value of these is calculated as the surface defect (stacking defect). Density.
  • the upper portions of discretely grown silicon carbide (72) are connected to each other, the width is 4 ⁇ m, the distance is 14 ⁇ m, and the depth is 30.1 ⁇ m at the lower portion of the main surface (that is, the first surface).
  • a space (74) having a height of 19.9 ⁇ m was formed. In this case, the thickness of the transition layer was 20 ⁇ m.
  • Table 7 shows the value of each parameter for the obtained substrate.
  • t and t T was measured by Mitutoyo micrometer.
  • N1, N2, and N3 the surface of the 3C—SiC substrate was subjected to a molten KOH treatment (500 ° C., 5 min), surface defects were revealed, and the number of surface defects per unit length was counted with a microscope.
  • the gradient 1 was 15.8 times the gradient 2 and did not satisfy the condition of 20 times or more. It was confirmed by warpage measurement that the warpage of the substrate was 250 ⁇ m.
  • a silicon substrate in which the surface normal axis of the (001) plane is tilted by 4 ° in the [110] direction and the surface normal axis of the (001) plane is also tilted by 2 ° in the [ ⁇ 110] direction is placed in a C 2 H in a CVD apparatus. Heating was performed in a mixed atmosphere of 2 and H 2 to form an ultrathin silicon carbide layer. The diameter of the substrate is 6 inches.
  • the substrate was heated to 1350 ° C.
  • the source gas C 2 H 2 and the carrier gas H 2 were supplied to the substrate surface from room temperature. The supply amount and pressure are as shown in Table 1. After the substrate surface reached 1350 ° C., the substrate was maintained in the above-described C 2 H 2 and hydrogen atmosphere for 15 minutes.
  • silicon carbide was grown by supplying SiH 2 Cl 2 , C 2 H 2 and H 2 at a temperature of 1350 ° C.
  • the growth conditions in this case are as shown in Table 2.
  • the pressure during the growth was adjusted with a pressure regulating valve installed between the reaction chamber and the pump.
  • Si source gas used for the growth of silicon carbide is SiH 4 , SiCl 4 , SiHCl 3
  • C source gas is CH 4 , C 2 H 4 , C 2 H 6 , C 3 H 8 . It can be used.
  • a metal film layer having a laminated structure of Cr / Au was provided on the main surface using a vacuum deposition method.
  • the thickness of each layer was set to Cr 25 nm and Au 110 nm.
  • a positive resist of 2 ⁇ m was spin-coated on the upper layer, and exposed with ultraviolet rays so as to expose a square pattern array with a photomask.
  • the mask pattern line side was aligned so as to be parallel to the ⁇ 110 ⁇ orientation of the substrate.
  • One side of the square pattern was 2 ⁇ m, and the distance between the patterns was 12 ⁇ m.
  • the resist was developed to provide an opening in the exposed region, and Ni having a thickness of 0.5 ⁇ m was formed in the opening by Ni electroplating.
  • the resist was completely removed by organic cleaning, and a Ni pattern having a thickness of 0.5 ⁇ m was obtained at a square portion having a side of 2 ⁇ m arranged at intervals of 12 ⁇ m.
  • vertical mesa processing was performed by inductively coupled plasma reactive ion etching. Silicon carbide is processed together with chromium and gold other than the square. Thereafter, Cr, Au, and Ni remaining in the square portion were completely removed by wet etching. Further, it was washed with a hydrogen peroxide solution + sulfuric acid mixed solution (1: 1) and an HF solution. After cleaning, a thermal oxide film was formed to a thickness of about 100 nm using a heat treatment apparatus.
  • the formed thermal oxide film was removed with dilute hydrofluoric acid. Through these steps, discrete cubic silicon carbide (that is, discretely arranged silicon carbide (62)) having a side of 2 ⁇ m and a height of 7 ⁇ m arranged on the main surface at intervals of 12 ⁇ m is formed. It was.
  • FIG. 6 shows a cross-sectional structure of the silicon carbide substrate after patterning. Thereafter, growth was performed for 60 minutes under the conditions in Table 8 to grow 8 ⁇ m cubic silicon carbide ((72) and (73)). At this time, as shown in FIG. 7, the upper parts of discretely grown silicon carbide (72) are connected to each other, the depth of the lower part of the main surface is 0.1 ⁇ m, the width is 4 ⁇ m, the interval is 10 ⁇ m, and the height is 14.9 ⁇ m. A space (74) is formed. In order to measure the stacking fault density on the main surface, that is, the transition layer surface, it was immersed in molten KOH at 500 ° C. for 5 minutes.
  • the stacking fault density in the main surface was 550 pieces / cm.
  • the surface of the transition layer is a surface including a portion immediately after the upper portions of discretely grown silicon carbide (72) are connected to each other, and the stacking fault density of the portion is strictly measured. Since there is almost no change in the stacking fault density when silicon carbide is stacked to the extent that the stacking fault density can be measured immediately after connection, the stacking fault density on the main surface described above Is used as the stacking fault density (N3) on the transition layer surface.
  • the “transition layer” includes not only a portion immediately after the upper portions of discretely grown silicon carbide (72) are connected to each other, but also a portion in which silicon carbide is laminated immediately after the connection so that the stacking fault density can be measured. .
  • a polishing process using 0.1 ⁇ m diamond abrasive grains is performed to remove a 50 ⁇ m stacking fault layer from the interface between the silicon substrate and silicon carbide.
  • it was immersed in molten KOH at 500 ° C. for 5 minutes. Thereafter, when an optical microscope observation was performed on the substrate on which the defects became apparent, the stacking fault density on the front surface (that is, the first surface) was 510 / cm, and the stacking fault on the back surface (that is, the second surface). The density was 1.5 ⁇ 10 5 lines / cm. Further, no anti-phase region interface was observed on the start surface of the transition layer.
  • Table 9 shows the values of the parameters in FIG. The substrate, the transition layer as shown in FIG. 9 (t T region) becomes the second surface area.
  • Total thickness t and the transition layer thickness t T was measured by Mitutoyo micrometer.
  • N1, N2, and N3 were subjected to molten KOH treatment (500 ° C., 5 min) on the surface of the cubic silicon carbide substrate, and surface defects were revealed. The number of defects was counted.
  • the surface defect density gradient (gradient 1) in the transition layer is about 20.6 times the surface defect density gradient (gradient 2) outside the transition layer region, which is 20 times or more.
  • the condition was met.
  • the warpage of the substrate was confirmed by warpage measurement to be 40 ⁇ m. That is, even when the transition layer is located on the second surface side, it was confirmed that a substrate with small warpage can be obtained if the gradient 1 is 20 times or more the gradient 2. In this example, the thickness of the transition layer satisfied 1/20 or less of the entire substrate.
  • Example 1 except that a silicon substrate in which the surface normal axis of the (001) plane is inclined by 3 ° in the [110] direction and the surface normal axis of the (001) plane is also inclined by 2 ° in the [ ⁇ 110] direction is used.
  • an ultrathin silicon carbide layer was formed on the silicon substrate under the conditions shown in Table 1. After the substrate surface reached 1350 ° C., the substrate was maintained in the above-described C 2 H 2 and hydrogen atmosphere for 15 minutes. Thereafter, in the same manner as in Example 1, growth was performed for 6 hours under the conditions shown in Table 2, and 300 ⁇ m cubic silicon carbide was grown on the Si substrate.
  • Si source gas used for the growth of silicon carbide is SiH 4 , SiCl 4 , SiHCl 3
  • C source gas is CH 4 , C 2 H 4 , C 2 H 6 , C 3 H 8 . It can be used.
  • the silicon substrate was etched with a mixed acid of hydrofluoric acid and nitric acid to produce a single cubic silicon carbide substrate.
  • a polishing process using 0.1 ⁇ m diamond abrasive grains is performed to remove the 10 ⁇ m stacking fault layer from the silicon substrate interface.
  • the stacking fault density on the front surface that is, the start surface of the transition layer was 7600 / cm
  • the stacking fault density on the back surface that is, the second surface was The number was 8000 / cm. Further, no anti-phase region interface was observed on the start surface of the transition layer.
  • the surface defect (stacking defect) density measurement is calculated as the number (unit: book / cm) of plane defects parallel to the [ ⁇ 110] direction intersecting the unit length in the [110] direction perpendicular to the [ ⁇ 110] direction.
  • the surface defects parallel to the [110] direction are calculated as the number (unit: lines / cm) intersecting the unit length in the [ ⁇ 110] direction orthogonal to the surface defects, and the average value of these is calculated as the surface defect (stacking defect). Density.
  • a metal film layer having a laminated structure of Cr / Au was provided on the main surface using a vacuum deposition method.
  • the thickness of each layer was set to Cr 25 nm and Au 110 nm.
  • a positive resist of 2 ⁇ m was spin-coated on the upper layer, and exposed with ultraviolet rays so as to expose a square pattern array with a photomask.
  • the mask pattern line side was aligned so as to be parallel to the ⁇ 110 ⁇ orientation of the substrate.
  • One side of the square pattern was 2 ⁇ m, and the interval between the patterns was 9 ⁇ m.
  • the resist was developed to provide an opening in the exposed region, and Ni having a thickness of 0.5 ⁇ m was formed in the opening by Ni electroplating.
  • the resist was completely removed by organic cleaning, and a Ni pattern having a thickness of 0.5 ⁇ m was obtained in a square portion with a side of 2 ⁇ m arranged at intervals of 9 ⁇ m.
  • vertical mesa processing was performed by inductively coupled plasma reactive ion etching. Silicon carbide is processed together with chromium and gold other than the square. Thereafter, Cr, Au, and Ni remaining in the square portion were completely removed by wet etching. Further, it was washed with a hydrogen peroxide solution + sulfuric acid mixed solution (1: 1) and an HF solution. After cleaning, a thermal oxide film was formed to a thickness of about 100 nm using a heat treatment apparatus.
  • the formed thermal oxide film was removed with dilute hydrofluoric acid. Through such steps, discrete cubic silicon carbide (62 in FIG. 6) arranged on the main surface at intervals of 9 ⁇ m and having a side of 2 ⁇ m and a height of 5 ⁇ m was formed.
  • the silicon carbide substrate was immersed in molten KOH at 500 ° C. for 5 minutes.
  • the stacking fault density on the first surface was 525 / cm.
  • FIG. 10 shows the definition of the curvature of a board
  • t was measured with a micrometer manufactured by Mitutoyo Corporation. N1, N2, and N3 were subjected to a molten KOH treatment (500 ° C. ⁇ 5 min) on the surface of the cubic silicon carbide substrate, and after surface defects were revealed, the number of surface defects per unit length was counted with a microscope. . When the gradient was obtained from the obtained numerical value, the gradient 1 was about 27.9 times the gradient 2, and the condition of 20 times or more was satisfied. The transition layer thickness t T was about 1/30 of the total film thickness t. Further, it was confirmed by warpage measurement that the warpage of the substrate was 45 ⁇ m.
  • Example 2 except that a silicon substrate in which the surface normal axis of the (001) plane is inclined by 3 ° in the [110] direction and the surface normal axis of the (001) plane is also inclined by 2 ° in the [ ⁇ 110] direction is used. Similarly, heating was performed in a CVD apparatus in a mixed atmosphere of C 2 H 2 and H 2 to form an extremely thin silicon carbide layer on the silicon substrate. The diameter of the substrate is 6 inches. The substrate was heated to 1350 ° C. The source gas C 2 H 2 and the carrier gas H 2 were supplied to the substrate surface from room temperature. The supply amount and pressure are as shown in Table 1.
  • the substrate surface reached 1350 ° C.
  • the substrate was maintained in the above-described C 2 H 2 and hydrogen atmosphere for 15 minutes.
  • silicon carbide was grown by supplying SiH 2 Cl 2 , C 2 H 2 and H 2 at a temperature of 1350 ° C.
  • the growth conditions in this case are as shown in Table 2.
  • the pressure during the growth was adjusted with a pressure regulating valve installed between the reaction chamber and the pump.
  • Si source gas used for the growth of silicon carbide is SiH 4 , SiCl 4 , SiHCl 3
  • C source gas is CH 4 , C 2 H 4 , C 2 H 6 , C 3 H 8 . It can be used.
  • a metal film layer having a laminated structure of Cr / Au was provided on the main surface using a vacuum deposition method.
  • the thickness of each layer was set to Cr 25 nm and Au 110 nm.
  • a positive resist of 2 ⁇ m was spin-coated on the upper layer, and exposed with ultraviolet rays so as to expose a square pattern array with a photomask.
  • the mask pattern line side was aligned so as to be parallel to the ⁇ 110 ⁇ orientation of the substrate.
  • One side of the square pattern was 2 ⁇ m, and the interval between the patterns was 9 ⁇ m.
  • the resist was developed to provide an opening in the exposed region, and Ni having a thickness of 0.5 ⁇ m was formed in the opening by Ni electroplating.
  • the resist was completely removed by organic cleaning, and a Ni pattern having a thickness of 0.5 ⁇ m was obtained in a square portion with a side of 2 ⁇ m arranged at intervals of 9 ⁇ m.
  • vertical mesa processing was performed by inductively coupled plasma reactive ion etching. Silicon carbide is processed together with chromium and gold other than the square. Thereafter, Cr, Au, and Ni remaining in the square portion were completely removed by wet etching. Further, it was washed with a hydrogen peroxide solution + sulfuric acid mixed solution (1: 1) and an HF solution. After cleaning, a thermal oxide film was formed to a thickness of about 100 nm using a heat treatment apparatus.
  • the formed thermal oxide film was removed with dilute hydrofluoric acid. Through these steps, discrete cubic silicon carbide (that is, discretely arranged silicon carbide (62)) having a side of 2 ⁇ m and a height of 5 ⁇ m arranged at intervals of 9 ⁇ m is formed on the main surface. It was.
  • FIG. 6 shows a cross-sectional structure of the silicon carbide substrate after patterning. Thereafter, growth was performed for 60 minutes under the conditions shown in Table 8 to grow 5 ⁇ m cubic silicon carbide ((72) and (73) in FIG. 7). At this time, as shown in FIG. 7, the upper parts of discretely grown silicon carbide (72) are connected to each other, the depth of the lower part of the main surface is 0.1 ⁇ m, the width is 4 ⁇ m, the interval is 7 ⁇ m, and the height is 9.9 ⁇ m. A space (74) is formed. In order to measure the stacking fault density on the main surface, that is, the transition layer surface, it was immersed in molten KOH at 500 ° C. for 5 minutes.
  • the stacking fault density in the main surface was 525 / cm.
  • the surface defect parallel to the [ ⁇ 110] direction is calculated as the number (unit: lines / cm) intersecting the unit length in the [110] direction perpendicular to the [110] direction. ]
  • the silicon substrate was etched with a mixed acid of hydrofluoric acid and nitric acid to produce a single cubic silicon carbide substrate.
  • a polishing process using 0.1 ⁇ m diamond abrasive grains is performed to remove the 25 ⁇ m stacking fault layer from the interface between the silicon substrate and silicon carbide.
  • it was immersed in molten KOH at 500 ° C. for 5 minutes. Thereafter, when an optical microscope observation was performed on the substrate in which the defects became apparent, the stacking fault density on the front surface (namely, the first surface) was 500 / cm2, and the stacking fault on the back surface (namely, the second surface). The density was 8000 pieces / cm. Further, no anti-phase region interface was observed on the start surface of the transition layer.
  • Table 11 shows the values of the parameters in FIG. 8 for the obtained substrate.
  • the substrate, the transition layer as shown in FIG. 9 (t T region) becomes the second surface area.
  • Total thickness t and the transition layer thickness t T was measured by Mitutoyo micrometer.
  • N1, N2, and N3 were subjected to a molten KOH treatment (500 ° C., 5 min) on the surface of the cubic silicon carbide substrate, and after revealing surface defects, the number of surface defects per unit length was counted with a microscope. .
  • the surface defect density gradient (gradient 1) in the transition layer is about 30 times the surface defect density gradient (gradient 2) outside the transition layer region, and the condition of 20 times or more is satisfied. I met.
  • the surface defect distribution in the region other than the transition layer, that is, N3 was within the range of N1 ⁇ 5%.
  • the warpage of the substrate was 50 ⁇ m. That is, even when the transition layer is located on the second surface side, it was confirmed that a substrate with small warpage can be obtained if the gradient 1 is 20 times or more the gradient 2. In this example, the thickness of the transition layer satisfied 1/20 or less of the entire substrate.

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Abstract

Cette invention concerne un substrat de carbure de silicium tel que : la densité de défauts plans (N1) sur une première surface est inférieure à la densité de défauts plans (N2) sur une seconde surface ; le substrat de carbure de silicium présente au moins une couche de transition approximativement parallèle à une première surface et présentant un gradient de densité de défauts plans dans le sens approximativement parallèle à une première surface, ainsi qu'un gradient de densité de défauts plans dans le sens approximativement perpendiculaire à la première surface ; la couche de transition présente un espace interne ; et si la distance de la première à la seconde surface est t, alors le gradient de densité de défauts plans dans la couche de transition est supérieur ou égal à 20×(N2-N1)/t.
PCT/JP2012/062507 2011-05-18 2012-05-16 Substrat de carbure de silicium WO2012157670A1 (fr)

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