TW201006973A - Nitride semiconductor layer-containing structure, nitride semiconductor layer-containing composite substrate and production methods of these - Google Patents

Nitride semiconductor layer-containing structure, nitride semiconductor layer-containing composite substrate and production methods of these Download PDF

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TW201006973A
TW201006973A TW098117306A TW98117306A TW201006973A TW 201006973 A TW201006973 A TW 201006973A TW 098117306 A TW098117306 A TW 098117306A TW 98117306 A TW98117306 A TW 98117306A TW 201006973 A TW201006973 A TW 201006973A
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nitride semiconductor
semiconductor layer
base substrate
substrate
nitride
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TWI427198B (en
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shi-nan Wang
Kenji Tamamori
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Canon Kk
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    • H01L21/02617—Deposition types
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD

Abstract

A nitride semiconductor layer-containing structure having a configuration in which: the structure includes a laminated structure based on at least two nitride semiconductor layers; the structure includes between the two nitride semiconductor layers in the laminated structure a plurality of voids surrounded by the faces of the walls inclusive of the inner walls of the recessed portions of the asperity pattern formed on the nitride semiconductor layer that is the lower layer of the two nitride semiconductor layers; and crystallinity defect-containing portions to suppress the lateral growth of the nitride semiconductor layer are formed on at least part of the inner walls of the recessed portions to form the voids.

Description

201006973 六、發明說明： 【發明所屬之技術領域】 本發明有關於含氮化物半導體層之結構、含氮化物半 導體層之複合基底及其製造方法。詳言之，本發明有關於 基於磊晶橫向過度生長之氮化物半導體層的製造方法。 【先前技術】 氮化物半導體，例如由通式AlxGayIni-x-yN(〇SxSl 、OSySl、OSx + ySl)表示之氮化鎵化合物半導體，具 有相對大能帶隙並且爲直接過渡型半導體材料。 因此，氮化物半導體被用爲形成半導體發光裝置之材 料，如能夠發射對應至從紫外線光至綠光的短波長光線之 半導體雷射，及能夠涵蓋從紫外線光至紅光及額外地白光 的廣發射波長範圍及發光二極體（LED )。 爲了獲得高品質的半導體發光裝置，需要高品質的氮 化物半導體膜或基底。 尤其，爲了獲得高品質的氮化物半導體膜，較佳進行 使用同質高品質的氮化物半導體基底或晶格常數差且熱膨 脹係數差相對小之異質基底的磊晶生長。 此外，在氮化物半導體之應用中，必須在根據情況形 成了氮化物半導體膜或氮化物半導體結構之後移除基礎基 底。 然而，會有難以製造高品質氮化物半導體膜或高品質 氮化物半導體基底的問題。於下討論此問題的主因。 -5- 201006973 (η氮化物半導體基底之製造程序涉及高成本步驟 。例如，在製造GaN基底時，需高溫及高壓，且難以製造 低缺陷密度且大直徑之基底。因此，GaN基底價格不菲， 且無法取得滿足量產之GaN基底的平穩供應。 (2) 適合用於高品質氮化物半導體之磊晶生長的異 質基底很稀少。需在約1000 °C之高溫及含有族V材料之 強腐蝕性的氨環境下進行氮化物半導體膜之磊晶生長。能 夠承受此種嚴苛條件的異質之單晶體基底有限。 (3) 取決於裝置，因爲氮化物半導體本身的晶體性 質，需要複雜的結構。例如，爲了實現一光學元件，成分 互相不同的氮化物半導體必須層壓成複數層。 由於上述原因，總的來說藍寶石基底經常作爲氮化物 半導體之基礎基底。 另一方面，如GaN、AlGaN及GalnN之氮化物半導體 爲晶格常數互不相同的完全應變材料，且因此在這些氮化 物半導體之間及這些氮化物半導體與基底之間容易產生裂 縫及應力應變。 因此，當使用如藍寶石基底的異質基底時，會發生由 增殖於氮化物半導體中因氮化物半導體與異質基底間的晶 格常數差所引起的錯位而導致之問題。 此一錯位穿線般通過氮化物半導體膜而到達氮化物半 導體的最上層，而變成穿線型（threading)錯位，並可能 降低氮化物半導體膜之性質。 此外，亦有在氮化物半導體膜及異質基底間發生因氮 -6- 201006973 化物半導體膜及異質基底間的熱膨脹係數差所引起的應力 應變。應力應變不僅使氮化物半導體及異質基底變形，並 且成爲氮化物半導體膜性質下降的因素之一。 爲了減少穿線型錯位密度，在應用物理書信（Appl. Phys. Lett.)(第 7 2 冊、第 16 號、19 9 8 年 4 月 2 0 日、 第2014至20 16頁）中揭露一種方法，其中藉由積極地利 用橫向生長來進行GaN的磊晶生長。 在此情況中，於橫向生長法中，其亦稱爲磊晶橫向過 度生長（ELOG )法，首先在異質基底上交替形成促進氮 化物半導體生長之區域及干擾氮化物半導體生長之區域。 並且，在促進生長區域上選擇性生長氮化物半導體， 並且氮化物半導體朝生長干擾區域橫向地生長。 在干擾生長區域上，不從基底生長氮化物半導體，且 干擾生長區域覆蓋有從促進生長區域上之氮化物半導體橫 向延伸的氮化物半導體。 因此，基底與氮化物半導體間之介面中產生的錯位幾 乎不會出現在表面上。 因而，在由橫向生長法形成的氮化物半導體中形成穿 線型錯位密度之分布。 詳言之，穿線型錯位密度在異質基底上的促進生長區 域上保持爲高，但在異質基底上之干擾生長區域上穿線型 錯位密度降低。 根據此技術，可獲得完全平坦且在某些區域中表面附 近的穿線型錯位密度爲低之氮化物半導體膜。 201006973 此技術提供一特徵，其藉由利用在基礎基底上形成之 遮罩圖案來實現氮化物半導體之選擇性ELOG生長。 可使用例如Si02作爲遮罩圖案的材料。在日本應用 物理期刊（Jpn. J. Appl· Phys.)(第42冊、第2部、第 7B號、2003年7月15日、第L818至L820頁）中，進一 步揭露一種藉由使用Si02遮罩圖案的ELOG生長來形成 厚膜氮化物半導體之兩層結構的技術。 日本專利申請案公開號2007-3 14360亦揭露一種氮化 物半導體膜之選擇性生長技術，使用Mg化合物作爲遮罩 圖案的材料。 根據此技術，Mg促成氮化物半導體膜之橫向生長， 並因此可有效率地製造令人滿意的氮化物半導體膜。 美國專利案號6,3 3 5,546亦揭露一種氮化物半導體之 選擇性ELOG生長技術，不使用任何遮罩圖案。 根據此技術，即便使用如藍寶石之材料所製造的異質 基底，仍可獲得平坦且低穿線型錯位密度之氮化物半導體 膜。 此效果亦已驗證於光及視覺環境期刊（J. Light & Vis. Env_)(第 27 冊、第 3 號（2003 年）、第 140 至 M5頁）中。此技術實現氮化物半導體膜之選擇性ELOG 生長，藉由利用形成在基底之生長表面上的粗糙圖案，並 具有在氮化物半導體與圖案凹陷部中的基底之間有空隙的 特徵。空隙的存在某程度緩和氮化物半導體與基底間之應 力應變。 -8 - 201006973 爲了減少穿線型錯位，美國專利案號6，9 7 9，5 8 4揭露 一種技術，其中：設置具有突出及凹陷表面（粗糙圖案） 的第一氮化物半導體，並接著藉由利用突出部的上面及側 面作爲晶核，進行第二氮化物半導體之磊晶縱向及橫向過 度生長；且當凹陷部被氮化物半導體塡充的同時，氮化物 半導體亦往上生長。 根據此技術，在其中第二氮化物半導體經歷磊晶橫向 @ 過度生長的部份之上部分中第一氮化物半導體所具有之穿 線型錯位的增殖會受到抑制，且可在被塡充之凹陷部中形 成穿線型錯位緩和的區域。 尤其，藉由重複突出及凹陷表面成形及磊晶縱向與橫 向過度生長，可預期到穿線型錯位之進一步的減少。此技 術具有空隙形成於第二氮化物半導體中的特徵。 另一方面，同樣在氮化物半導體之基礎基底的移除中 ，經常會有長操作時間以及氮化物半導體的破壞之問題。 φ 這些問題在使用藍寶石（其爲硬）作爲基礎基底時特別顯 著。 日本專利申請案公開號200 1 - 1 768 1 3揭露一種氮化物 _ 半導體基底的製造方法，其中可藉由滿意地移除如藍寶石 基底的異質基底來獲得氮化物半導體基底。 根據此技術，可獲得無瑕疵且錯位減少以及在結晶度 及表面條件上令人滿意之氮化物半導體基底。 在此技術中，藉由以來自從異質基底側之電磁波輻射 分解氮化物半導體來移除異質基底；此技術具有在氮化物 9 - 201006973 半導體與異質基底間有空隙形成能減少所產生的N2之氣 體壓力對氮化物半導體之破壞的特徵。 然而’上述應用物理書信（第72冊、第16號、 1998年4月20日、第2014至2016頁）、日本鹰用物理 期刊（第42冊、第2部、第7B號、2003年7月15日、 第L818至L820頁）或日本專利申請案公開號2007-314360中所揭露的技術需要使用與氮化物半導體異質的材 料來做爲遮罩’以實現氮化物半導體膜之選擇性ELOG生 長。 因此’此技術會有一個問題，即在需要約l〇〇(TC生長 溫度的氮化物半導體膜之晶體生長程序中，遮罩材料降級 而不利地影響氮化物半導體膜。 例如，在其中遮罩材料爲Si02的情況中，其成分Si 或〇2，以及在遮罩材料爲Mg化合物的情況中，其成分 Mg及其它，擴散到氮化物半導體膜中而可能依情況不利 地影響氮化物半導體之品質或載體控制。 另一方面，光及視覺環境期刊（第27冊、第3號（ 2 003年）、第140至145頁）中所揭露之技術使用粗糙圖 案，並藉此克服使用異質材料遮罩的問題，並且同時實現 氮化物半導體膜與基底間之應力應變的緩和。 然而，藉由使用粗糙圖案而在氮化物半導體膜與基底 間形成僅單一層的空隙結構不足以減少穿線型錯位及緩和 應力應變。 正如此一技術，不容易形成具有想要形狀之兩或更多 -10- 201006973 層的空隙。 另一方面，美國專利案號6,979,864所揭露之技術能 夠形成兩或更多層的空隙，但難以確保空隙大小，因爲縱 向生長及橫向生長爲同時發生。因此，空隙對應力應變之 緩和的影響爲低。 曰本專利申請案公開號2001 -1 7681 3所揭露之技術藉 由分解下層來移除基礎基底，且移除造成的衝擊會傳送至 直接覆在下層上的氮化物半導體。 例如，在下層中產生之微裂縫會傳送至直接覆在下層 上的氮化物半導體。因此，單單日本專利申請案公開號 2 00 1-1 76 813所揭露之技術幾乎無法避免在移除基礎基底 時對氮化物半導體造成的破壞。 有鑑於上述問題，本發明之一目的在於提供一種結構 ，其含有穿線型錯位減少的氮化物半導體層、含此氮化物 半導體的複合基底及其製造方法。此外，本發明之另一目 的在於提供含此氮化物半導體層之結構的製造方法，其減 少基礎基底之移除對於氮化物半導體層的破壞。 【發明內容】 本發明提供一種如下述般形成含氮化物半導體層之結 構、一種含氮化物半導體層之複合基底及其製造方法。 本發明之含氮化物半導體層之結構的特徵在於：該結 構包含基於至少兩氮化物層之疊層結構；該結構包含，於 該疊層結構中之該兩氮化物半導體層之間，複數空隙，其 -11 - 201006973 係由包含形成於爲該兩氮化物半導體層之較低層的該氮化 物半導體層上之粗糙圖案的凹陷部之內壁的壁面所圍繞； 以及抑制該氮化物半導體層之橫向生長的含結晶度缺陷部 係形成於該些凹陷部之該些內壁的至少部分上以形成該些 空隙。 此外，本發明之含氮化物半導體層之複合基底的特徵 在於：含氮化物半導體層之結構係形成在基礎基底上。 此外，本發明之含氮化物半導體層之複合基底的製造 方法的其特徵在於包括：於基礎基底上形成第一氮化物半 導體層之第一步驟、於該第一氮化物半導體層上形成粗糙 圖案之第二步驟、於該第一氮化物半導體層之該粗糙圖案 中之凹陷部的內壁之至少部分上形成因自單晶體狀態變更 的狀態而造成的含結晶度缺陷部之第三步驟、以及於形成 在該第一氮化物半導體層上且包括該含結晶度缺陷部的該 粗糙圖案上形成第二氮化物半導體層之第四步驟。 此外，本發明之含氮化物半導體層之結構的製造方法 的特徵在於包括：藉由使用上述說明的任一者之複合基底 的製造方法來製造複合基底之步驟、以及從該製造方法所 製造的該複合基底移除基礎基底之步驟。 根據本發明，可實現含有穿線型錯位減少之氮化物半 導體層的結構、含此氮化物半導體層的複合基底及其製造 方法。 此外，可實現含此氮化物半導體層之結構的製造方法 ’其減少基礎基底之移除對於氮化物半導體層的破壞。 201006973 【實施方式】 根據本發明，作爲上述含氮化物半導體層之結構，可 實現上述結構。 在本發明之一實施例中，上述結構可如下般組態。 在本實施例中，含氮化物半導體層之結構設置有基於 至少兩氮化物半導體層的疊層結構。 此結構包括於該疊層結構中之該兩氮化物半導體層之 間，複數空隙，其係由包含形成於爲該兩氮化物半導體層 之較低層的該氮化物半導體層上之粗糙圖案的凹陷部之內 壁的壁面所圍繞。 抑制該氮化物半導體層之橫向生長的含結晶度缺陷部 係形成於該些凹陷部之該些內壁的至少部分上以形成該些 空隙。 因此，由於空隙的緣故，可緩和氮化物半導體層之薄 膜應變及兩氮化物半導體層間之壓力，且獲得穿線型錯位 密度的減少。 由於含結晶度缺陷部的緣故，可抑制凹陷部中氮化物 半導體的磊晶橫向過度生長並確保空隙之大小。含結晶度 缺陷狀態在此意指從單晶體狀態變更的一狀態’如非晶質 狀態、多孔狀態或多晶體狀態。 在此所指之氮化物半導體意指由通式AlxGayIni_x-yN (OSxSl、OSySl、OSx + ySl)表示之氮化鎵化合物 半導體。 -13- 201006973 根據本實施例的含氮化物半導體層之結構能夠實現含 有穿線型錯位減少的氮化物半導體層之結構。因此，可實 現較高品質之氮化物半導體光學元件。 在本發明之一實施例中，含氮化物半導體層複合基底 可如下般組態。 在本實施例中，藉由在基礎基底上形成含氮化物半導 體層之結構，可組態含氮化物半導體層複合基底。 在此情況中，含氮化物半導體層複合基底可組態成具 有，在該基礎基底與爲該兩氮化物半導體層之較低層的該 氮化物半導體層之間，複數空隙，其係由包含形成於爲該 較低層的該氮化物半導體層上之該粗糙圖案的該些凹陷部 之該些內壁的該些壁面所圍繞。 亦可藉由採用單晶體基底作爲基礎基底來組態含氮化 物半導體層複合基底。 亦可藉由採用一基礎基底爲該基礎基底，其中，在一 單晶體基底上，進一步形成有與該單晶體基底同質或異質 之中間膜，來組態含氮化物半導體層複合基底。 亦可藉由採用氮化物半導體、藍寶石、矽（Si)及碳 化矽（Sic )之任一者作爲單晶體基底之材料來組態含氮 化物半導體層複合基底。 根據本實施例的上述含氮化物半導體層複合基底能夠 組態含有穿線型錯位減少的氮化物半導體層之複合基底， 並藉此實現用於高品質的氮化物半導體之磊晶生長中的基 底。 -14 - 201006973 在本發明之一實施例中，含氮化物半導體層之複合基 底的製造方法可如下般組態。 根據本實施例的含氮化物半導體層之複合基底的製造 方法包括：於基礎基底上形成第一氮化物半導體層之第一 步驟、於該第一氮化物半導體層上形成粗糙圖案之第二步 驟、於該第一氮化物半導體層之該粗糙圖案中之凹陷部的 內壁之至少部分上形成因自單晶體狀態變更的狀態而造成 的含結晶度缺陷部之第三步驟、以及於形成在該第一氮化 物半導體層上且包括該含結晶度缺陷部的該粗糙圖案上形 成第二氮化物半導體層之第四步驟。 在此情況中，於形成含結晶度缺陷狀態之第三步驟中 ，可使用基於如反應性離子蝕刻（RIE )、電漿蝕刻、離 子輻射或反應性離子輻射之技術的表面處理。 藉由施加這些技術，所關心之部分可從單晶體狀態變 更成例如非晶質狀態、多孔狀態或多晶體狀態。 在本發明之一實施例中，該第一步驟可爲藉由於基礎 基底上形成粗糙圖案及藉由在該粗糙圖案上進行氮化物半 導體層的磊晶橫向過度生長來形成該第一氮化物半導體層 的連續層之步驟。 此外，第四步驟可爲藉由進行氮化物半導體層的磊晶 橫向過度生長來形成該第二氮化物半導體層的連續層之步 驟。 含氮化物半導體層複合基底的製造方法亦可組態成使 得在進行過第四步驟一次之後，分別進一步重複該第二及 -15- 201006973 該第四步驟N次（N20)，並且重複該第三步驟Μ次（ M2 N )。 上述根據本實施例之含氮化物半導體層複合基底的製 造方法能夠以比傳統氮化物半導體更低價地製造複合基底 並促成基底直徑的放大。 如上述此一基底的使用能進行高品質氮化物半導體層 - 的磊晶生長，並能實現高品質的光學元件。 含氮化物半導體層之結構亦能作爲用於氮化物半導體 之磊晶生長中的基底。 © 在本發明之一實施例中，可從藉由上述製造方法製造 的複合基底移除基礎基底，且含氮化物半導體層之結構的 製造方法可如下般組態。 根據本實施例的含氮化物半導體層之結構的製造方法 包括：藉由使用根據本發明之實施例的上述複合基底之製 造方法的任一者來製造複合基底之步驟、以及從該製造方 法所製造的該複合基底移除基礎基底之步驟。 ❹ 在本發明之一實施例中，製造結構之方法亦可組態成 使得於該移除該基礎基底的步驟中’使用一基礎基底作爲 該基礎基底，其中於單晶體基底上’進一步形成與單晶體 基底同質或異質之中間膜’且由選擇性蝕刻移除此中間膜 〇 製造結構之方法亦可組態成使得在該移除該基礎基底 的步驟中使用藍寶石作爲該基礎基底並從該基礎基底側進 行雷射照射，且在該藍寶石基底及該含氮化物半導體層的 -16- 201006973 結構之間的介面中分解該第一氮化物半導體層。 製造結構之方法亦可組態成使得在該移除該基礎基底 的步驟中，使用一基礎基底作爲該基礎基底，其中於單晶 體基底上，進一步形成與單晶體基底同質或異質之中間膜 ，並藉由光電化學蝕刻來選擇性移除該中間膜。 在此所稱之光電化學蝕刻意指一蝕刻，其中將基底浸 入電解溶液中，並在待蝕刻物體被外來紫外線光照射的同 時進行蝕刻。根據此方法，藉由紫外線照射在電流收縮層 表面中產生的正電洞導致電流收縮層之溶解作用，藉此允 許進行蝕刻。 此蝕刻亦稱爲PEC蝕刻（光電化學飩刻）。 在本發明之一實施例中，製造結構之方法亦可組態成 使得在該移除該基礎基底的步驟中，該含氮化物半導體層 之結構係接合至第二基底並接著移除該基礎基底。 上述根據本實施例的含氮化物半導體層複合基底之製 造方法進一步促進氮化物半導體之基礎基底的移除，並能 夠減少在基礎基底移除時對氮化物半導體所產生之破壞。 依照此方式，可減少製造成本並可獲得產率之改善。 此後，參照附圖進一步描述這些實施例。注意到在個 別圖中，相同符號用於相同元件，且因此省略冗餘部分之 說明。 (第一實施例） 作爲本發明之第一實施例，說明含氮化物半導體層之 -17- 201006973 結構的一範例。第1圖顯示描繪本實施例中之含氮化物半 導體層之結構的一範例之示意剖面圖。 第1圖描繪含氮化物半導體之結構20、第一氮化物半 導體層40、第一氮化物半導體層之凸出部42及在第一氮 化物半導體層中之含結晶度缺陷部45。 第1圖亦描繪第二氮化物半導體層50、形成在第一氮 化物半導體層之凹陷部中的氮化物半導體51及在氮化物 半導體結構中的空隙62。 本實施例的含氮化物半導體之結構20係由第一氮化 物半導體層40、第二氮化物半導體層50、及形成在這些 氮化物半導體層40及50間的氮化物半導體結構中之空隙 62 ° 一特徵爲結晶度缺陷可在圍繞氮化物半導體結構中之 空隙62的壁之至少一部分上。 含結晶度缺陷部爲例如第一氮化物半導體層40之內 壁的表面，由第一氮化物半導體層中的含結晶度缺陷部45 所指示。 接下來，更詳細說明含結晶度缺陷部45。 爲了方便說明，第2圖僅顯示從第1圖中之含氮化物 半導體之結構20拆解下來之第一氮化物半導體層40。在 第2圖中，亦省略含結晶度缺陷部45。第2圖描繪第一氮 化物半導體層之凸出部42、第一氮化物半導體層之凹陷部 43及第一氮化物半導體層之凹陷部的底面44。 在此所稱之含結晶度缺陷狀態意指一狀態，其中在含 -18- 201006973 結晶度缺陷部45中，其之結晶狀態爲從第一氮化物半導 體層40之內部的單晶體狀態變更之狀態。 例如，含結晶度缺陷部4 5處於非晶質狀態、多孔狀 態或多晶體狀態。 在第1圖中，含結晶度缺陷部45爲第一氮化物半導 體層40之凹陷部的內壁之整個表面，但第2圖中僅顯示 整個表面的部份，如底面44或側壁46。 當含結晶度缺陷部45之厚度從單一原子層厚度至數 百奈米，可帶出部45的效果；較佳所關心之厚度從單一 原子層厚度至數十奈米。 含結晶度缺陷部45之薄膜厚度可爲均勻或不均勻。 尤其，側壁44及底面44不需爲含結晶度缺陷部45之相 同厚度。 含結晶度缺陷部45之角色爲減少在其表面上氮化物 半導體之形成速率。 此一角色之結果爲可確保空隙62的大小。 接下來，說明形成在第一氮化物半導體層之凹陷部上 的半導體51。形成在第一氮化物半導體層之凹陷部上的氮 化物半導體51之薄膜厚度取決於含結晶度缺陷部45之形 成條件或薄膜形成條件可爲不均勻。 詳言之，在側壁44及底面44上，形成在第一氮化物 半導體層之凹陷部上的氮化物半導體51之薄膜厚度可爲 不同。 形成在第一氮化物半導體層之凹陷部上的氮化物半導 -19- 201006973 體51之薄膜厚度可爲’在其整個表面或部分上，薄如單 一原子層厚度或更少或薄到可忽略。在有含結晶度缺陷部 45的位置’形成在第一氮化物半導體層之凹陷部上的氮化 物半導體51之薄膜厚度特別薄。 在本實施例中，爲了確保空隙62的大小，形成在第 一氮化物半導體層之凹陷部上的氮化物半導體51之薄膜 厚度越薄越好。 接下來，說明空隙62。 空隙62係形成在第一氮化物半導體層40之凹陷部43 及第二氮化物半導體層50間的空隙。 空隙62數量超過一，且等於或小於凹陷部43的數量 〇 從第1及2圖中可見，當含結晶度缺陷部45之厚度 及形成在第一氮化物半導體層之凹陷部上之氮化物半導體 51的厚度皆夠薄時，空隙62的大小大略由凹陷部43的大 小而定。 爲了確保第二氮化物半導體層50之薄膜品質，第一 氮化物半導體層之凹陷部43較佳以週期性方式分布。 此外，針對第一氮化物半導體層之凹陷部43，個別凹 陷部之大小較佳大略互相相等。 第一氮化物半導體層之凹陷部43之圖案從薄膜形成 表面上看去爲例如一組週期性配置之平行溝渠或一組週期 性配置的獨立孔。第一氮化物半導體層之凹陷部43的內 壁（包括側壁46及底面44)不需爲平坦且滑順。 201006973 此外，第一氮化物半導體層之凹陷部43的側壁46不 需爲垂直。第一氮化物半導體層之凹陷部43的大小可根 據第一氮化物半導體層之凹陷部43的圖案形狀、第一氮 化物半導體層40的薄膜厚度U及第二氮化物半導體層的 薄膜厚度t2而最佳化。 藉由舉例來說明第一氮化物半導體層之凹陷部43的 大小，其中圖案爲一組週期性配置的平行直線溝渠。 設定溝渠之每一個的長度使溝渠跨過意圖發生生長的 區域。例如，當意圖發生生長的區域的直徑爲2英吋0， 溝渠之每一個的長度設定爲最大2英吋。 如第2圖中所示，溝渠之週期、寬度及深度分別由Pl 、以1及di表示。當^>50奈米（nm)時，需滿足下列關 係：20 nm<pi<10ti，10 nm<wi<pi > 0.2wi<di<ti » t2>W] ° 例如，當ti = 8微米（μπι)時，需滿足下列關係：1 μιη<ρι<20μιη，10 0 nm<wi<pi，20 nm<d ι <8 μιη > t2> 2 0 0 nm 。舉另一特定範例，需要滿足下列關係：tl = 8pm、 ρι = 10μιη、w ι = 7 μιη ' d ι = 6 μιη ' Ϊ2=1〇μιη。 在此情況中，所得之空隙62具有約7μιη之寬度及 3 μιη或更多之深度。 空隙62可緩和第一氮化物半導體層40及第二氮化物 半導體層50之間的應變應力。 尤其，當這些氮化物半導體層40及50的材料互相不 同時’空隙62的效果更顯著。因此，在含氮化物半導體 之結構20中，可減少第二氮化物半導體層50中應變應力 -21 - 201006973 造成的變形或缺陷，尤其，在第二氮化物半導體層50的 表面上。 在第1圖中所示之含氮化物半導體之結構20中，第 一氮化物半導體層40及第二氮化物半導體層50可互相爲 同質，或互相爲絕對異質。此外，可分別由氮化物半導體 膜所形成之多層膜形成這些氮化物半導體層40及50。 在此所稱之氮化物半導體意指例如由通式AlxGayIni.x_yN ( OSxSl、OSySl、OS x + y S1)表示之氮化鎵化合物半 導體。 其典型範例包括GaN、AlGaN、InGaN、A1N及InN。 此外，在第1圖中所示之含氮化物半導體之結構20 僅由第一氮化物半導體層40及第二氮化物半導體層50形 成，但可藉由層壓此一結構複數次而形成。在此一情況中 ，在上層部，圍繞空隙之壁會無含結晶度缺陷部。 含氮化物半導體之結構20可單一用爲光學元件之材 料。 含氮化物半導體之結構20亦可用爲氮化物半導體膜 之磊晶生長的基底。 此外，含氮化物半導體之結構20亦可以附接至另一 基底的方式加以使用。 可藉由將在第四實施例中所述的製造方法製造本實施 例之含氮化物半導體之結構20。 (第二實施例） -22- 201006973 作爲本發明之第二實施例，說明含氮化物半導體層複 合基底之一範例。 第3圖顯示描繪本實施例中之含氮化物半導體層複合 基底的一範例之不意剖面圖。 第3圖描繪基礎基底10、基礎基底之凸出部12、含 氮化物半導體層複合基底30、形成在基礎基底之凹陷部中 的氮化物半導體41及在基礎基底與氮化物半導體之間的 空隙6 1。 本實施例中之含氮化物半導體層複合基底30係由基 礎基底10及含氮化物半導體之結構20所形成。 基礎基底10及結構20可互相連結而在其間無任何間 隔。當藉由晶體生長在基礎基底10上形成結構20時，爲 了確保結構20的品質，較佳在基礎基底10及結構20之 間形成空隙。舉例而言，在第3圖中所示之含氮化物半導 體層複合基底30中，在基礎基底10及結構20之間形成 空隙6 1。 接下來，由於含氮化物半導體之結構20與第一實施 例中的相同，此後參照第3及4圖，僅說明基礎基底10 及空隙6 1。 第4圖爲僅顯示從第3圖中所示之含氮化物半導體層 複合基底30拆下來之基礎基底10的圖。 第4圖描繪基礎基底之凸出部12、基礎基底之凹陷部 、基礎基底之凹陷部的底面14及基礎基底之凹陷部的側 壁16 〇 -23- 201006973 首先說明基礎基底 基礎基底1〇可爲簡單的單晶體基底。 基礎基底10之材料例如爲典型有GaN、藍寶石、矽 (Si)及碳化矽（SiC)之氮化物半導體之的任一者。 在基礎基底10中，根據意圖目的，在簡單的單晶體 基底上，可進一步形成與單晶體基底同質或異質的中間膜 〇 此中間膜可爲多層膜。舉例而言’中間膜爲包括GaN 、AlGaN、InGaN、A1N及InN的至少任一者之單層膜或 多層膜。 此外，如第4圖中所示，可在基礎基底1〇之薄膜形 成表面上形成粗糙圖案。 當形成中間膜時，可形成粗糙圖案以到達中間膜之一 半位置或形成爲穿透中間膜以到達單晶體基底之內部。此 外，可在已形成粗糙圖案後形成中間膜。 基礎基底之凹陷部13的內壁（包括側壁16及底面14 )不需爲平坦且滑順。 此外，側壁16不需爲垂直，可爲錐形。形成凹陷部 之每一個的兩側壁1 6之傾斜角度不需互相相等。 接下來說明空隙6 1。 空隙61係形成在基礎基底1〇之凹陷部13與第一氮 化物半導體層40之間。 空隙61的數量超過一，且等於或小於凹陷部13的數 量。當基礎基底10及第一氮化物半導體層40互相在接介 -24- 201006973 處接合，空隙6 1的大小大略由凹陷部1 3的大小而定。 在藉由使用基礎基底10的粗糙圖案之橫向生長形成 氮化物半導體層40的情況中，如第3及4圖中可見，空 隙61的大小由凹陷部13的大小、氮化物半導體41的厚 度及基礎基底的凹陷部之側壁16上所形成之氮化物半導 體（未圖示）之厚度而定。 當基礎基底10爲由非氮化物半導體之材料形成之基 底時，基礎基底的凹陷部之側壁16上所形成之薄膜厚度 幾乎可忽略。 形成在基礎基底的凹陷部之側壁16上之氮化物半導 體41的厚度係由基礎基底10及第一氮化物半導體層40 之生長條件而定，且經常爲第一氮化物半導體層40之厚 度U的一半或更少。 爲了確保第一氮化物半導體層40之薄膜品質，凹陷 部13較佳以幾乎週期性的方式分布。 此外，針對凹陷部13,個別凹陷部之大小較佳大略互 相相等。凹陷部13之圖案從薄膜形成表面上看去爲例如 一組週期性配置之平行溝渠或一組週期性配置的獨立孔。 可根據凹陷部13的圖案形狀、基礎基底10的厚度t〇 及第一氮化物半導體層40之薄膜厚度^來最佳化凹陷部 1 3的大小。 藉由舉例來說明凹陷部13的大小，其中圖案爲一組 週期性配置的平行直線溝渠。 設定溝渠之每一個的長度使溝渠跨過意圖發生生長的 -25- 201006973 區域。例如，當意圖發生生長的區域的直徑爲2英吋0， 溝渠之每一個的長度設定爲最大2英吋。 如第4圖中所示，溝渠之週期、寬度及深度分別由P〇 、w〇及d〇表示。當t〇>100pm時，需滿足下列關係：20 ηιη<ρ〇<20μιη * 10 nm<w〇<p〇，0.2w〇<d〇<t〇，ti>w〇。舉另一 特定範例，需要滿足下列關係：t〇 = 420pm、ρ〇 = 10μιη、 w〇 = 7μπι ' ά〇 = 6μιη ' ΐι = 10μηι。 在此情況中，所得之空隙61具有約7μίη之寬度及 3μιη或更多之深度。 空隙61之存在能夠緩和氮化物半導體20及基礎基底 10之間的應變應力。此外，當藉由使用基礎基底上之粗糙 圖案的橫向生長形成第一氮化物半導體層40而非當第一 氮化物半導體層40藉由直接生長而形成於平坦基礎基底 上時，可更減少第一氮化物半導體層40中之穿線型錯位 密度。 可藉由在第三實施例中所示之製造方法製造本實施例 之含氮化物半導體層複合基底30。 (第三實施例） 作爲本發明之第三實施例，說明含氮化物半導體層複 合基底之製造方法的一範例。 第5Α至5F圖顯示描繪在本實施例中之含氮化物半導 體層複合基底之製造方法的一範例之示意剖面圖。 在複合基底之製造中，首先準備基礎基底1〇(第5Α 201006973 圖）。 基礎基底可爲簡單的單晶體基底。基礎基 料例如爲典型有GaN、藍寶石、矽（Si)及插 )之氮化物半導體之的任一者。 在基礎基底10中，根據意圖目的，在簡 基底上，可進一步形成與單晶體基底同質或異 (未圖示）。 此中間膜可爲多層膜。舉例而言，中間膜j 、AlGaN、InGaN、A1N 及 InN 的至少任一者 多層膜。 接下來，如第5B圖中所示，可在基礎基垣 形成表面上形成粗糙圖案。當形成中間膜時， 圖案以到達中間膜之一半位置或形成爲穿透中 單晶體基底之內部。此外，可在已形成粗糙圖 間膜。 粗糙圖案之凹陷部1 3的內壁（包括側壁1 )不需爲平坦且滑順。 此外，側壁16不需爲垂直，可爲錐形。 之每一個的兩側壁16之傾斜角度不需互相相等 粗糙圖案係由眾所知週的微影技術及蝕刻 。微影技術之範例包括基於光微影技術之阻劑 術或電子束曝露技術。 根據需要，將阻劑圖案轉移至所謂的硬遮 薄膜或Si02薄膜。 底10之材 U匕矽（Sic 單的單晶體 質的中間膜 爲包括GaN 之單層膜或 Ξ 10之薄膜 可形成粗糙 間膜以到達 案後形成中 6及底面14 形成凹陷部 〇 技術所形成 圖案形成技 罩，如金屬 -27- 201006973 飩刻技術爲藉由藉由使用阻劑圖案或硬遮罩圖案作爲 遮罩之乾或濕蝕刻來處理基礎基底10之技術。 因而形成之基礎基底10的凹陷部13較佳以幾乎週期 性的方式分布。 此外，針對凹陷部1 3，個別凹陷部之大小較佳大略互 相相等。凹陷部13之圖案從薄膜形成表面上看去爲例如 一組週期性配置之平行溝渠或一組週期性配置的獨立孔。 可根據凹陷部13的圖案形狀、基礎基底1〇的厚度t〇 及第一氮化物半導體層40之薄膜厚度“來最佳化凹陷部 1 3的大小。 藉由舉例來說明凹陷部1 3的大小，其中圖案爲一組 週期性配置的平行直線溝渠。 設定溝渠之每一個的長度使溝渠跨過意圖發生生長的 區域。例如，當意圖發生生長的區域的直徑爲2英吋分’ 溝渠之每一個的長度設定爲最大2英吋。 如第5B圖中所示，溝渠之週期、寬度及深度分別由 p〇、及d〇表示。當ΐ〇>100μιη時，需滿足下列關係· 2〇 ηιη<ρ〇<20μιη，1 0 nm<w〇<p。，0.2w〇<d〇<t。’ ti>w〇。舉另一 特定範例，需要滿足下列關係：“ = 420μιη、PD=lMm、 \ν〇 = 7μιη、d〇 = 6μπι ' ΐι = 10μιη ο 根據需要，粗糙圖案之配置方向匹配基礎基β 10 51 結晶取向。 接下來，進行顯示於第5C圖中之形成第一氮化物半 導體層40之連續層的第一步驟。 -28- 201006973 在此情況中，在基礎基底ι〇及第一氮化物半導體層 40之間形成空隙6 1。第一氮化物半導體層40之材料例如 爲由通式 AlxGayln^x.yN ( OSxS 1、OSyS 1、〇Sx + yS 1 )表示之氮化鎵化合物半導體。 其典型範例包括GaN、AlGaN、InGaN、A1N及InN。 第一氮化物半導體層40可藉由基底接介來接合至基礎基 底10 » φ 在此所稱之基底接介意指例如包括表面活化步驟及加 熱密合步驟的接介。加熱溫度可從室溫至1 000 °c。 可藉由晶體生長在基礎基底10上形成第一氮化物半 導體40。晶體生長方法之範例包括金屬有機化學蒸汽沈積 方法（MOCVD方法）、氫化物蒸汽相壘晶方法（HVPE方 法）及分子束磊晶生長方法（MBE方法）。爲了減少第一 氮化物半導體層40中之穿線型錯位密度並形成空隙61， 較佳有優先進行第一氮化物半導體層40之橫向生長的晶 φ 體生長條件。 爲了進行優先橫向生長，基礎基底10之粗糙圖案的 配置方法預先與意圖結晶取向匹配。 在晶體生長的情況中，第一氮化物半導體之薄膜，由 形成在基礎基底之凹陷部上的氮化物半導體41代表，亦 形成於基礎基底10之凹陷部13的底面14上。 晶體生長條件例如爲下列目前爲止已知的MOCVD生 長條件。換言之，在MOCVD設備中，首先在3 0 0至700 亡的基底溫度生長數十奈米的氮化物半導體緩衝層。 -29- 201006973 在 GaN 的情況中，例如，三甲基鎵（ trimethylgallium; TMG)用作族 III 材料且氨（NH3)用作 族V材料。 接下來’增加基底溫度至約l〇〇(TC，進行氮化物半導 體之橫向生長。 例如’形成ΙΟμιη厚的GaN薄膜。在此情況中，TMG 及NH3用作材料。當意圖引進雜質時，將適當氣體引進薄 膜形成設備中。例如，作爲GaN之施體氣體，矽烷爲適當 〇 藉由橫向生長，獲得第一氮化物半導體層40之連續 層，其爲完全平坦，且其中在其表面附近之穿線型錯位密 度在基礎基底之凹陷部13的上區域中爲減少。 在其中穿線型錯位密度爲減少之第一氮化物半導體層 40的區域中，穿線型錯位密度變成ixl〇8 Cm·2或更少。 此値比基礎基底之凸出部12上形成之氮化物半導體 的穿線型錯位密度低一量級或更多。 在上述晶體生長條件下，當 ρ〇=10μηι、·\ν〇 = 7μιη、 (1〇 = 6μιη、tflOpm，所得之空隙61具有約7μιη的寬度及 約3μη!或更多之深度。 接下來，如第5D圖中所示，進行在第一氮化物半導 體層40之連續層上形成粗糙圖案的第二步驟。 藉由目前已知的微影技術及蝕刻技術來形成連續層上 之粗糙圖案。微影技術之範例包括基於光微影技術或電子 束曝露技術之阻劑圖案形成技術。 -30- 201006973 根據需要，將阻劑圖案轉移至所謂的硬遮罩，如金屬 薄膜或Si02薄膜。 在形成深粗糙圖案的情況中特別需要使用硬遮罩。 蝕刻技術爲藉由藉由使用阻劑圖案或硬遮罩圖案作爲 蝕刻遮罩（未圖示）之乾或濕蝕刻來處理第一氮化物半導 體層40之技術。乾鈾刻例如爲使用反應性氣體之電漿的 乾蝕刻。 反應性氣體爲單一氣體或包括兩或更多氣體之混合氣 體，且可根據第一氮化物半導體層40之成分最佳化。 例如，在其中第一氮化物半導體層40爲GaN層的情 況中，作爲主要反應性氣體，可使用含氯氣體（如C12、 BC13、SiCl4 )或含CH4之氣體。 當形成粗糙圖案之凹陷部43時，較佳盡可能移除在 第一氮化物半導體層40中穿線型錯位密度相對高的部份 〇 這能夠在後續氮化物半導體之薄膜形成中獲得缺陷密 度更爲減少之薄膜。 穿線型錯位密度爲高之部分係例如位在基礎基底10 之凸出部12上。當形成第一氮化物半導體層40的飩刻遮 罩時，適當進行遮罩形狀之設計及在光微影時的定位能夠 形成上述粗糙圖案之凹陷部43。 取決於凹陷部43之圖案形狀、第一氮化物半導體層 40之薄膜厚度tl及稍後形成之第二氮化物半導體層50的 薄膜厚度t2可最佳化粗糙圖案之凹陷部43的大小。 -31 - 201006973 藉由舉例來說明粗糙圖案之凹陷部43的大小，其中 圖案爲一組週期性配置的平行直線溝渠。 設定溝渠之每一個的長度使溝渠跨過意圖發生生長的 區域。例如，當意圖發生生長的區域的直徑爲2英吋0 ’ 溝渠之每一個的長度設定爲最大2英吋。 如第5D圖中所示，溝渠之週期、寬度及深度分別由 Pi、Wi及di表示。當ti>50奈米（nm)時，需滿足下列 關係：20 nm<pi<10ti > 10 nm<wi<pi > Ο . 2 w i <d i <t ι 5 t2> w i o 例如，當 tplOpm 時，需滿足下列關係：1 μιη<ρ ι <20μιη， 10 0 nm<wι <ρ ι > 10 0 nm<di <8 μιη，t2>2 00 nm。舉另一特定範例，需要滿足下列關係：tl = 8pm、 ρ ι = 1 0 μιη ' w ι = 7 μιη ' d ι = 6 μιη ' t2=l〇pm。 接下來，如第5E圖中所示，進行在第一氮化物半導 體層40之連續層中形成含結晶度缺陷狀態的第三步驟。 具有含結晶度缺陷狀態之部分45係至少部分形成在 粗糙圖案之凹陷部43的內壁。 在第5E圖中，具有含結晶度缺陷狀態之部分45係形 成在粗糙圖案之凹陷部43的內壁的整個表面上，但可僅 形成在粗糙圖案之凹陷部43的一部份上，如僅在第5D圖 中所示之底面44上或僅在側壁46上。 具有含結晶度缺陷狀態之部分45可爲可爲均勻或不 均勻。 尤其，側壁44及底面44相較於具有含結晶度缺陷之 -32- 201006973 部分45的厚度不需爲相同。 具有含結晶度缺陷之部分45之角色爲減少在其表面 上氮化物半導體之形成速率。 作爲具有含結晶度缺陷之部分45的形成方法，施加 基於如反應性如離子蝕刻（RIE )、電漿蝕刻、離子輻射 或中子束輻射之技術的表面處理以從單晶體狀態變更所關 心之部分。 φ 在變更後所關心之部分的狀態可從單晶體狀態變更成 例如非晶質狀態、多孔狀態或多晶體狀態。 在表面處理時，以遮罩（未圖示）保護不想變更之部 分。 上述保護遮罩可爲藉由第二步驟中所述的蝕刻遮罩之 形成方法新形成的，或蝕刻遮罩本身即可作爲保護遮罩。 可由上述表面處理條件及表面處理時間來控制部分45之 厚度，且從單一原子層厚度變化至數百奈米。 φ 接下來，進行第5F圖中所示之形成第二氮化物半導 體層50之第四步驟。 在此情況中，空隙62係形成在第二氮化物半導體層 . 50及第一氮化物半導體層40間。 第二氮化物半導體層之材料例如爲由通式AlxGayIni.x.yN (OSxSl、OSySl、〇Sx + ySl)表示之氮化鎵化合物 半導體。 其典型範例包括GaN、AlGaN、InGaN、A1N及InN。 第二氮化物半導體層50及第一氮化物半導體層40可互相 -33- 201006973 爲同質或互相絕對異質。此外’第二氮化物半導體層50 可由多層膜形成。 第二氮化物半導體層50之形成方法與第一步驟中所 述之第一氮化物半導體層40的晶體生長方法類似’且爲 主要用眾所皆知的MOCVD之橫向生長。 與第二氮化物半導體層50之橫向生長同時地’亦可 在第一氮化物半導體層之凹陷部43內部中形成氮化物半 導體51。 取決於含結晶度缺陷部45的形成條件或薄膜形成條 件，氮化物半導體51的薄膜厚度可爲不均勻。 尤其，在如第5D圖中所示之側壁46及底面44上， 氮化物半導體51的薄膜厚度可爲不均勻。 含結晶度缺陷部45之存在減少，在內壁43上，尤其 ，在側壁46上，氮化物半導體之形成速率，使氮化物半 導體51之薄膜厚度可適需要忽略地薄。因而確保空隙62 之大小。所得之空隙62，舉例而言，具有約7μιη之寬度 及3 μπι或更多之深度，當第二氮化物半導體層50之薄膜 厚度t2設定成ί2=10μιη。由此一橫向生長所形成之第二氮 化物半導體層50的薄膜之穿線型錯位密度爲3χι 〇7 cin·2 或更少。此値比基於在無形成粗糙圖案的第一氮化物半導 體層40上直接生長的氮化物半導體之穿線型錯位密度更 低。 在第一氮化物半導體層50之晶體生長過程中，含結 晶度缺陷部45之一部分因重新結晶而變成多晶體，但不 -34- 201006973 會變成與凸出部42 —體之單晶體。 空隙62可緩和第一氮化物半導體層40及第二氮化物 半導體層50間的應變應力。尤其’當第一氮化物半導體 層40之材料及第二氮化物半導體層50之材料互相不同時 ，此緩和較果很顯著。 因此，空隙62之存在’與基礎基底對於第一氮化 物半導體層40的影響相比，大幅減少基礎基底10對於第 二氮化物半導體層50的影響。 因而在第二氮化物半導體層50中’可減少因應變應 力造成之變形及缺陷。 根據本實施例，得以製造本發明中之含氮化物半導體 的複合基底。 作爲本發明之第四實施例，說明含氮化物半導體的結 構之製造方法的一範例。 本實施例中之含氮化物半導體的結構20之製造方法 的特徵在於包括：製造含氮化物半導體的複合基底30之 步驟、以及移除複合基底30之基礎基底之步驟。 已在第三實施例中說明複合基底30之製造方法，因 此在此省略。此後說明移除基礎基底及其他之步驟。 可利用材料間之抗蝕刻程度差以選擇性蝕刻來移除基 礎基底10。 例如，當基礎基底1〇之材料爲Si時，可藉由以KOH 僅溶解Si來移除基礎基底10。 當以相對溶液拋光之材料形成基礎基底10時，可胃 -35- 201006973 由拋光來移除基礎基底1〇。 當基礎基底10包括可用選擇性蝕刻移除的中間膜時 ，可藉由選擇性飩刻移除中間膜來移除基礎基底10。 當基礎基底10爲以諸如GaN或藍寶石的透明基底製 成時，亦可藉由目前已知的雷射剝離（亦稱爲LLO )來移 除基礎基底1〇。 此外，當基礎基底1〇爲透明基底時，可藉由目前已 知的光電化學鈾刻選擇性移除中間膜來移除基礎基底1 〇。 例如，當基礎基底10以GaN或藍寶石製成時，InGaN可 作爲中間膜。 可用發出基礎基底10不實質上吸收的燈或雷射來做 爲光源，如Xe-Hg燈。可使用例如KOH的水溶液來做爲 蝕刻溶液。 此外，可在複合基底30已經附接至適當的第二基底 時移除基礎基底10。附接方法的範例包括使用蠘或樹脂之 接介方法及包括表面活化步驟與加熱密合步驟的直接接介 方法。 此後，參照第6A至6D圖’詳細說明藉由LLO方法 基礎基底10之移除。 利用第二實施例中說明之含氮化物半導體的複合基底 3 0來舉例說明。 第6A圖顯示在進行處理前含氮化物半導體的複合基 底30。 第6B圖顯示電磁波輻射步驟。電磁波實質上不被基 -36- 201006973 礎基底10所吸收，但會被第一氮化物半導體層40之第一 氮化物半導體層所吸收，且例如爲雷射光。 例如，當基礎基底10係由藍寶石製成且第一氮化物 半導體層40係由GaN製成時，具有370· nm或更短之振盪 波長之雷射光爲較佳。可使用之雷射的範例包括下列準分 子雷射：ArF(193 nm ) ' KrF ( 248.5 nm )及 XeCl(308 nm ) ° _ 電磁波輻射時間僅需爲允許分解第一氮化物半導體層 40並藉此移除基礎基底10，且藉由根據電磁波的種類適 當調節輻射時間來進行輻射。 作爲輻射方法，如第6B圖中所示，可以雷射光沿方 向70從基礎基底1〇之後面輻射整個區域。 替代地，移動其上放置基底之xy台，並最終可將雷 射從基礎基底10之後面輻射至整個區域。 藉由電磁波輻射，如第6B圖中所示，其中氮化物半 φ 導體已被分解的部分71及72分別形成在與基礎基底1〇 的凹陷部之底面的介面及與基礎基底10的凸出部之頂面 的介面上。 例如，當第一氮化物半導體層40係由GaN製成， GaN分解成Ga及N2，因此其中氮化物半導體已被分解的 部分71及72主要由Ga形成。 N2氣體爆炸性地擴散於空隙61中。若無空隙61，N2 氣體之爆炸性擴散會在第一氮化物半導體層40中產生大 量的微裂縫。 -37- 201006973 空隙61之存在提供N2氣體散逸路徑，並因此能大幅 減少微裂縫的產生。 因此，可減少基底之移除對含氮化物半導體之結構20 造成的破壞。 電磁波輻射之結果爲在含氮化物半導體之結構2〇與 基礎基底10之間的接觸介面中的連結以Ga爲主。 即使僅施加一點力量就可移除基礎基底10，產生如第 6C圖中所示之結構。可使用如此製造出的含氮化物半導 體之結構20。根據需要，進行下列額外的程序1至3。 在額外程序1中，移除附接至含氮化物半導體之結構 20之表面的Ga及類似者。爲此，以稀釋的鹽酸進行清洗 〇 在額外的程序2中，如第6C圖中所示，在與第一氮 化物半導體層40及基礎基底10接觸之介面中之第一氮化 物半導體層40側上形成凹部47。此時，電磁波輻射造成 之破壞仍保留在第一氮化物半導體層40中之凹部47中。 根據基於剖面傳輸電子顯微鏡（TEM)方法或魯塞佛 (Rutherford )回散射（RBS )方法之分析，取決於電磁 波輻射情況，可見到破壞被侷限於自介面500 nm之深度 〇 此破壞層之移除幾乎排除因基底移除對含氮化物半導 體之結構20造成的破壞。 移除第一氮化物半導體層中之凹部47的方法之範例 包括機械拋光、化學機械拋光（CMP )、離子碾磨及氣體 201006973 叢集離子束（GCIB)蝕刻。 在額外的程序3中，如第6D圖中所示，當意圖平面 化第一氮化物半導體層40之表面或意圖調節第一氮化物 半導體層40之薄膜厚度時，藉由用來移除第一氮化物半 導體層之凹部47的相同方法來使第一氮化物半導體層40 之表面變平。 因此，可獲得具有平坦之底面的含氮化物半導體之結 ❹ 構20。 根據本實施例，可實現本發明中之含氮化物半導體之 結構的製造。 此後說明本發明之範例。 <範例1> 在範例1中，參照第1及2圖說明已在第一實施例中 說明之含氮化物半導體之結構的一特定範例。 φ 省略與在第一實施例中說明過之部分重疊的部分之說 明。 在本範例中，第一氮化物半導體層40及第二氮化物 半導體層50皆爲GaN之單一晶體。 第一氮化物半導體層40之厚度q設定成t! = 8 μιη且 第二氮化物半導體層50之厚度t2設定成t2=10 μπι。含 GaN之結構20係由這些氮化物半導體層40及50以及在 這些氮化物半導體層40及50之間形成之空隙62所形成 ，且其特徵在於圍繞空隙62之壁的至少部分含有結晶度 -39- 201006973 缺陷。 在含結晶度缺陷部45中，其之結晶狀態自第一氮化 物半導體層40之內部（例如，部分42 )之單晶體狀態變 更。 含結晶度缺陷部45之結晶狀態包括至少一多晶體狀 態。 含結晶度缺陷部45之區域覆蓋幾乎第一氮化物半導 體層40之凹陷部45的內壁之整個表面。 含結晶度缺陷部45之厚度可從單一原子層至數百奈 米，且以原子層等級而言爲不均勻。 含結晶度缺陷部45之角色爲減少在其表面上氮化物 半導體之形成速率。此一角色之結果爲可確保空隙62的 大小。 形成在第一氮化物半導體層之凹陷部43上的氮化物 半導體51之薄膜厚度取決於含結晶度缺陷部45之薄膜形 成條件或形成條件可爲不均句。 例如，氮化物半導體51之薄膜厚度在側壁46上可忽 略地薄如數原子層厚，且在底面44上爲2 μπι或更少。 空隙62係形成在第一氮化物半導體層之凹陷部43及 第二氮化物半導體層50間。 空隙62數量超過一，且等於或小於第一氮化物半導 體層之凹陷部43的數量。 如第1及2圖中可見，空隙62的大小大略由凹陷部 43的大小及氮化物半導體51之厚度而定。 -40- 201006973 爲了確保第二氮化物半導體層50之薄膜品質，第一 氮化物半導體層之凹陷部43較佳以週期性方式分布。此 外，第一氮化物半導體層之個別凹陷部43之大小較佳大 略互相相等。 第一氮化物半導體層之凹陷部43之圖案從薄膜形成 表面上看去爲一組週期性配置之平行溝渠。 第一氮化物半導體層之凹陷部43的內壁（包括側壁 46及底面44 )以原子等級而言不平坦且滑順。 第一氮化物半導體層之凹陷部43的側壁46之傾斜角 度約爲85°。 第一氮化物半導體層之凹陷部43的大小如下。 溝渠之每一個的長度爲溝渠跨過2英吋0之基底，且 溝渠之每一個的長度最大爲2英吋。 如第2圖中所示，當溝渠週期爲Ρι = 10μπι、溝渠寬度 爲Wl=7pm及溝渠深度爲（Ιρόμιη時，所得之空隙62具有 約7μηι之寬度及4μιη或更多之深度。 空隙62能緩和第一氮化物半導體層40及第二氮化物 半導體層50間的應變應力。因此，在含氮化物半導體之 結構20中，可減少因應變應力造成之變形與缺陷。 可由如範例4中所述之製造方法製造本範例之含GaN 結構20。 <範例2> 在範例2中，參照第3及4圖說明已在第二實施例中 -41 - 201006973 說明之含氮化物半導體之複合基底的一特定範例。 省略與在第二實施例中說明過之部分重疊的部分之說 明。 在本範例中，含氮化物半導體的複合基底30係由以 藍寶石製成之基礎基底10及範例1中所述之含氮化物半 導體之結構20形成。 空隙61係形成在基礎基底10與結構20之間，且空 隙62係形成在第一氮化物半導體層40與第二氮化物半導 體層50之間。 ® 由於含氮化物半導體之結構20與範例1中的相同， 此後參照第3及4圖，僅說明基礎基底10及空隙61。 首先說明基礎基底10。 基礎基底10爲2英吋0藍寶石單晶體基底且其之厚 度t Q設定成t 〇 = 4 2 0 μ m。 如第4圖中所示，基礎基底1〇之薄膜形成表面爲C 平面，且週期性直線溝渠係以與基礎基底10之「11-20」 方向幾乎平行的方式形成。 設定溝渠之每一個的長度使溝渠跨過基礎基底10之 整個區域，且溝渠之每一個的長度最大爲2英吋。 設定溝渠週期爲Ρι = 10μηι、溝渠寬度爲wfJpm及溝 渠深度爲1 = 6μιη。 接下來說明空隙6 1。 空隙61係形成在基礎基底1〇之凹陷部13與第一氮 化物半導體層40之間。 -42- 201006973 空隙61的數量等於凹陷部13的數量。空隙61的大 小大略由凹陷部13及形成在凹陷部13之底面14上之氮 化物半導體41而定。 在凹陷部1 3之側壁1 6部分上所形成之氮化物半導體 的薄膜厚度幾乎可忽略。 氮化物半導體41之厚度爲3 μηι或更少。詳言之，空 隙61橫跨基礎基底10並聚有最大2英吋之長度、約7μιη 之寬度及約3μιη或更少之深度。 空隙61之存在能夠緩和互爲異質之氮化物半導體20 及藍寶石基礎基底10之間的應變應力。 此外，當藉由使用基礎基底上之粗糙圖案的橫向生長 來形成第一氮化物半導體層40而非當藉由直接生長而形 成第一氮化物半導體層40於平坦基礎基底上時，可更減 少第一氮化物半導體層40中之穿線型錯位密度。 可藉由範例3中所述之製造方法來製造本範例之含氮 化物半導體的複合基底30。 <範例3> 在範例3中，參照第5Α至5F圖說明已在第三實施例 中說明過之含氮化物半導體的複合基底的製造之一特定範 例。 省略與在第三實施例中說明過之部分重疊的部分之說 明。 首先準備基礎基底10。 -43- 201006973 第5A圖顯示藍寶石基礎基底10。基礎基底10之大 小爲2英吋0且其之厚度to設定成to = 4 2 0 μηι。基礎基底 10之薄膜形成表面爲C平面。 此外，如第5Β圖中所示，在基礎基底1〇之薄膜形成 表面上，週期性直線溝渠係以與基礎基底1 〇之「1 1 -20」 方向幾乎平行的方式形成。 可使用眾所週知的微影技術及蝕刻技術作爲形成方法 (未圖示）。 首先，在基礎基底1〇之薄膜形成表面上，藉由噴濺 沈積約300 nm之Cr薄膜。 接著，藉由光微影技術，在Cr薄膜上形成想要的阻 劑圖案。 在此情況中，進行遮罩與基底之定位使得直線溝渠配 置成與基礎基底之^ 11-2 0」方向幾乎平行。 接著，使用阻劑作爲蝕刻遮罩，且藉由具有包括氯（ Cl2 ) 、02及Ar的混合氣體施加RIE將圖案轉移至Cr薄 膜，並因此形成以Cr製成之硬遮罩。 接著，藉由施加氧電漿，拆離阻劑。藉由使用Cr硬 遮罩，並藉由施加具有含氯氣體之RIE，將藍寶實基底蝕 刻至想要的深度。 最後，用商業提供的Cr蝕刻劑來完全移除Cr硬遮罩 。在所得之直線溝渠圖案中，設定溝渠之每一個的長度使 溝渠跨過基礎基底之整個區域’並設定成最大爲2英 吋，且設定溝渠週期爲Ρ^ΙΟμιη、溝渠寬度爲^^μιη及 -44- 201006973 溝渠深度爲diWpm。 側壁46之傾斜角度約爲8 5 °。 接著，進行顯示於第5C圖中之形成第一氮化物半導 體層40之連續層的第一步驟。 在此情況中’空隙6 1係形成在基礎基底1 0及第一氮 化物半導體層40之間。第一氮化物半導體層40之材料爲 G aN 〇 藉由基於MOCVD之晶體生長在基礎基底10上形成 第一氮化物半導體層40。 爲了減少第一氮化物半導體層40中之穿線型錯位密 度並形成空隙6 1，在優先進行橫向生長之晶體生長條件下 形成第一氮化物半導體層40。 藉由晶體生長，在與第一氮化物半導體層40之形成 同時，由氮化物半導體41代表之GaN薄膜亦形成在基礎 基底10之凹陷部13的底面14上。 晶體生長條件爲例如目前已知的MOCVD生長條件。 詳言之，在MOCVD設備中，首先在500°C的基底溫度生 長數十奈米的GaN緩衝層。接著，增加基底溫度至約 1000 °C ’進行GaN之橫向生長以形成約ιομϊη厚的第一氮 化物半導體層40之GaN連續層。 當形成GaN連續層時，使用三甲基鎵（TMG )作爲族 III材料且使用氨（NH3 )作爲族V材料。 在此晶體生長條件下，氮化物半導體41之厚度爲 3 μιη或更少，且GaN幾乎不形成在基礎基底之凹陷部 -45- 201006973 的側壁1 6上。 詳言之，空隙61跨過基礎基底10並具有最大2英吋 之長度、約7μιη之寬度及約3μιη或更多之深度。 在第一氮化物半導體層40中由此種橫向生長所形成 之穿線型錯位密度低於藉由晶體生長形成在無粗糙圖案形 成之基底上所形成之GaN薄膜的穿線型錯位密度。 詳言之，在主要以晶體生長的第一氮化物半導體層40 之一部分中（例如，直接位在基礎基底之凹陷部13上方 的部份），穿線型錯位密度爲lxl〇8 cm_2或更少。 以原子力顯微鏡（AFM)或類似者來進行穿線型錯位 密度的評估。 接著，如第5D圖中所示，進行在第一氮化物半導體 層40之GaN連續層上形成粗糙圖案的第二步驟。 粗糙圖案係以與第5B圖中所示之藍寶石基底10上之 圖案幾乎平行的週期性直線溝渠所形成，且粗糙圖案之週 期與藍寶石基底1〇上圖案的相同。 詳言之，Ρ^ΡοΜΟμπι。然而，當形成粗糙圖案之凹陷 部43時，盡可能移除第一氮化物半導體層40之相對高穿 線型錯位密度部分。這在後續氮化物半導體之薄膜形成中 能獲得缺陷密度更減少之薄膜。換言之，凹陷部43之底 面44直接形成在基礎基底10的凸出部12上。 當形成第一氮化物半導體層40的蝕刻遮罩時，若適 當進行遮罩形狀之設計及在光微影時的定位，能夠輕易實 現上述。 -46- 201006973 使用皆知的微影技術及蝕刻技術（未圖示）來形成第 一氮化物半導體層40上之粗糙圖案。 例如，首先藉由使用剝離方法，在第一氮化物半導體 層40之上表面上形成約500 nm厚的Ni圖案。 接著，藉由使用Ni圖案作爲硬遮罩，並藉由施加具 有包括Cl2及BC13或類似者之混合氣體的RIE，將第一氮 化物半導體層40蝕刻至想要的深度。最後，以FeCl2的 3.5%水溶液作爲鈾刻劑藉由加熱至約50°C來完全移除Ni 硬遮罩。 設定所得直線溝渠圖案的溝渠之每一個的長度，使溝 渠跨過基礎基底10之整個區域，且溝渠之每一個的長度 設定爲最大2英吋。設定溝渠週期爲Ρι = 10μιη、溝渠寬度 爲wpTpm及溝渠深度爲（Ι^όμιη»側壁16之傾斜角度約 爲 85°。 接下來，如第5Ε圖中所示，進行在第一氮化物半導 體層40中形成含結晶度缺陷狀態的第三步驟。 作爲形成具有含結晶度缺陷狀態的部分45之方法， 藉由例如Ar離子輻射，將第一氮化物半導體層之凹陷部 43的內壁之整個表面轉變成非晶體狀態。 可藉由Ar離子加速度能量及Ar離子輻射時間來控制 含結晶度缺陷部45之厚度，從單一原子層厚度至數百奈 米，且無需爲均勻。 接下來，進行如第5F圖中所示之形成第二氮化物半 導體層50之連續層的第四步驟。在此情況中，空隙62係 -47- 201006973 形成在第二氮化物半導體層50及第一氮化物半導體層40 間。 第二氮化物半導體層之材料例如爲單晶體GaN。 第二氮化物半導體層50之形成方法與第一步驟中所 述之第一氮化物半導體層40的晶體生長方法類似’且爲 主要用眾所皆知的MOCVD之橫向生長。 然而，在此情況中，低溫緩衝層之形成變得不必要。 與第二氮化物半導體層50之橫向生長同時地，亦可 在第一氮化物半導體層40之凹陷部43內部中形成氮化物 半導體51。 取決於含結晶度缺陷部45的形成條件或薄膜形成條 件，氮化物半導體51的薄膜厚度可爲不均勻。 含結晶度缺陷部45之存在減少，在內壁上，尤其係 在第一氮化物半導體層之凹陷部43的側壁46上，GaN之 形成速率。 因此，可確保空隙62之大小。 當第二氮化物半導體層50之薄膜厚度t2設定成 t2=10pm時，所得之空隙62具有約6μιη之寬度及3μιη或 更多之深度。 由此一橫向生長所形成之第二氮化物半導體層50的 薄膜之穿線型錯位密度爲lxlO7 cm·2或更少。 此値比基於在無形成粗糙圖案的第一氮化物半導體層 4〇上直接生長的氮化物半導體之穿線型錯位密度更低。 空隙62能緩和第一氮化物半導體層40及第二氮化物 -48- 201006973 半導體層5 0間的應變應力。 因此，與基礎基底10對於第一氮化物半導體層40的 影響相比，大幅減少基礎基底10對於第二氮化物半導體 層50的影響。 因而在第二氮化物半導體層50中，可減少因應變應 力造成之變形及缺陷。 根據本範例，可實現在本發明中之含氮化物半導體的 複合基底的製造。 <範例4> 在範例4中，參照第6Α及6D圖說明已在第四實施 例中說明之含氮化物半導體之結構20的製造之一特定範 例。 省略與在第四實施例中說明過之部分重疊的部分之說 明。 含氮化物半導體之結構20的製造方法之特徵在於包 括製造含氮化物半導體的複合基底30之步驟及移除複合 基底30的基礎基底10之步驟。 已在範例3中描述複合基底3 0之製造方法，因此在 此省略其之說明。此後，說明移除藍寶石基礎基底之 步驟及其他步驟。 藉由目前已知的LLO方法來進行基礎基底10之移除 〇 第6Α圖顯示在進行LLO處理前含GaN的複合基底 -49- 201006973 30 ° 第6B圖顯示電磁波輻射步驟。 電磁波爲例如KrF準分子雷射光，且其波長爲248.5 nm、其能量密度約爲600 mJ/cm2且其雷射脈衝寬度約爲 20 ns。從藍寶石基底側70進行雷射輻射。 將複合基底30放置在xy台上，並移動台來進行輻射 ，以從基礎基底1〇之內部分的周邊部分均勻地進行輻射 。根據基礎基底1〇之剝蝕情況來最佳化移動速度。 如第6B圖中所示，電磁波輻射分別在與基礎基底10 的凹陷部之底面的介面及與基礎基底1〇的凸出部之頂面 的介面上形成其中氮化物半導體GaN被分解之部分71及 72 ° 在此情況中，GaN分解成0&及N2，因此其中氮化物 半導體已被分解的部分71及72主要由Ga形成。 N2氣體爆炸性地擴散於空隙61中。若無空隙61，N2 氣體之爆炸性擴散會在第一氮化物半導體層40中產生大 量的微裂縫。 空隙61之存在提供N2氣體散逸路徑，並因此能大幅 減少微裂縫的產生。因此，空隙61之存在可減少基底之 移除對含氮化物半導體之結構20造成的破壞。 在LLO之後，在結構20與基礎基底10之間的接觸 介面中的連結以Ga爲主。即使僅施加一點力量就可移除 基礎基底10，產生如第6C圖中所示之結構。 接著，移除附接至結構20之表面的Ga及類似者。爲 -50- 201006973 此，以稀釋的鹽酸進行清洗。 接著’如第6C圖中所示，移除第一氮化物半導體層 40側之凹部47。在凹部47中，仍保留LLO造成之破壞 〇 破壞層之深度約爲500 nm之深度。可使用Ar離子碾 磨作爲移除凹部47之方法。 接著，如第6D圖中所示，平面化第一氮化物半導體 層40之表面並同時調整第一氮化物半導體層40之薄膜厚 度。 在此情控中，結合使用Ar離子碾磨及GCIB蝕刻。 尤其，GCIB對平面化特別有效。最後，以稀釋的鹽 酸清洗第一氮化物半導體層40之表面。 接著，獲得具有平坦底面之含氮化物半導體之結構20 〇 根據本範例之方法，可實現本發明之氮化物半導體之 結構。 <範例5> 在範例5中，說明已在本發明之實施例及範例中說明 之含氮化物半導體的複合基底的應用範例。 第7A至7G圖顯示描繪在本發明之實施例及範例中 說明之含氮化物半導體的複合基底的應用範例之示意剖面 圖。 首先，製造在第二實施例及範例2中所述之含氮化物 201006973 半導體的複合基底30。含氮化物半導體的複合基底30之 製造方法已描述於第三實施例及範例3中，故在此省略其 說明。 接著，如第7A圖中所示，藉由使用複合基底30作爲 基底來形成含氮化物半導體裝置結構層80。 裝置結構層80形成方法爲目前已知的MOCVD方法 。至於形成條件，可參考目前已知的條件。不在此做形成 條件的冗餘敘述。 裝置結構層80係例如由作爲第一層之氮化物半導體 層81、作爲第二層之氮化物半導體層82及作爲第三層之 氮化物半導體層83所形成。 每一層之結構與成分如下：201006973 VI. Description of the Invention: [Technical Field] The present invention relates to a structure including a nitride semiconductor layer, a composite substrate containing a nitride semiconductor layer, and a method of manufacturing the same. In particular, the present invention relates to a method of fabricating a nitride semiconductor layer based on epitaxial lateral overgrowth. [Prior Art] A nitride semiconductor such as a gallium nitride compound semiconductor represented by the general formula AlxGayIni-x-yN (〇SxSl, OSySl, OSx + ySl) has a relatively large band gap and is a direct transition type semiconductor material. Therefore, a nitride semiconductor is used as a material for forming a semiconductor light-emitting device, such as a semiconductor laser capable of emitting short-wavelength light corresponding to ultraviolet light to green light, and can cover a wide range from ultraviolet light to red light and additionally white light. The emission wavelength range and the light emitting diode (LED). In order to obtain a high quality semiconductor light emitting device, a high quality nitride semiconductor film or substrate is required. In particular, in order to obtain a high-quality nitride semiconductor film, epitaxial growth using a homogenous high-quality nitride semiconductor substrate or a heterogeneous substrate having a poor lattice constant and a relatively small difference in thermal expansion coefficient is preferably used. Further, in the application of a nitride semiconductor, it is necessary to remove the base substrate after forming a nitride semiconductor film or a nitride semiconductor structure as the case may be. However, there is a problem that it is difficult to manufacture a high quality nitride semiconductor film or a high quality nitride semiconductor substrate. Let's discuss the main cause of this problem. -5- 201006973 (The manufacturing procedure of the η nitride semiconductor substrate involves a high cost step. For example, when manufacturing a GaN substrate, high temperature and high pressure are required, and it is difficult to manufacture a substrate having a low defect density and a large diameter. Therefore, the GaN substrate is expensive. , and the smooth supply of GaN substrates that meet the mass production cannot be obtained. (2) Heterogeneous substrates suitable for epitaxial growth of high-quality nitride semiconductors are rare. They need to be at a high temperature of about 1000 °C and contain strong V-type materials. Epitaxial growth of a nitride semiconductor film in a corrosive ammonia environment. A heterogeneous single crystal substrate capable of withstanding such severe conditions is limited. (3) Depending on the device, a complex structure is required because of the crystal nature of the nitride semiconductor itself. For example, in order to realize an optical element, a nitride semiconductor having different compositions must be laminated into a plurality of layers. For the above reasons, in general, a sapphire substrate is often used as a base substrate of a nitride semiconductor. On the other hand, such as GaN, AlGaN And the nitride semiconductor of GalnN is a fully strained material having different lattice constants, and thus in these nitride halves Cracks and stress strains are easily generated between the bodies and between the nitride semiconductor and the substrate. Therefore, when a heterogeneous substrate such as a sapphire substrate is used, crystals which are proliferated in the nitride semiconductor due to the nitride semiconductor and the heterogeneous substrate may occur. The problem caused by the misalignment caused by the difference in lattice constant. This misalignment passes through the nitride semiconductor film to reach the uppermost layer of the nitride semiconductor, becomes threading misalignment, and may lower the properties of the nitride semiconductor film. In addition, there is a stress strain caused by a difference in thermal expansion coefficient between the nitride semiconductor film and the heterogeneous substrate due to a difference in thermal expansion coefficient between the nitrogen-6-201006973 compound semiconductor film and the heterogeneous substrate. The stress strain not only deforms the nitride semiconductor and the heterogeneous substrate, but also It is one of the factors that reduce the properties of nitride semiconductor films. In order to reduce the threading type misalignment density, Appl. Phys. Lett. is applied (No. 72, No. 16, April 20, 1988) , 2014 to 20 16), a method in which GaN is actively performed by lateral growth. Epitaxial growth. In this case, in the lateral growth method, which is also called epitaxial lateral overgrowth (ELOG) method, firstly, a region for promoting the growth of a nitride semiconductor and an interference with the growth of a nitride semiconductor are alternately formed on a heterogeneous substrate. And a nitride semiconductor is selectively grown on the growth promoting region, and the nitride semiconductor grows laterally toward the growth interference region. On the interference growth region, the nitride semiconductor is not grown from the substrate, and the interference growth region is covered by the promotion. A nitride semiconductor in which a nitride semiconductor extends laterally on the growth region. Therefore, a misalignment occurring in an interface between the substrate and the nitride semiconductor hardly occurs on the surface. Thus, the distribution of the thread-type dislocation density is formed in the nitride semiconductor formed by the lateral growth method. In particular, the threading type misalignment density remains high in the growth promoting region on the heterogeneous substrate, but the threading type dislocation density is lowered on the interference growth region on the heterogeneous substrate. According to this technique, a nitride semiconductor film which is completely flat and has a low threading type dislocation density near the surface in some regions can be obtained. 201006973 This technique provides a feature for achieving selective ELOG growth of a nitride semiconductor by utilizing a mask pattern formed on a base substrate. For example, SiO 2 can be used as the material of the mask pattern. In the Japanese Journal of Applied Physics (Jpn. J. Appl. Phys.) (Vol. 42, No. 2, No. 7B, July 15, 2003, L818 to L820), a further disclosure by using SiO 2 A technique in which a mask pattern ELOG is grown to form a two-layer structure of a thick film nitride semiconductor. Japanese Patent Application Publication No. 2007-3 14360 also discloses a selective growth technique for a nitride semiconductor film using a Mg compound as a material for a mask pattern. According to this technique, Mg contributes to lateral growth of the nitride semiconductor film, and thus a satisfactory nitride semiconductor film can be efficiently produced. A selective ELOG growth technique for nitride semiconductors is also disclosed in U.S. Patent No. 6,3 3 5,546, which does not use any masking pattern. According to this technique, even if a heterogeneous substrate made of a material such as sapphire is used, a nitride semiconductor film having a flat and low threading type dislocation density can be obtained. This effect has also been validated in the Journal of Light and Visual Environment (J. Light & Vis. Env_) (Vol. 27, No. 3 (2003), pp. 140-M5). This technique realizes selective ELOG growth of a nitride semiconductor film by utilizing a rough pattern formed on the growth surface of the substrate and having a feature of a space between the nitride semiconductor and the substrate in the pattern depressed portion. The presence of voids moderates the strain strain between the nitride semiconductor and the substrate to some extent. -8 - 201006973 In order to reduce the threading type misalignment, a technique is disclosed in which a first nitride semiconductor having a protruding and recessed surface (rough pattern) is provided, and then The epitaxial longitudinal and lateral overgrowth of the second nitride semiconductor is performed by using the upper surface and the side surface of the protruding portion as crystal nuclei; and when the depressed portion is filled with the nitride semiconductor, the nitride semiconductor also grows upward. According to this technique, the proliferation of the thread-type misalignment of the first nitride semiconductor in the portion above the portion where the second nitride semiconductor undergoes the epitaxial lateral @overgrowth is suppressed, and can be recessed in the depression A region where the threading type misalignment is moderated in the portion. In particular, a further reduction in threading type misalignment can be expected by repeated protrusion and depression surface formation and epitaxial longitudinal and lateral overgrowth. This technique has the feature that voids are formed in the second nitride semiconductor. On the other hand, also in the removal of the base substrate of the nitride semiconductor, there is often a problem of long operation time and destruction of the nitride semiconductor. φ These problems are particularly noticeable when using sapphire (which is hard) as the base substrate. A method of manufacturing a nitride-semiconductor substrate in which a nitride semiconductor substrate can be obtained by satisfactorily removing a heterogeneous substrate such as a sapphire substrate is disclosed in Japanese Patent Application Laid-Open No. Hei. No. Hei. According to this technique, a nitride semiconductor substrate which is free from defects and has a reduced misalignment and is satisfactory in crystallinity and surface conditions can be obtained. In this technique, a heterogeneous substrate is removed by decomposing a nitride semiconductor from electromagnetic wave radiation from a heterogeneous substrate side; this technique has a void formation between a nitride 9 - 201006973 semiconductor and a heterogeneous substrate to reduce the generated N 2 gas The characteristic of pressure on the destruction of nitride semiconductors. However, 'the above applied physical letters (72, 16 , April 20, 1998, 2014 to 2016), Japanese Eagle Physics Journal (Vol. 42, No. 2, No. 7B, 2003 7) The technique disclosed in the Japanese Patent Application Laid-Open No. 2007-314360, or the use of a material heterogeneous to a nitride semiconductor as a mask to achieve a selective ELOG of a nitride semiconductor film. Growing. Therefore, there is a problem in the technique that in a crystal growth process requiring a nitride semiconductor film of a TC growth temperature, the mask material is degraded to adversely affect the nitride semiconductor film. For example, a mask is formed therein. In the case where the material is SiO 2 , the composition Si or 〇 2, and in the case where the mask material is a Mg compound, the components Mg and others, diffused into the nitride semiconductor film, may adversely affect the nitride semiconductor depending on the situation. Quality or carrier control. On the other hand, the techniques disclosed in the Journal of Light and Visual Environments (Vol. 27, No. 3 (2 003), pp. 140-145) use rough patterns and overcome the use of heterogeneous materials. The problem of the mask, and at the same time, the relaxation of the stress strain between the nitride semiconductor film and the substrate is achieved. However, the formation of a void structure of only a single layer between the nitride semiconductor film and the substrate by using a rough pattern is insufficient to reduce the threading type misalignment. And alleviating stress and strain. As with this technique, it is not easy to form voids having two or more layers of the desired shape - 2010-06073. On the other hand, The technique disclosed in Japanese Patent No. 6,979,864 is capable of forming voids of two or more layers, but it is difficult to secure the void size because longitudinal growth and lateral growth occur simultaneously. Therefore, the influence of voids on the relaxation of stress and strain is low. The technique disclosed in Patent Application Publication No. 2001-1 7681 3 removes the base substrate by decomposing the lower layer, and the impact caused by the removal is transmitted to the nitride semiconductor directly overlying the lower layer. For example, it is produced in the lower layer. The micro-cracks are transferred to the nitride semiconductor directly overlying the underlying layer. Therefore, the technique disclosed in Japanese Patent Application Laid-Open No. Hei No. 2 00 1-1 76 813 can hardly avoid the formation of a nitride semiconductor when the base substrate is removed. In view of the above problems, it is an object of the present invention to provide a structure including a nitride semiconductor layer having reduced threading type misalignment, a composite substrate containing the nitride semiconductor, and a method of manufacturing the same. Further, another object of the present invention Is a method of manufacturing a structure including the nitride semiconductor layer, which reduces the removal of the base substrate The present invention provides a structure in which a nitride-containing semiconductor layer is formed, a nitride-containing semiconductor layer-containing composite substrate, and a method for producing the same. The nitride-containing semiconductor layer of the present invention is provided. The structure is characterized in that the structure comprises a stacked structure based on at least two nitride layers; the structure comprises a plurality of voids between the two nitride semiconductor layers in the laminated structure, and the -11 - 201006973 is included a wall surface of the inner wall of the depressed portion formed on the nitride semiconductor layer of the lower layer of the two nitride semiconductor layers; and a crystallinity-containing defect portion for suppressing lateral growth of the nitride semiconductor layer Formed on at least a portion of the inner walls of the recesses to form the voids. Further, the composite substrate containing the nitride semiconductor layer of the present invention is characterized in that the structure containing the nitride semiconductor layer is formed on the base substrate. In addition, the method for fabricating a nitride semiconductor layer-containing composite substrate of the present invention is characterized by comprising: a first step of forming a first nitride semiconductor layer on a base substrate, and forming a rough pattern on the first nitride semiconductor layer a second step of forming a third step containing a crystallinity defect portion due to a state changed from a single crystal state on at least a portion of an inner wall of the depressed portion in the rough pattern of the first nitride semiconductor layer, and And forming a second nitride semiconductor layer on the rough pattern including the crystallinity defect portion formed on the first nitride semiconductor layer. Further, the method for producing a structure of a nitride-containing semiconductor layer of the present invention is characterized by comprising the steps of manufacturing a composite substrate by using the method for producing a composite substrate according to any of the above-described methods, and manufacturing the same from the manufacturing method. The step of removing the base substrate from the composite substrate. According to the present invention, a structure including a nitride-type dislocation-reduced nitride semiconductor layer, a composite substrate containing the nitride semiconductor layer, and a method of manufacturing the same can be realized. Further, a manufacturing method of a structure including the nitride semiconductor layer can be realized, which reduces the destruction of the nitride semiconductor layer by the removal of the base substrate. [Embodiment] According to the present invention, the above structure can be realized as the structure of the above-described nitride-containing semiconductor layer. In an embodiment of the invention, the above structure can be configured as follows. In the present embodiment, the structure of the nitride-containing semiconductor layer is provided with a laminated structure based on at least two nitride semiconductor layers. The structure is included between the two nitride semiconductor layers in the stacked structure, a plurality of voids, which are formed by a rough pattern including the nitride semiconductor layer formed on the lower layer of the two nitride semiconductor layers The wall surface of the inner wall of the recess is surrounded. A crystallinity-containing defect portion which suppresses lateral growth of the nitride semiconductor layer is formed on at least a portion of the inner walls of the depressed portions to form the voids. Therefore, due to the voids, the film strain of the nitride semiconductor layer and the pressure between the two nitride semiconductor layers can be alleviated, and the reduction in the threading type misalignment density can be obtained. Due to the crystallinity-containing defective portion, the epitaxial lateral overgrowth of the nitride semiconductor in the depressed portion can be suppressed and the size of the void can be secured. The crystallinity-containing defect state here means a state changed from a single crystal state such as an amorphous state, a porous state, or a polycrystalline state. The nitride semiconductor referred to herein means a gallium nitride compound semiconductor represented by the general formula AlxGayIni_x-yN (OSxSl, OSySl, OSx + ySl). -13- 201006973 The structure of the nitride-containing semiconductor layer according to the present embodiment can realize a structure including a nitride semiconductor layer having a reduced type of misalignment. Therefore, a higher quality nitride semiconductor optical element can be realized. In an embodiment of the invention, the nitride-containing semiconductor layer composite substrate can be configured as follows. In the present embodiment, the nitride-containing semiconductor layer composite substrate can be configured by forming a structure containing a nitride-containing semiconductor layer on the base substrate. In this case, the nitride-containing semiconductor layer composite substrate may be configured to have a plurality of voids between the base substrate and the nitride semiconductor layer which is a lower layer of the two nitride semiconductor layers, which are included The wall surfaces of the inner walls of the recesses of the rough pattern formed on the nitride semiconductor layer of the lower layer are surrounded. The nitride-containing semiconductor layer composite substrate can also be configured by using a single crystal substrate as a base substrate. The nitride-containing semiconductor layer composite substrate can also be configured by using a base substrate as the base substrate, wherein an intermediate film which is homogenous or heterogeneous to the single crystal substrate is further formed on a single crystal substrate. The nitride-containing semiconductor layer composite substrate can also be configured by using any of a nitride semiconductor, sapphire, bismuth (Si), and bismuth carbide (Sic) as a material of a single crystal substrate. The above-described nitride-containing semiconductor layer composite substrate according to the present embodiment can configure a composite substrate containing a nitride-type dislocation-reduced nitride semiconductor layer, and thereby realize a substrate for epitaxial growth of a high-quality nitride semiconductor. -14 - 201006973 In an embodiment of the present invention, a method of manufacturing a composite substrate containing a nitride semiconductor layer can be configured as follows. A method of fabricating a nitride semiconductor layer-containing composite substrate according to the present embodiment includes: a first step of forming a first nitride semiconductor layer on a base substrate, and a second step of forming a rough pattern on the first nitride semiconductor layer Forming, in at least a portion of the inner wall of the depressed portion in the rough pattern of the first nitride semiconductor layer, a third step including a crystallinity defect portion due to a state changed from a single crystal state, and forming A fourth step of forming a second nitride semiconductor layer on the first nitride semiconductor layer and including the rough pattern containing the crystallinity defect portion. In this case, in the third step of forming a state containing crystallinity defects, a surface treatment based on a technique such as reactive ion etching (RIE), plasma etching, ionizing radiation or reactive ionizing radiation may be used. By applying these techniques, the portion of interest can be changed from a single crystal state to, for example, an amorphous state, a porous state, or a polycrystalline state. In an embodiment of the present invention, the first step may be to form the first nitride semiconductor by forming a rough pattern on the base substrate and performing lateral epitaxial overgrowth of the nitride semiconductor layer on the rough pattern. The step of successive layers of layers. Further, the fourth step may be a step of forming a continuous layer of the second nitride semiconductor layer by performing epitaxial lateral overgrowth of the nitride semiconductor layer. The manufacturing method of the nitride-containing semiconductor layer composite substrate may also be configured such that after the fourth step is performed once, the second step -15-201006973 is further repeated N times (N20), and the first step is repeated. Three steps (M2 N ). The above-described method for fabricating a nitride-containing semiconductor layer composite substrate according to the present embodiment can produce a composite substrate at a lower cost than a conventional nitride semiconductor and contribute to enlargement of the diameter of the substrate. The use of such a substrate as described above enables epitaxial growth of a high quality nitride semiconductor layer and enables realization of high quality optical components. The structure of the nitride-containing semiconductor layer can also serve as a substrate for epitaxial growth of a nitride semiconductor. © In an embodiment of the present invention, the base substrate can be removed from the composite substrate manufactured by the above-described manufacturing method, and the manufacturing method of the structure containing the nitride semiconductor layer can be configured as follows. The manufacturing method of the structure containing the nitride semiconductor layer according to the present embodiment includes the steps of manufacturing a composite substrate by using any of the above-described methods of manufacturing the composite substrate according to the embodiment of the present invention, and from the manufacturing method The step of manufacturing the composite substrate to remove the base substrate. In one embodiment of the invention, the method of fabricating the structure may also be configured such that in the step of removing the base substrate 'using a base substrate as the base substrate, wherein the single crystal substrate is further formed with a single crystal The substrate may be homogenous or heterogeneous interlayer film' and the method of fabricating the structure by selective etching may also be configured such that sapphire is used as the base substrate and from the base substrate in the step of removing the base substrate The side is subjected to laser irradiation, and the first nitride semiconductor layer is decomposed in an interface between the sapphire substrate and the nitride-containing semiconductor layer--16-201006973 structure. The method of fabricating the structure may also be configured such that in the step of removing the base substrate, a base substrate is used as the base substrate, wherein an intermediate film which is homogenous or heterogeneous with the single crystal substrate is further formed on the single crystal substrate, and The interlayer film is selectively removed by photoelectrochemical etching. Photoelectrochemical etching as referred to herein means an etching in which a substrate is immersed in an electrolytic solution and etched while an object to be etched is irradiated with external ultraviolet light. According to this method, the positive hole generated in the surface of the current shrinking layer by ultraviolet irradiation causes dissolution of the current shrinkage layer, thereby allowing etching. This etching is also known as PEC etching (photoelectrochemical etching). In an embodiment of the invention, the method of fabricating the structure may also be configured such that in the step of removing the base substrate, the nitride semiconductor layer-containing structure is bonded to the second substrate and then the foundation is removed Substrate. The above-described manufacturing method of the nitride-containing semiconductor layer composite substrate according to the present embodiment further promotes the removal of the base substrate of the nitride semiconductor, and can reduce the damage to the nitride semiconductor when the base substrate is removed. In this way, manufacturing costs can be reduced and an improvement in yield can be obtained. Hereinafter, these embodiments will be further described with reference to the drawings. It is noted that in the individual figures, the same symbols are used for the same elements, and thus the description of the redundant parts is omitted. (First Embodiment) As an example of the first embodiment of the present invention, an example of a structure of a nitride-containing semiconductor layer -17-201006973 will be described. Fig. 1 is a schematic cross-sectional view showing an example of the structure of the nitride-containing semiconductor layer in the present embodiment. Fig. 1 depicts a nitride-containing semiconductor structure 20, a first nitride semiconductor layer 40, a projection portion 42 of a first nitride semiconductor layer, and a crystallinity-containing defect portion 45 in the first nitride semiconductor layer. Fig. 1 also depicts a second nitride semiconductor layer 50, a nitride semiconductor 51 formed in a depressed portion of the first nitride semiconductor layer, and a void 62 in the nitride semiconductor structure. The nitride semiconductor-containing structure 20 of the present embodiment is composed of a first nitride semiconductor layer 40, a second nitride semiconductor layer 50, and a void 62 formed in the nitride semiconductor structure between the nitride semiconductor layers 40 and 50. A characteristic is that the crystallinity defect can be on at least a portion of the wall surrounding the void 62 in the nitride semiconductor structure. The portion containing the crystallinity defect is, for example, the surface of the inner wall of the first nitride semiconductor layer 40, as indicated by the crystallinity-containing defect portion 45 in the first nitride semiconductor layer. Next, the crystallinity-containing defect portion 45 will be described in more detail. For convenience of explanation, Fig. 2 only shows the first nitride semiconductor layer 40 which is removed from the nitride-containing semiconductor structure 20 in Fig. 1. In Fig. 2, the crystallinity-containing defect portion 45 is also omitted. Fig. 2 depicts the convex portion 42 of the first nitride semiconductor layer, the depressed portion 43 of the first nitride semiconductor layer, and the bottom surface 44 of the depressed portion of the first nitride semiconductor layer. The crystallinity-containing defect state referred to herein means a state in which the crystal state of the crystallinity defect portion 45 containing -18 to 201006973 is changed from the state of the single crystal state inside the first nitride semiconductor layer 40. . For example, the crystallinity-containing defect portion 45 is in an amorphous state, a porous state, or a polycrystalline state. In Fig. 1, the crystallinity-containing defect portion 45 is the entire surface of the inner wall of the depressed portion of the first nitride semiconductor layer 40, but only the portion of the entire surface such as the bottom surface 44 or the side wall 46 is shown in Fig. 2. When the thickness of the crystal-containing defect portion 45 is from a single atomic layer thickness to several hundred nanometers, the effect of the portion 45 can be brought about; preferably, the thickness of interest is from a single atomic layer thickness to several tens of nanometers. The film thickness of the crystallinity-containing defect portion 45 may be uniform or non-uniform. In particular, the side walls 44 and the bottom surface 44 need not be the same thickness as the crystallinity-deficient portion 45. The role of the crystallinity-containing defect portion 45 is to reduce the rate of formation of a nitride semiconductor on the surface thereof. The result of this role is to ensure the size of the void 62. Next, the semiconductor 51 formed on the depressed portion of the first nitride semiconductor layer will be described. The film thickness of the nitride semiconductor 51 formed on the depressed portion of the first nitride semiconductor layer may be uneven depending on the formation conditions of the crystallinity-containing defect portion 45 or the film formation conditions. In detail, on the side wall 44 and the bottom surface 44, the film thickness of the nitride semiconductor 51 formed on the depressed portion of the first nitride semiconductor layer may be different. The nitride semi-conductive -19-201006973 body 51 formed on the depressed portion of the first nitride semiconductor layer may have a film thickness "on its entire surface or portion, as thin as a single atomic layer or less or thinner ignore. The film thickness of the nitride semiconductor 51 formed on the depressed portion of the first nitride semiconductor layer at the position where the crystallinity-containing defect portion 45 is present is particularly thin. In the present embodiment, in order to secure the size of the void 62, the thinner the film thickness of the nitride semiconductor 51 formed on the depressed portion of the first nitride semiconductor layer, the better. Next, the gap 62 will be described. The void 62 is formed in a space between the depressed portion 43 of the first nitride semiconductor layer 40 and the second nitride semiconductor layer 50. The number of the voids 62 exceeds one and is equal to or smaller than the number of the depressed portions 43. As can be seen from FIGS. 1 and 2, the thickness of the crystal-containing defect portion 45 and the nitride formed on the depressed portion of the first nitride semiconductor layer are visible. When the thickness of the semiconductor 51 is sufficiently thin, the size of the void 62 is roughly determined by the size of the depressed portion 43. In order to ensure the film quality of the second nitride semiconductor layer 50, the depressed portions 43 of the first nitride semiconductor layer are preferably distributed in a periodic manner. Further, with respect to the depressed portion 43 of the first nitride semiconductor layer, the sizes of the individual depressed portions are preferably substantially equal to each other. The pattern of the depressed portions 43 of the first nitride semiconductor layer is, for example, a set of periodically arranged parallel trenches or a set of discrete holes of a periodic configuration as viewed from the film forming surface. The inner wall (including the side walls 46 and the bottom surface 44) of the depressed portion 43 of the first nitride semiconductor layer need not be flat and smooth. 201006973 Further, the side wall 46 of the depressed portion 43 of the first nitride semiconductor layer need not be vertical. The size of the depressed portion 43 of the first nitride semiconductor layer may be according to the pattern shape of the depressed portion 43 of the first nitride semiconductor layer, the film thickness U of the first nitride semiconductor layer 40, and the film thickness t2 of the second nitride semiconductor layer. Optimized. The size of the depressed portion 43 of the first nitride semiconductor layer is illustrated by way of example, wherein the pattern is a set of periodically arranged parallel straight trenches. The length of each of the ditches is set such that the ditches span the area where the growth is intended. For example, when the diameter of the region where growth is intended is 2 inches, the length of each of the trenches is set to a maximum of 2 inches. As shown in Fig. 2, the period, width and depth of the trench are represented by Pl, 1 and di, respectively. When ^>50 nm (nm), the following relationship must be satisfied: 20 nm <pi <10ti, 10 nm <wi <pi > 0.2wi <di <ti » t2>W] ° For example, when ti = 8 μm (μπι), the following relationship is required: 1 μιη <ρι <20μιη, 10 0 nm <wi <pi, 20 nm <d ι <8 μιη >t2> 2 0 0 nm. For another specific example, the following relationship needs to be satisfied: tl = 8pm, ρι = 10μιη, w ι = 7 μιη 'd ι = 6 μιη ' Ϊ2=1〇μιη. In this case, the resulting voids 62 have a width of about 7 μm and a depth of 3 μm or more. The void 62 can alleviate the strain stress between the first nitride semiconductor layer 40 and the second nitride semiconductor layer 50. In particular, when the materials of the nitride semiconductor layers 40 and 50 are different from each other, the effect of the void 62 is more remarkable. Therefore, in the structure 20 containing the nitride semiconductor, deformation or defects caused by the strain stress -21 - 201006973 in the second nitride semiconductor layer 50 can be reduced, particularly on the surface of the second nitride semiconductor layer 50. In the nitride semiconductor-containing structure 20 shown in Fig. 1, the first nitride semiconductor layer 40 and the second nitride semiconductor layer 50 may be homogenous to each other or may be absolutely heterogeneous to each other. Further, these nitride semiconductor layers 40 and 50 can be formed of a multilayer film formed of a nitride semiconductor film, respectively. The nitride semiconductor referred to herein means, for example, a gallium nitride compound semiconductor represented by the general formula AlxGayIni.x_yN (OSxSl, OSySl, OSx + y S1). Typical examples thereof include GaN, AlGaN, InGaN, AlN, and InN. Further, the nitride semiconductor-containing structure 20 shown in Fig. 1 is formed only of the first nitride semiconductor layer 40 and the second nitride semiconductor layer 50, but it can be formed by laminating this structure plural times. In this case, in the upper portion, there is no crystallinity-deficient portion around the wall of the void. The nitride-containing semiconductor structure 20 can be used alone as a material for an optical component. The nitride semiconductor-containing structure 20 can also be used as a substrate for epitaxial growth of a nitride semiconductor film. In addition, the nitride semiconductor-containing structure 20 can also be used in a manner that can be attached to another substrate. The nitride semiconductor-containing structure 20 of the present embodiment can be manufactured by the manufacturing method described in the fourth embodiment. (Second Embodiment) -22- 201006973 As an example of the second embodiment of the present invention, an example of a composite substrate containing a nitride semiconductor layer will be described. Fig. 3 is a cross-sectional view showing an example of the nitride-containing semiconductor layer composite substrate in the present embodiment. 3 depicts the base substrate 10, the base portion projections 12, the nitride-containing semiconductor layer composite substrate 30, the nitride semiconductor 41 formed in the recess portion of the base substrate, and the gap between the base substrate and the nitride semiconductor. 6 1. The nitride-containing semiconductor layer composite substrate 30 in this embodiment is formed of a base substrate 10 and a structure 20 containing a nitride semiconductor. The base substrate 10 and the structure 20 can be joined to each other without any separation therebetween. When the structure 20 is formed on the base substrate 10 by crystal growth, it is preferable to form a void between the base substrate 10 and the structure 20 in order to secure the quality of the structure 20. For example, in the nitride-containing semiconductor layer composite substrate 30 shown in Fig. 3, a void 61 is formed between the base substrate 10 and the structure 20. Next, since the structure 20 containing the nitride semiconductor is the same as that in the first embodiment, only the base substrate 10 and the void 61 are described hereinafter with reference to Figs. Fig. 4 is a view showing only the base substrate 10 detached from the nitride-containing semiconductor layer composite substrate 30 shown in Fig. 3. Figure 4 depicts the base 12 projection, the base base recess, the bottom surface 14 of the recess of the base substrate, and the sidewall of the recess of the base substrate. 〇-23- 201006973 First, the base substrate base can be described as Simple single crystal substrate. The material of the base substrate 10 is, for example, any one of nitride semiconductors typically having GaN, sapphire, bismuth (Si), and tantalum carbide (SiC). In the base substrate 10, an intermediate film which is homogenous or heterogeneous to the single crystal substrate may be further formed on a simple single crystal substrate according to the intended purpose. The intermediate film may be a multilayer film. For example, the interlayer film is a single layer film or a multilayer film including at least one of GaN, AlGaN, InGaN, AlN, and InN. Further, as shown in Fig. 4, a rough pattern can be formed on the film forming surface of the base substrate 1〇. When the intermediate film is formed, a rough pattern may be formed to reach one half of the intermediate film or formed to penetrate the intermediate film to reach the inside of the single crystal substrate. Further, an intermediate film can be formed after a rough pattern has been formed. The inner wall of the recessed portion 13 of the base substrate (including the side walls 16 and the bottom surface 14) need not be flat and smooth. Further, the side wall 16 need not be vertical and may be tapered. The inclination angles of the side walls 16 forming each of the depressed portions need not be equal to each other. Next, the gap 6 1 will be described. The void 61 is formed between the depressed portion 13 of the base substrate 1 and the first nitride semiconductor layer 40. The number of the voids 61 exceeds one and is equal to or smaller than the number of the depressed portions 13. When the base substrate 10 and the first nitride semiconductor layer 40 are bonded to each other at -24-201006973, the size of the void 61 is roughly determined by the size of the recess 13. In the case where the nitride semiconductor layer 40 is formed by lateral growth using the rough pattern of the base substrate 10, as seen in FIGS. 3 and 4, the size of the void 61 is determined by the size of the depressed portion 13, the thickness of the nitride semiconductor 41, and The thickness of the nitride semiconductor (not shown) formed on the sidewall 16 of the depressed portion of the base substrate depends on the thickness of the nitride semiconductor (not shown). When the base substrate 10 is a substrate formed of a material of a non-nitride semiconductor, the thickness of the film formed on the side wall 16 of the depressed portion of the base substrate is almost negligible. The thickness of the nitride semiconductor 41 formed on the sidewall 16 of the depressed portion of the base substrate is determined by the growth conditions of the base substrate 10 and the first nitride semiconductor layer 40, and is often the thickness U of the first nitride semiconductor layer 40. Half or less. In order to ensure the film quality of the first nitride semiconductor layer 40, the depressed portions 13 are preferably distributed in an almost periodic manner. Further, with respect to the depressed portion 13, the size of the individual depressed portions is preferably substantially equal to each other. The pattern of the depressed portions 13 is, for example, viewed from the film forming surface as a set of periodically arranged parallel trenches or a set of independently arranged periodic holes. The size of the depressed portion 13 can be optimized according to the pattern shape of the depressed portion 13, the thickness t of the base substrate 10, and the film thickness of the first nitride semiconductor layer 40. The size of the recess 13 is illustrated by way of example, wherein the pattern is a set of periodically arranged parallel straight trenches. Set the length of each of the ditches so that the ditches cross the -25-201006973 area where the growth is intended. For example, when the diameter of the region where growth is intended is 2 inches, the length of each of the trenches is set to a maximum of 2 inches. As shown in Fig. 4, the period, width and depth of the trench are represented by P 〇 , w 〇 and d 分别 , respectively. When t〇>100pm, the following relationship must be satisfied: 20 ηιη <ρ〇 <20μιη * 10 nm <w〇 <p〇,0.2w〇 <d〇 <t〇,ti>w〇. To give another specific example, the following relationship needs to be satisfied: t〇 = 420 pm, ρ 〇 = 10 μιη, w〇 = 7 μπι ' ά〇 = 6 μιη ' ΐι = 10μηι. In this case, the resulting void 61 has a width of about 7 μί and a depth of 3 μm or more. The presence of the voids 61 can alleviate the strain stress between the nitride semiconductor 20 and the base substrate 10. Further, when the first nitride semiconductor layer 40 is formed by lateral growth using a rough pattern on the base substrate, rather than when the first nitride semiconductor layer 40 is formed on the flat base substrate by direct growth, the number can be further reduced. The threading type misalignment density in the nitride semiconductor layer 40. The nitride-containing semiconductor layer composite substrate 30 of the present embodiment can be manufactured by the manufacturing method shown in the third embodiment. (Third Embodiment) As a third embodiment of the present invention, an example of a method of manufacturing a nitride-containing semiconductor layer composite substrate will be described. Figs. 5 to 5F are schematic cross-sectional views showing an example of a method of manufacturing the nitride-containing semiconductor layer composite substrate in the present embodiment. In the manufacture of the composite substrate, the base substrate 1 is first prepared (Fig. 5, 2010, 069, 730). The base substrate can be a simple single crystal substrate. The base material is, for example, any of nitride semiconductors typically having GaN, sapphire, bismuth (Si) and intercalation. In the base substrate 10, depending on the intended purpose, it may be further formed on the simple substrate to be homogenous or different from the single crystal substrate (not shown). This interlayer film can be a multilayer film. For example, at least one of the interlayer film j, AlGaN, InGaN, AlN, and InN is a multilayer film. Next, as shown in Fig. 5B, a rough pattern can be formed on the base substrate forming surface. When the intermediate film is formed, the pattern reaches a half of the intermediate film or is formed to penetrate the inside of the single crystal substrate. In addition, a rough pattern interlayer film can be formed. The inner wall of the recessed portion 13 of the rough pattern (including the side wall 1) need not be flat and smooth. Further, the side wall 16 need not be vertical and may be tapered. The inclination angles of the two side walls 16 of each of them do not need to be equal to each other. The rough pattern is known by the lithography technique and etching. Examples of lithography techniques include photoresist or photobeam exposure techniques based on photolithography. The resist pattern is transferred to a so-called hard mask film or SiO 2 film as needed. The material of the bottom 10 is U匕矽 (Sic single single crystal intermediate film is a single layer film including GaN or a film of Ξ 10 can form a rough interlayer film to form a middle portion 6 and a bottom surface 14 to form a depressed portion. Forming a pattern forming mask such as metal -27-201006973 The engraving technique is a technique of processing the base substrate 10 by dry or wet etching using a resist pattern or a hard mask pattern as a mask. The depressed portions 13 of 10 are preferably distributed in an almost periodic manner. Further, the size of the individual depressed portions is preferably substantially equal to each other with respect to the depressed portions 13. The pattern of the depressed portions 13 is, for example, a group as viewed from the film forming surface. A periodically arranged parallel trench or a set of independent holes arranged periodically. The recess can be optimized according to the pattern shape of the recess 13 , the thickness t 基础 of the base substrate 1 , and the film thickness of the first nitride semiconductor layer 40 . The size of the portion 13. The size of the recess 13 is illustrated by way of example, wherein the pattern is a set of periodically arranged parallel straight trenches. Setting the length of each of the trenches allows the trench to cross the intent The area where the growth occurs. For example, when the area where the growth is intended is 2 inches in diameter, the length of each of the ditches is set to a maximum of 2 inches. As shown in Fig. 5B, the period, width and depth of the trench are respectively It is represented by p〇 and d〇. When ΐ〇>100μιη, the following relationship must be satisfied. 2〇ηιη <ρ〇 <20μιη, 1 0 nm <w〇 <p. , 0.2w〇 <d〇 <t. ‘ti>w〇. For another specific example, the following relationship needs to be satisfied: " = 420μιη, PD = lMm, \ν〇 = 7μιη, d〇 = 6μπι ' ΐι = 10μιη ο As needed, the orientation of the rough pattern matches the base base β 10 51 crystal orientation Next, a first step of forming a continuous layer of the first nitride semiconductor layer 40 shown in Fig. 5C is performed. -28- 201006973 In this case, the base substrate ι and the first nitride semiconductor layer 40 are formed. A void 61 is formed therebetween. The material of the first nitride semiconductor layer 40 is, for example, a gallium nitride compound semiconductor represented by the general formula AlxGayln^x.yN (OSxS 1, OSyS 1 , 〇Sx + yS 1 ). GaN, AlGaN, InGaN, AlN, and InN are included. The first nitride semiconductor layer 40 can be bonded to the base substrate 10 by substrate bonding. φ. The term "substrate" as used herein means, for example, a surface activation step and a heat bonding. The step of the connection may be from room temperature to 1 000 ° C. The first nitride semiconductor 40 may be formed on the base substrate 10 by crystal growth. Examples of the crystal growth method include metal organic chemical vapor deposition. Method (MOCVD method), hydride vapor phase crystal method (HVPE method), and molecular beam epitaxy growth method (MBE method). In order to reduce the threading type dislocation density in the first nitride semiconductor layer 40 and form the void 61, It is preferable to preferentially carry out the crystal growth condition of the lateral growth of the first nitride semiconductor layer 40. For preferential lateral growth, the arrangement pattern of the rough pattern of the base substrate 10 is previously matched with the intended crystal orientation. In the case of crystal growth, The thin film of the first nitride semiconductor is represented by a nitride semiconductor 41 formed on the depressed portion of the base substrate, and is also formed on the bottom surface 14 of the depressed portion 13 of the base substrate 10. The crystal growth conditions are, for example, the following as known so far. MOCVD growth conditions. In other words, in an MOCVD apparatus, a nitride semiconductor buffer layer of several tens of nanometers is first grown at a substrate temperature of 300 to 700. -29- 201006973 In the case of GaN, for example, trimethylgallium (trimethylgallium; TMG) is used as a Group III material and ammonia (NH3) is used as a Group V material. Next 'increasing the substrate temperature to about 1 〇〇 (TC) Conducting lateral growth of a nitride semiconductor, for example, 'forming a GaN film thick ΙΟμηη. In this case, TMG and NH3 are used as materials. When an impurity is intended to be introduced, a suitable gas is introduced into the thin film forming apparatus. For example, as a GaN application The bulk gas, decane is suitable, and by lateral growth, a continuous layer of the first nitride semiconductor layer 40 is obtained, which is completely flat, and wherein the threading type dislocation density near the surface thereof is in the upper region of the depressed portion 13 of the base substrate. Medium for reduction. In the region of the first nitride semiconductor layer 40 in which the threading type misalignment density is reduced, the threading type misalignment density becomes ixl 〇 8 Cm·2 or less. This turn is one order of magnitude or more lower than the threading type misalignment density of the nitride semiconductor formed on the projections 12 of the base substrate. Under the above crystal growth conditions, when ρ 〇 = 10 μηι, · \ν 〇 = 7 μηη, (1 〇 = 6 μηη, tflOpm, the resulting void 61 has a width of about 7 μm and a depth of about 3 μη! or more. Next, As shown in Fig. 5D, a second step of forming a rough pattern on the continuous layer of the first nitride semiconductor layer 40 is performed. The rough pattern on the continuous layer is formed by the currently known lithography technique and etching technique. Examples of lithography techniques include resist patterning techniques based on photolithography or electron beam exposure techniques. -30- 201006973 Transfer resist patterns to so-called hard masks, such as metal films or SiO 2 films, as needed. A hard mask is particularly required in the case of forming a deep roughness pattern. The etching technique is to treat the first nitride by dry or wet etching using an resist pattern or a hard mask pattern as an etch mask (not shown). The technique of the semiconductor layer 40. The dry uranium engraving is, for example, dry etching using a plasma of a reactive gas. The reactive gas is a single gas or a mixed gas including two or more gases, and may be according to the first The composition of the semiconductor layer 40 is optimized. For example, in the case where the first nitride semiconductor layer 40 is a GaN layer, as the main reactive gas, a chlorine-containing gas (such as C12, BC13, SiCl4) or CH4 may be used. When forming the recessed portion 43 of the rough pattern, it is preferable to remove as much as possible the portion of the first nitride semiconductor layer 40 having a relatively high threading-type dislocation density, which can be obtained in the formation of a thin film of a subsequent nitride semiconductor. A film having a reduced defect density. A portion having a high threading type dislocation density is, for example, positioned on the projection 12 of the base substrate 10. When the engraved mask of the first nitride semiconductor layer 40 is formed, a mask is appropriately formed. The design of the shape and the positioning in the photolithography can form the depressed portion 43 of the above rough pattern. Depending on the pattern shape of the depressed portion 43, the film thickness t1 of the first nitride semiconductor layer 40, and the second nitride formed later The film thickness t2 of the semiconductor layer 50 can optimize the size of the depressed portion 43 of the rough pattern. -31 - 201006973 The size of the depressed portion 43 of the rough pattern is illustrated by way of example, wherein the pattern A set of periodically arranged parallel straight trenches. Set the length of each of the ditches so that the ditches span the area where the growth is intended. For example, when the area where the growth is intended is 2 inches in diameter, the length of each of the ditches is set. For a maximum of 2 inches. As shown in Figure 5D, the period, width and depth of the trench are represented by Pi, Wi and di, respectively. When ti > 50 nm (nm), the following relationship is required: 20 nm <pi <10ti > 10 nm <wi <pi > Ο . 2 w i <d i <t ι 5 t2> w i o For example, when tplOpm, the following relationship is required: 1 μιη <ρ ι <20μιη, 10 0 nm <wι <ρ ι > 10 0 nm <di <8 μιη, t2> 2 00 nm. For another specific example, the following relationship needs to be satisfied: tl = 8pm, ρ ι = 1 0 μιη 'w ι = 7 μιη 'd ι = 6 μιη ' t2=l〇pm. Next, as shown in Fig. 5E, a third step of forming a state containing crystallinity defects in the continuous layer of the first nitride semiconductor layer 40 is performed. The portion 45 having the crystallinity-containing defect state is at least partially formed on the inner wall of the depressed portion 43 of the rough pattern. In Fig. 5E, the portion 45 having the crystallinity-containing defect state is formed on the entire surface of the inner wall of the depressed portion 43 of the rough pattern, but may be formed only on a portion of the depressed portion 43 of the rough pattern, such as Only on the bottom surface 44 shown in Figure 5D or only on the side wall 46. The portion 45 having a state containing crystallinity defects may be uniform or non-uniform. In particular, the sidewalls 44 and the bottom surface 44 need not be the same thickness as the portion 45 having a crystallinity-containing defect of -32 - 201006973. The role of the portion 45 having crystallinity defects is to reduce the rate of formation of the nitride semiconductor on its surface. As a method of forming the portion 45 having crystallinity defects, a surface treatment based on a technique such as reactivity such as ion etching (RIE), plasma etching, ionizing radiation, or neutron beam irradiation is applied to change the portion of interest from the single crystal state. . The state of the portion of interest of φ after the change can be changed from a single crystal state to, for example, an amorphous state, a porous state, or a polycrystalline state. At the time of surface treatment, a portion that does not want to be changed is protected by a mask (not shown). The protective mask may be newly formed by the formation method of the etch mask described in the second step, or the etching mask itself may serve as a protective mask. The thickness of the portion 45 can be controlled by the above surface treatment conditions and surface treatment time, and varies from a single atomic layer thickness to several hundred nanometers. φ Next, the fourth step of forming the second nitride semiconductor layer 50 shown in Fig. 5F is performed. In this case, the void 62 is formed between the second nitride semiconductor layer 50 and the first nitride semiconductor layer 40. The material of the second nitride semiconductor layer is, for example, a gallium nitride compound semiconductor represented by the general formula AlxGayIni.x.yN (OSxSl, OSySl, 〇Sx + ySl). Typical examples thereof include GaN, AlGaN, InGaN, AlN, and InN. The second nitride semiconductor layer 50 and the first nitride semiconductor layer 40 may be homogenous or mutually heterogeneous with each other -33-201006973. Further, the second nitride semiconductor layer 50 may be formed of a multilayer film. The second nitride semiconductor layer 50 is formed in a similar manner to the crystal growth method of the first nitride semiconductor layer 40 described in the first step and is a lateral growth of MOCVD which is mainly known. The nitride semiconductor 51 can also be formed in the inside of the depressed portion 43 of the first nitride semiconductor layer simultaneously with the lateral growth of the second nitride semiconductor layer 50. The film thickness of the nitride semiconductor 51 may be uneven depending on the formation conditions or film formation conditions of the crystallinity-containing defect portion 45. In particular, the film thickness of the nitride semiconductor 51 may be uneven on the side walls 46 and the bottom surface 44 as shown in Fig. 5D. The presence of the crystallinity-containing defect portion 45 is reduced, and the rate of formation of the nitride semiconductor on the inner wall 43, particularly, on the side wall 46, makes the film thickness of the nitride semiconductor 51 suitably negligibly thin. Thus the size of the gap 62 is ensured. The resulting void 62 has, for example, a width of about 7 μm and a depth of 3 μm or more, and the film thickness t2 of the second nitride semiconductor layer 50 is set to ί2 = 10 μm. The film of the second nitride semiconductor layer 50 formed by this lateral growth has a threading type misalignment density of 3 χ 〇 7 cin·2 or less. This 値 is lower than the threading type misalignment density based on the nitride semiconductor grown directly on the first nitride semiconductor layer 40 where no rough pattern is formed. During the crystal growth of the first nitride semiconductor layer 50, a portion of the crystal-containing defect portion 45 becomes polycrystalline due to recrystallization, but does not become a single crystal which is integral with the projection 42. The void 62 can alleviate the strain stress between the first nitride semiconductor layer 40 and the second nitride semiconductor layer 50. In particular, when the material of the first nitride semiconductor layer 40 and the material of the second nitride semiconductor layer 50 are different from each other, the relaxation is remarkable. Therefore, the presence of the voids 62 greatly reduces the influence of the base substrate 10 on the second nitride semiconductor layer 50 as compared with the influence of the base substrate on the first nitride semiconductor layer 40. Therefore, deformation and defects due to strain stress can be reduced in the second nitride semiconductor layer 50. According to this embodiment, the nitride semiconductor-containing composite substrate of the present invention can be produced. As a fourth embodiment of the present invention, an example of a method of manufacturing a structure containing a nitride semiconductor will be described. The method of fabricating the nitride semiconductor-containing structure 20 of the present embodiment is characterized by comprising the steps of: manufacturing a nitride semiconductor-containing composite substrate 30, and removing the base substrate of the composite substrate 30. The method of manufacturing the composite substrate 30 has been described in the third embodiment, and thus is omitted here. The steps of removing the base substrate and others are described hereinafter. The base substrate 10 can be removed by selective etching using a difference in the degree of etching resistance between the materials. For example, when the material of the base substrate 1 is Si, the base substrate 10 can be removed by dissolving only Si in KOH. When the base substrate 10 is formed of a material that is polished relative to the solution, the base substrate 1 can be removed by polishing from the stomach - 35 - 201006973. When the base substrate 10 includes an intermediate film that can be removed by selective etching, the base substrate 10 can be removed by selective etching to remove the intermediate film. When the base substrate 10 is made of a transparent substrate such as GaN or sapphire, the base substrate 1 can also be removed by the currently known laser lift-off (also referred to as LLO). Further, when the base substrate 1 is a transparent substrate, the base substrate 1 can be removed by selectively removing the interlayer film by the currently known photoelectrochemical uranium engraving. For example, when the base substrate 10 is made of GaN or sapphire, InGaN can function as an intermediate film. A lamp or laser that emits a base substrate 10 that is not substantially absorbed can be used as a light source, such as a Xe-Hg lamp. An aqueous solution such as KOH can be used as the etching solution. Moreover, the base substrate 10 can be removed while the composite substrate 30 has been attached to a suitable second substrate. Examples of the attachment method include a mediation method using ruthenium or a resin and a direct interface method including a surface activation step and a heat-adhesion step. Thereafter, the removal of the base substrate 10 by the LLO method will be described in detail with reference to Figs. 6A to 6D. The nitride semiconductor-containing composite substrate 30 described in the second embodiment will be exemplified. Figure 6A shows a composite substrate 30 containing a nitride semiconductor prior to processing. Figure 6B shows the electromagnetic wave radiation step. The electromagnetic wave is substantially not absorbed by the base substrate 10, but is absorbed by the first nitride semiconductor layer of the first nitride semiconductor layer 40, and is, for example, laser light. For example, when the base substrate 10 is made of sapphire and the first nitride semiconductor layer 40 is made of GaN, laser light having an oscillation wavelength of 370 nm or shorter is preferable. Examples of lasers that can be used include the following excimer lasers: ArF (193 nm) 'KrF (248.5 nm) and XeCl (308 nm) ° _ Electromagnetic wave radiation time only needs to allow decomposition of the first nitride semiconductor layer 40 and This removes the base substrate 10, and performs radiation by appropriately adjusting the irradiation time according to the kind of electromagnetic waves. As the radiation method, as shown in Fig. 6B, the entire area can be radiated from the base substrate 1 雷 in the direction 70 by the laser light. Alternatively, the xy stage on which the substrate is placed is moved, and finally the laser can be radiated from the rear surface of the base substrate 10 to the entire area. By electromagnetic wave radiation, as shown in Fig. 6B, the portions 71 and 72 in which the nitride half φ conductor has been decomposed are respectively formed on the interface with the bottom surface of the depressed portion of the base substrate 1 and the projection with the base substrate 10. The interface on the top of the department. For example, when the first nitride semiconductor layer 40 is made of GaN, GaN is decomposed into Ga and N2, and thus the portions 71 and 72 in which the nitride semiconductor has been decomposed are mainly formed of Ga. The N 2 gas is explosively diffused in the void 61. If there is no void 61, the explosive diffusion of the N2 gas causes a large amount of microcracks in the first nitride semiconductor layer 40. -37- 201006973 The presence of the void 61 provides an N2 gas escape path and thus greatly reduces the generation of microcracks. Therefore, the damage caused by the removal of the substrate to the structure 20 containing the nitride semiconductor can be reduced. As a result of the electromagnetic wave radiation, the connection in the contact interface between the structure 2〇 of the nitride-containing semiconductor and the base substrate 10 is dominated by Ga. The base substrate 10 can be removed even if only a little force is applied, resulting in a structure as shown in Fig. 6C. The nitride-containing semiconductor structure 20 thus fabricated can be used. Perform the following additional procedures 1 through 3 as needed. In the additional procedure 1, Ga and the like attached to the surface of the structure 16 containing the nitride semiconductor are removed. To this end, the cleaning is carried out with diluted hydrochloric acid. In an additional procedure 2, as shown in FIG. 6C, the first nitride semiconductor layer 40 in the interface in contact with the first nitride semiconductor layer 40 and the base substrate 10 is used. A recess 47 is formed on the side. At this time, the damage caused by the electromagnetic wave radiation remains in the concave portion 47 in the first nitride semiconductor layer 40. According to the analysis based on the section transmission electron microscopy (TEM) method or the Rutherford backscattering (RBS) method, depending on the electromagnetic radiation, it can be seen that the damage is limited to the depth of the self-interface 500 nm. The damage to the nitride-containing semiconductor structure 20 due to substrate removal is almost excluded. Examples of methods of removing the recess 47 in the first nitride semiconductor layer include mechanical polishing, chemical mechanical polishing (CMP), ion milling, and gas 201006973 cluster ion beam (GCIB) etching. In an additional procedure 3, as shown in FIG. 6D, when it is intended to planarize the surface of the first nitride semiconductor layer 40 or to adjust the film thickness of the first nitride semiconductor layer 40, The same method of the recess 47 of the nitride semiconductor layer is to flatten the surface of the first nitride semiconductor layer 40. Therefore, a nitride semiconductor-containing structure 20 having a flat bottom surface can be obtained. According to this embodiment, the fabrication of the structure of the nitride-containing semiconductor in the present invention can be achieved. Hereinafter, an example of the present invention will be described. <Example 1> In Example 1, a specific example of the structure of the nitride-containing semiconductor which has been described in the first embodiment will be described with reference to Figs. φ omits the description of the portion overlapping with the portion explained in the first embodiment. In this example, both the first nitride semiconductor layer 40 and the second nitride semiconductor layer 50 are single crystals of GaN. The thickness q of the first nitride semiconductor layer 40 is set to t! = 8 μm and the thickness t2 of the second nitride semiconductor layer 50 is set to t2 = 10 μm. The GaN-containing structure 20 is formed of the nitride semiconductor layers 40 and 50 and the voids 62 formed between the nitride semiconductor layers 40 and 50, and is characterized in that at least a portion of the wall surrounding the void 62 contains crystallinity - 39- 201006973 Defect. In the crystallinity-containing defect portion 45, the crystal state thereof is changed from the single crystal state of the inside (e.g., portion 42) of the first nitride semiconductor layer 40. The crystalline state of the crystallinity-containing defect portion 45 includes at least one polycrystalline state. The region containing the crystallinity defect portion 45 covers the entire surface of the inner wall of the depressed portion 45 of the first first nitride semiconductor layer 40. The crystal-containing defect portion 45 may have a thickness ranging from a single atomic layer to several hundred nanometers, and is uneven in atomic layer level. The role of the crystallinity-containing defect portion 45 is to reduce the rate of formation of a nitride semiconductor on the surface thereof. The result of this role is to ensure the size of the gap 62. The film thickness of the nitride semiconductor 51 formed on the depressed portion 43 of the first nitride semiconductor layer depends on the film formation condition or formation condition of the crystallinity-containing defect portion 45, which may be an uneven sentence. For example, the film thickness of the nitride semiconductor 51 is negligibly thin on the side wall 46 as a few atomic layer thick, and is 2 μm or less on the bottom surface 44. The gap 62 is formed between the depressed portion 43 of the first nitride semiconductor layer and the second nitride semiconductor layer 50. The number of voids 62 exceeds one and is equal to or less than the number of recesses 43 of the first nitride semiconductor layer. As can be seen from Figs. 1 and 2, the size of the gap 62 is roughly determined by the size of the depressed portion 43 and the thickness of the nitride semiconductor 51. -40- 201006973 In order to ensure the film quality of the second nitride semiconductor layer 50, the depressed portions 43 of the first nitride semiconductor layer are preferably distributed in a periodic manner. Further, the sizes of the individual depressed portions 43 of the first nitride semiconductor layer are preferably substantially equal to each other. The pattern of the depressed portions 43 of the first nitride semiconductor layer is a set of periodically arranged parallel trenches as viewed from the film forming surface. The inner walls (including the side walls 46 and the bottom surface 44) of the depressed portion 43 of the first nitride semiconductor layer are uneven and smooth in atomicity. The side wall 46 of the depressed portion 43 of the first nitride semiconductor layer has an inclination angle of about 85°. The size of the depressed portion 43 of the first nitride semiconductor layer is as follows. Each of the trenches has a length that spans 2 inches of the base of the trench, and each of the trenches has a length of up to 2 inches. As shown in Fig. 2, when the trench period is Ρι = 10μπι, the trench width is Wl = 7pm, and the trench depth is (Ιρόμιη), the resulting void 62 has a width of about 7 μm and a depth of 4 μm or more. The strain stress between the first nitride semiconductor layer 40 and the second nitride semiconductor layer 50 is alleviated. Therefore, in the nitride semiconductor-containing structure 20, deformation and defects due to strain stress can be reduced. The fabrication method described herein produces the GaN-containing structure 20 of the present example. <Example 2> In Example 2, a specific example of a nitride semiconductor-containing composite substrate which has been described in the second embodiment, -41 - 201006973, is explained with reference to Figs. Description of the portions overlapping with the portions explained in the second embodiment will be omitted. In the present example, the nitride semiconductor-containing composite substrate 30 is formed of a base substrate 10 made of sapphire and a nitride-containing semiconductor structure 20 as described in Example 1. A void 61 is formed between the base substrate 10 and the structure 20, and a void 62 is formed between the first nitride semiconductor layer 40 and the second nitride semiconductor layer 50. ® Since the structure 20 of the nitride-containing semiconductor is the same as that in the first embodiment, only the base substrate 10 and the void 61 will be described with reference to FIGS. 3 and 4. First, the base substrate 10 will be described. The base substrate 10 is a 2 inch 0 sapphire single crystal substrate and its thickness t Q is set to t 〇 = 4 2 0 μ m. As shown in Fig. 4, the film forming surface of the base substrate 1 is a C-plane, and the periodic straight channel is formed in a manner substantially parallel to the "11-20" direction of the base substrate 10. The length of each of the ditches is set such that the ditches span the entire area of the base substrate 10, and each of the ditches has a length of up to 2 inches. Set the trench period to Ρι = 10μηι, the trench width to wfJpm, and the trench depth to 1 = 6μιη. Next, the gap 6 1 will be described. The void 61 is formed between the depressed portion 13 of the base substrate 1 and the first nitride semiconductor layer 40. -42- 201006973 The number of the voids 61 is equal to the number of the recessed portions 13. The size of the void 61 is roughly determined by the depressed portion 13 and the nitride semiconductor 41 formed on the bottom surface 14 of the depressed portion 13. The film thickness of the nitride semiconductor formed on the side wall portion 16 of the depressed portion 13 is almost negligible. The thickness of the nitride semiconductor 41 is 3 μm or less. In particular, the void 61 spans the base substrate 10 and is gathered to a length of up to 2 inches, a width of about 7 μm, and a depth of about 3 μm or less. The presence of the voids 61 can alleviate the strain stress between the mutually heterogeneous nitride semiconductor 20 and the sapphire base substrate 10. Further, when the first nitride semiconductor layer 40 is formed by lateral growth using a rough pattern on the base substrate, instead of forming the first nitride semiconductor layer 40 on the flat base substrate by direct growth, it can be further reduced The threading type misalignment density in the first nitride semiconductor layer 40. The nitrided semiconductor-containing composite substrate 30 of the present example can be produced by the manufacturing method described in Example 3. <Example 3> In Example 3, a specific example of the manufacture of the nitride semiconductor-containing composite substrate which has been described in the third embodiment will be described with reference to Figs. 5 to 5F. Description of the portions overlapping with the portions explained in the third embodiment will be omitted. The base substrate 10 is first prepared. -43- 201006973 Figure 5A shows a sapphire base substrate 10. The base substrate 10 has a size of 2 inches and its thickness to is set to to = 4 2 0 μη. The film forming surface of the base substrate 10 is a C plane. Further, as shown in Fig. 5, on the film formation surface of the base substrate 1, the periodic straight groove is formed to be almost parallel to the "1 1 -20" direction of the base substrate 1 . A well-known lithography technique and etching technique can be used as a forming method (not shown). First, a Cr film of about 300 nm was deposited by sputtering on the film formation surface of the base substrate. Next, a desired resist pattern is formed on the Cr film by photolithography. In this case, the positioning of the mask and the substrate is such that the linear trench is disposed almost parallel to the direction of the base substrate. Next, a resist was used as an etching mask, and the pattern was transferred to the Cr film by applying RIE with a mixed gas including chlorine (Cl2), 02, and Ar, and thus a hard mask made of Cr was formed. Next, the resist is detached by applying an oxygen plasma. The sapphire substrate is etched to the desired depth by using a Cr hard mask and by applying a RIE with a chlorine-containing gas. Finally, a commercially available Cr etchant is used to completely remove the Cr hard mask. In the obtained linear trench pattern, the length of each of the trenches is set such that the trench spans the entire area of the base substrate and is set to a maximum of 2 inches, and the channel period is set to Ρ^ΙΟμιη, the trench width is ^^μιη and -44- 201006973 The ditch depth is diWpm. The angle of inclination of the side wall 46 is about 85 °. Next, a first step of forming a continuous layer of the first nitride semiconductor layer 40 shown in Fig. 5C is performed. In this case, the void 6 1 is formed between the base substrate 10 and the first nitride semiconductor layer 40. The material of the first nitride semiconductor layer 40 is G aN 〇 The first nitride semiconductor layer 40 is formed on the base substrate 10 by MOCVD-based crystal growth. In order to reduce the threading type misalignment density in the first nitride semiconductor layer 40 and form the voids 6, the first nitride semiconductor layer 40 is formed under the crystal growth conditions in which lateral growth is preferentially performed. At the same time as the formation of the first nitride semiconductor layer 40, a GaN thin film represented by the nitride semiconductor 41 is also formed on the bottom surface 14 of the depressed portion 13 of the base substrate 10 by crystal growth. The crystal growth conditions are, for example, currently known MOCVD growth conditions. In detail, in the MOCVD apparatus, a GaN buffer layer of several tens of nanometers was first grown at a substrate temperature of 500 °C. Next, the substrate temperature is increased to about 1000 ° C' to carry out lateral growth of GaN to form a GaN continuous layer of the first nitride semiconductor layer 40 of about ιομηη thick. When a continuous layer of GaN is formed, trimethylgallium (TMG) is used as the Group III material and ammonia (NH3) is used as the Group V material. Under this crystal growth condition, the thickness of the nitride semiconductor 41 is 3 μm or less, and GaN is hardly formed on the sidewall 16 of the depressed portion -45 - 201006973 of the base substrate. In particular, the void 61 spans the base substrate 10 and has a length of up to 2 inches, a width of about 7 μm, and a depth of about 3 μm or more. The threading type dislocation density formed by such lateral growth in the first nitride semiconductor layer 40 is lower than the threading type dislocation density of the GaN film formed by crystal growth on the substrate formed without the roughness pattern. In detail, in a portion of the first nitride semiconductor layer 40 mainly grown in a crystal (for example, a portion directly above the depressed portion 13 of the base substrate), the threading type misalignment density is lxl 〇 8 cm 2 or less. . The evaluation of the threading type dislocation density is performed by atomic force microscopy (AFM) or the like. Next, as shown in Fig. 5D, a second step of forming a rough pattern on the GaN continuous layer of the first nitride semiconductor layer 40 is performed. The rough pattern is formed by a periodic straight groove which is almost parallel to the pattern on the sapphire substrate 10 shown in Fig. 5B, and the period of the rough pattern is the same as that of the pattern on the sapphire substrate. In detail, Ρ^ΡοΜΟμπι. However, when the recessed portion 43 of the rough pattern is formed, the relatively high-thread-type dislocation density portion of the first nitride semiconductor layer 40 is removed as much as possible. This makes it possible to obtain a film having a reduced defect density in the formation of a film of a subsequent nitride semiconductor. In other words, the bottom surface 44 of the depressed portion 43 is formed directly on the projection 12 of the base substrate 10. When the etching mask of the first nitride semiconductor layer 40 is formed, the above can be easily realized if the design of the mask shape and the positioning during photolithography are appropriately performed. -46- 201006973 A rough pattern on the first nitride semiconductor layer 40 is formed using well-known lithography techniques and etching techniques (not shown). For example, a Ni pattern of about 500 nm thick is formed on the upper surface of the first nitride semiconductor layer 40 by using a lift-off method. Next, the first nitride semiconductor layer 40 is etched to a desired depth by using a Ni pattern as a hard mask and by applying RIE having a mixed gas including Cl2 and BC13 or the like. Finally, the Ni hard mask was completely removed by heating to about 50 ° C with a 3.5% aqueous solution of FeCl 2 as the uranium engraving agent. The length of each of the trenches of the resulting straight trench pattern is set such that the trench spans the entire area of the base substrate 10 and the length of each of the trenches is set to a maximum of 2 inches. The trench period is set to Ρι = 10μιη, the trench width is wpTpm, and the trench depth is (Ι^όμιη» sidewall 16 has an oblique angle of about 85°. Next, as shown in FIG. 5, the first nitride semiconductor layer is performed. A third step of forming a state of crystallinity defect is formed in 40. As a method of forming the portion 45 having a state of crystallinity-containing defects, the entire inner wall of the depressed portion 43 of the first nitride semiconductor layer is irradiated by, for example, Ar ion irradiation. The surface is transformed into an amorphous state. The thickness of the crystal-containing defect portion 45 can be controlled by the Ar ion acceleration energy and the Ar ion irradiation time, from a single atomic layer thickness to several hundred nanometers, and need not be uniform. A fourth step of forming a continuous layer of the second nitride semiconductor layer 50 as shown in Fig. 5F. In this case, the void 62 is -47-201006973 formed on the second nitride semiconductor layer 50 and the first nitride The material of the second nitride semiconductor layer is, for example, single crystal GaN. The method of forming the second nitride semiconductor layer 50 and the first nitride half described in the first step The crystal growth method of the bulk layer 40 is similar to 'and is the lateral growth of the main well-known MOCVD. However, in this case, the formation of the low temperature buffer layer becomes unnecessary. The lateral growth with the second nitride semiconductor layer 50 Simultaneously, the nitride semiconductor 51 may be formed in the inside of the depressed portion 43 of the first nitride semiconductor layer 40. The film thickness of the nitride semiconductor 51 may be determined depending on the formation conditions or film formation conditions of the crystallinity-containing defect portion 45. The unevenness of the crystallinity-containing defect portion 45 is reduced, and the formation rate of GaN is formed on the inner wall, particularly on the side wall 46 of the depressed portion 43 of the first nitride semiconductor layer. Therefore, the size of the void 62 can be ensured. When the film thickness t2 of the second nitride semiconductor layer 50 is set to t2 = 10 pm, the resulting void 62 has a width of about 6 μm and a depth of 3 μm or more. Thus, a second nitride semiconductor layer formed by lateral growth is formed. The threading type dislocation density of the film of 50 is lxlO7 cm·2 or less. This bismuth ratio is based on nitriding directly grown on the first nitride semiconductor layer 4 without forming a rough pattern. The shiddle type misalignment density of the semiconductor is lower. The gap 62 can alleviate the strain stress between the first nitride semiconductor layer 40 and the second nitride-48-201006973 semiconductor layer 50. Therefore, the base substrate 10 and the first nitride semiconductor Compared with the influence of the layer 40, the influence of the base substrate 10 on the second nitride semiconductor layer 50 is greatly reduced. Therefore, in the second nitride semiconductor layer 50, deformation and defects due to strain stress can be reduced. The manufacture of a nitride semiconductor-containing composite substrate in the present invention is achieved. <Example 4> In Example 4, a specific example of the manufacture of the nitride-containing semiconductor structure 20 which has been explained in the fourth embodiment will be described with reference to Figs. 6 and 6D. Description of the portions overlapping with the portions explained in the fourth embodiment will be omitted. The method of fabricating the nitride-containing semiconductor structure 20 is characterized by the steps of fabricating the nitride semiconductor-containing composite substrate 30 and removing the base substrate 10 of the composite substrate 30. The manufacturing method of the composite substrate 30 has been described in the example 3, and thus the description thereof is omitted here. Hereinafter, the steps of removing the sapphire base substrate and other steps will be explained. Removal of the base substrate 10 by the currently known LLO method 〇 Figure 6 shows the composite substrate containing GaN before the LLO treatment -49- 201006973 30 ° Figure 6B shows the electromagnetic wave irradiation step. The electromagnetic wave is, for example, KrF excimer laser light having a wavelength of 248.5 nm, an energy density of about 600 mJ/cm 2 and a laser pulse width of about 20 ns. Laser radiation is applied from the sapphire substrate side 70. The composite substrate 30 is placed on the xy stage, and the stage is moved to perform radiation to uniformly radiate from the peripheral portion of the inner portion of the base substrate. The moving speed is optimized according to the erosion of the base substrate 1〇. As shown in Fig. 6B, the electromagnetic wave radiation forms a portion in which the nitride semiconductor GaN is decomposed in the interface with the bottom surface of the depressed portion of the base substrate 10 and the top surface of the convex portion of the base substrate 1 respectively. And 72 ° In this case, GaN is decomposed into 0 and N2, and thus the portions 71 and 72 in which the nitride semiconductor has been decomposed are mainly formed of Ga. The N 2 gas is explosively diffused in the void 61. If there is no void 61, the explosive diffusion of the N2 gas causes a large amount of microcracks in the first nitride semiconductor layer 40. The presence of the voids 61 provides an N2 gas dissipation path and thus greatly reduces the generation of microcracks. Therefore, the presence of the voids 61 can reduce the damage caused by the removal of the substrate to the nitride-containing semiconductor structure 20. After the LLO, the bond in the contact interface between the structure 20 and the base substrate 10 is dominated by Ga. The base substrate 10 can be removed even if only a little force is applied, resulting in a structure as shown in Fig. 6C. Next, Ga and the like attached to the surface of the structure 20 are removed. For -50- 201006973 This is washed with diluted hydrochloric acid. Next, as shown in Fig. 6C, the concave portion 47 on the side of the first nitride semiconductor layer 40 is removed. In the recess 47, the damage caused by the LLO is still retained. The depth of the fracture layer is about 500 nm. Ar ion milling can be used as a method of removing the recess 47. Next, as shown in Fig. 6D, the surface of the first nitride semiconductor layer 40 is planarized while adjusting the film thickness of the first nitride semiconductor layer 40. In this case, Ar ion milling and GCIB etching are used in combination. In particular, GCIB is particularly effective for planarization. Finally, the surface of the first nitride semiconductor layer 40 is washed with diluted hydrochloric acid. Next, a structure of a nitride-containing semiconductor having a flat bottom surface is obtained. 〇 According to the method of the present example, the structure of the nitride semiconductor of the present invention can be realized. <Example 5> In Example 5, an application example of a nitride semiconductor-containing composite substrate which has been described in the examples and examples of the present invention is explained. 7A to 7G are schematic cross-sectional views showing an application example of a nitride semiconductor-containing composite substrate described in the embodiments and examples of the present invention. First, the composite substrate 30 of the nitride-containing 201006973 semiconductor described in the second embodiment and the example 2 was fabricated. The method of manufacturing the nitride semiconductor-containing composite substrate 30 has been described in the third embodiment and the example 3, and the description thereof is omitted here. Next, as shown in Fig. 7A, the nitride-containing semiconductor device structure layer 80 is formed by using the composite substrate 30 as a substrate. The method of forming the device structure layer 80 is a currently known MOCVD method. As for the formation conditions, reference can be made to the currently known conditions. Do not make redundant statements that form conditions. The device structure layer 80 is formed, for example, of a nitride semiconductor layer 81 as a first layer, a nitride semiconductor layer 82 as a second layer, and a nitride semiconductor layer 83 as a third layer. The structure and composition of each layer are as follows:

81 : 160 nm 的 η 型 AlojGao.pN81 : η type AlojGao.pN of 160 nm

82 : InGaN之多量子井而無引進雜質，以 3 nm的 In〇.〇8Ga〇.92N/15 nm 的 In〇.〇iGa〇.99N/3 nm 的 In〇.〇8Ga〇.92N 所形成。82: InGaN multi-quantum well without introduction of impurities, formed by 3 nm In〇.〇8Ga〇.92N/15 nm In〇.〇iGa〇.99N/3 nm In〇.〇8Ga〇.92N .

83 : 1 60 nm 的 p 型 Al〇.iGa〇.9N 接著，如第7B圖中所示，在由作爲第三層之氮化物 半導體層83代表的p型AlGaN上形成第一粗糙結構84。 第一粗稳結構爲例如以直徑爲100 nm、深度爲70 nm 及週期爲160 nm的圓形孔所形成之三角形晶格結構。以 目前已知的技術來進行第一粗糙圖案之製造。 例如，藉由電子束曝露方法來形成阻劑圖案，且藉由 使用利用包括eh、BCh及類似者之混合氣體的rIE方法 201006973 用阻劑圖案蝕刻作爲第三層之氮化物半導體層83之暴露 的部份’以形成第一粗糙結構84。第一粗糙結構84爲所 謂的二維光子晶體。 接著’如第7C圖中所示，將其上形成第一粗糙結構 84之作爲第三層之氮化物半導體層83接合至疊層基底90 。在此情況中，藉由包括基底之表面活化步驟及加熱密合 步驟的基底接介方法來進行接合。 一組基底接介條件爲約400°C之溫度及0.5 MPa之負 載。 接著，如第7D圖中所示，藉由第四實施例及範例4 中所述之LLO方法來移除基礎基底1〇。 第7E圖顯示已經移除基礎基底1〇後之情況。 接著，如第7E圖中所示，移除含氮化物半導體之結 構20之區域同時使用Ar離子碾磨結合GCIB蝕刻來進行 平面化。如第7F圖中所示，含氮化物半導體之結構20之 移除暴露出作爲第一層之氮化物半導體層81而產生如第 7F圖中所示之結構。爲了能見度之方便，第7F圖上下顛 倒地顯示在結構20區域移除後之結構。 接著，如第7G圖中所示，在由作爲第一層之氮化物 半導體層81所代表之n型AlGaN上形成第二粗糙結構85 ，產生含氮化物半導體裝置結構86。 當第二粗糙結構85爲週期性粗糙圖案時，第二粗糙 結構85爲所謂的二維光子晶體。 可根據想要的目的相關於其結構適當設計第二粗糙結 -53- 201006973 構85之圖案形狀。 第二粗糙結構85可與第一粗糙結構84的結構完全相 同。如第7G圖中所示，沿著與作爲第一層之氮化物半導 體層81的頂面正交之方向觀看，第二粗糙結構85之孔位 置上可大略與第一粗糙結構84的孔重疊。 上述方法製造之含氮化物半導體裝置結構86可例如 應用至雷射。 在此一情況中，作爲第二層之含氮化物半導體層82 作爲主動層。藉由分別形成在作爲第一層之氮化物半導體 層81及作爲第三層之氮化物半導體層83上之作爲二維光 子晶體的第二粗糙結構85及作爲另一二維光子晶體的第 一粗糙結構84可有雷射振盪。 當電極不如第7G圖般形成時，可藉由光激發將含氮 化物半導體裝置結構86變成雷射振盪。 當藉由電流注入使含氮化物半導體裝置結構86變成 雷射振邊時，可進一步形成電極。例如，可使用p型低電 阻Si基底作爲疊層基底90。 在此一情況中’ P電極可形成在Si側上。另一方面， η電極可形成在第一氮化物半導體層81的上部分中，例如 無作爲二維光子晶體的第二粗糙結構85之部分。 在此範例中’已呈現一有限結構之製造方法。 然而，藉由使用上述方法或從上述方法輕易推知之方 法’可製造出在如含氮化物半導體裝置結構層80之薄膜 成分（材料種類、個別層及類似者之厚度）及第一粗糙結 -54- 0 0201006973 構84與第二粗糖結構85之每一者的結構（粗稳圖案之種 類及粗糙圖案之孔的週期、形狀、大小及深度）上有所變 更的結構。 雖已參照範例實施例說明本發明，可了解到本發明不 限於所揭露之實施例。下列申請專利範圍之範疇應給予最 廣之解釋，以涵蓋所有此種變更及等效結構及功能。 【圖式簡單說明】 第1圖爲描繪本發明之第一實施例中之含氮化物半導 體層之結構的一範例之示意剖面圖； 第2圖爲僅描繪在本發明之第一實施例中之含氮化物 半導體層之結構中之已拆下的第一氮化物半導體層； 第3圖爲描繪根據本發明之第二實施例中之含氮化物 半導體層複合基底的一範例之示意剖面圖。 第4圖爲僅描繪在本發明之第二實施例中之含氮化物 半導體層之結構中之已拆下的基礎基底的圖； 第5A、5B、5C、5D、5E及5F圖爲描繪在本發明之 第三實施例中之含氮化物半導體層複合基底之製造方法的 一範例之示意剖面圖； 第6A、6B、6C及6D圖爲描繪在本發明之第四實施 例中之含氮化物半導體的結構之製造方法的一範例之示意 剖面圖；以及 第7A、7B、7C、7D、7E、7F及7G圖爲描繪在本發 明之實施例及範例中之含氮化物半導體層複合基 -55- 201006973 範例的示意剖面圖。 【主要元件符號說明】 10 :基礎基底 12 :凸出部 1 4 :底面 1 6 :側壁83 : 1 60 nm p-type Al〇.iGa〇.9N Next, as shown in Fig. 7B, a first roughness 84 is formed on p-type AlGaN represented by the nitride semiconductor layer 83 as the third layer. The first coarse stable structure is, for example, a triangular lattice structure formed by circular holes having a diameter of 100 nm, a depth of 70 nm, and a period of 160 nm. The fabrication of the first rough pattern is performed using currently known techniques. For example, the resist pattern is formed by an electron beam exposure method, and the exposure of the nitride semiconductor layer 83 as the third layer is etched with a resist pattern by using the rIE method 201006973 using a mixed gas including eh, BCh, and the like. Part 'to form a first roughness 84. The first roughness 84 is a so-called two-dimensional photonic crystal. Next, as shown in Fig. 7C, the nitride semiconductor layer 83 as the third layer on which the first roughness 84 is formed is bonded to the laminated substrate 90. In this case, the bonding is performed by a substrate bonding method including a surface activation step of the substrate and a heat bonding step. A set of substrate interface conditions is a temperature of about 400 ° C and a load of 0.5 MPa. Next, as shown in FIG. 7D, the base substrate 1 is removed by the LLO method described in the fourth embodiment and the example 4. Figure 7E shows the situation after the base substrate has been removed. Next, as shown in Fig. 7E, the region of the structure 20 containing the nitride semiconductor is removed while planarization is performed using Ar ion milling in combination with GCIB etching. As shown in Fig. 7F, the removal of the nitride semiconductor-containing structure 20 exposes the nitride semiconductor layer 81 as the first layer to produce a structure as shown in Fig. 7F. For the convenience of visibility, the 7F diagram shows the structure after the structure 20 is removed upside down. Next, as shown in Fig. 7G, a second roughness 85 is formed on n-type AlGaN represented by the nitride semiconductor layer 81 as the first layer, and a nitride-containing semiconductor device structure 86 is produced. When the second roughness 85 is a periodic roughness pattern, the second roughness 85 is a so-called two-dimensional photonic crystal. The pattern shape of the second rough knot -53 - 201006973 can be appropriately designed in accordance with its structure depending on the intended purpose. The second roughness 85 can be identical to the structure of the first roughness 84. As shown in FIG. 7G, the hole position of the second roughness 85 can be roughly overlapped with the hole of the first roughness 84 as viewed in a direction orthogonal to the top surface of the nitride semiconductor layer 81 as the first layer. . The nitride-containing semiconductor device structure 86 fabricated by the above method can be applied, for example, to a laser. In this case, the nitride-containing semiconductor layer 82 as the second layer serves as an active layer. A second roughness 85 as a two-dimensional photonic crystal and a first two-dimensional photonic crystal are formed on the nitride semiconductor layer 81 as the first layer and the nitride semiconductor layer 83 as the third layer, respectively. The roughness 84 can have a laser oscillation. When the electrode is not formed as in Fig. 7G, the nitride-containing semiconductor device structure 86 can be changed to laser oscillation by photoexcitation. When the nitride-containing semiconductor device structure 86 is changed to a laser vibration side by current injection, an electrode can be further formed. For example, a p-type low resistance Si substrate can be used as the laminated substrate 90. In this case, the 'P electrode' can be formed on the Si side. On the other hand, the ? electrode may be formed in the upper portion of the first nitride semiconductor layer 81, for example, as a portion of the second roughness 85 as a two-dimensional photonic crystal. In this example, a manufacturing method of a limited structure has been presented. However, by using the above method or the method easily inferred from the above method, the film composition (thickness of material type, individual layer and the like) and the first rough junction in the structural layer 80 such as the nitride-containing semiconductor device can be manufactured. 54- 0 0201006973 The structure of each of the structure 84 and the second coarse sugar structure 85 (the type of the rough pattern and the period, shape, size, and depth of the hole of the rough pattern) is changed. Although the invention has been described with reference to the exemplary embodiments, it is understood that the invention is not limited to the disclosed embodiments. The scope of the following claims is to be accorded the broadest interpretation to cover all such modifications and equivalent structures and functions. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing an example of a structure of a nitride-containing semiconductor layer in a first embodiment of the present invention; FIG. 2 is a view only showing a first embodiment of the present invention. The removed first nitride semiconductor layer in the structure of the nitride-containing semiconductor layer; FIG. 3 is a schematic cross-sectional view showing an example of the nitride-containing semiconductor layer composite substrate in the second embodiment of the present invention . 4 is a view showing only the detached base substrate in the structure of the nitride-containing semiconductor layer in the second embodiment of the present invention; FIGS. 5A, 5B, 5C, 5D, 5E, and 5F are depicted in FIG. An exemplary cross-sectional view of a method of fabricating a nitride-containing semiconductor layer composite substrate in a third embodiment of the present invention; FIGS. 6A, 6B, 6C, and 6D are diagrams depicting nitrogen in the fourth embodiment of the present invention. A schematic cross-sectional view of an exemplary method of fabricating a structure of a semiconductor; and 7A, 7B, 7C, 7D, 7E, 7F, and 7G are diagrams depicting nitride-containing semiconductor layer composites in embodiments and examples of the present invention -55- 201006973 Schematic cross-sectional view of the example. [Main component symbol description] 10: Base substrate 12: Projection 1 4: Base surface 1 6 : Side wall

20 :含氮化物半導體之結構 30:含氮化物半導體層複合基底 40:第一氮化物半導體層 41 :氮化物半導體 42 :凸出部 43 :凹陷部 44 :底面 45 :含結晶度缺陷部20: Structure of nitride-containing semiconductor 30: nitride-containing semiconductor layer composite substrate 40: first nitride semiconductor layer 41: nitride semiconductor 42: protrusion 43: depressed portion 44: bottom surface 45: crystallinity-containing defect portion

46 :側壁 47 :凹部 50:第二氮化物半導體層 5 1 :氮化物半導體 6 2 :空隙 6 1 :空隙 70 :方向 71、72 :部分 7 〇 :藍寶石基底側 -56- 20100697346: side wall 47: recess 50: second nitride semiconductor layer 5 1 : nitride semiconductor 6 2 : void 6 1 : void 70: direction 71, 72: part 7 〇 : sapphire base side -56- 201006973

80:含氮化物半導體裝置結構層 81、82、83 :氮化物半導體層 84 :第一粗糙結構 8 5 :第二粗糙結構 86:含氮化物半導體裝置結構 90 :疊層基底 -57-80: nitride-containing semiconductor device structure layer 81, 82, 83: nitride semiconductor layer 84: first roughness structure 8 5: second roughness structure 86: nitride-containing semiconductor device structure 90: laminated substrate - 57-

Claims (1)

201006973 七、申請專利範圍： 1. —種含氮化物半導體層之結構，其特徵在於： 該結構包含基於至少兩氮化物層之疊層結構； 該結構包含介於該疊層結構中之該兩氮化物半導體層 之間的複數空隙，該些空隙係由包含形成於爲該兩氮化物 半導體層之較低層的該氮化物半導體層上之粗糙圖案的凹 陷部之內壁的壁面所圍繞；以及 抑制該氮化物半導體層之橫向生長的含結晶度缺陷部 係形成於該些凹陷部之該些內壁的至少部分上以形成該些 空隙。 2. —種含氮化物半導體層之複合基底，其特徵在於 如申請專利範圍第1項所述之含氮化物半導體層之結 構係形成在基礎基底上。 3. 如申請專利範圍第2項所述之複合基底，其中包 含介於該基礎基底與爲該兩氮化物半導體層之較低層的該 氮化物半導體層之間的複數空隙，該些空隙係由包含形成 於爲該較低層的該氮化物半導體層上之該粗糙圖案的該些 凹陷部之該些內壁的該些壁面所圍繞。 4. 如申請專利範圍第2或3項所述之複合基底，其 中該基礎基底爲單晶體基底。 5. 如申請專利範圍第3項所述之複合基底，其中該 基礎基底爲一基礎基底，其中，在一單晶體基底上，進一 步形成有與該單晶體基底同質或異質之中間膜。 -58- 201006973 6. 如申請專利範圍第2項所述之複合基底，其中該 單晶體基底之材料爲氮化物半導體、藍寶石、矽（Si)及 碳化矽（SiC)之任一者。 7. —種含氮化物半導體層之複合基底的製造方法， 其特徵在於包含： 於基礎基底上形成第一氮化物半導體層之第一步驟； 於該第一氮化物半導體層上形成粗糙圖案之第二步驟 ❹ 於該第一氮化物半導體層之該粗糙圖案中之凹陷部的 內壁之至少部分上形成因自單晶體狀態變更的狀態而造成 的含結晶度缺陷部之第三步驟；以及 於形成在該第一氮化物半導體層上且包括該含結晶度 缺陷部的該粗糙圖案上形成第二氮化物半導體層之第四步 驟。 8. 如申請專利範圍第7項所述之複合基底的製造方 φ 法’其中該第一步驟爲藉由於基礎基底上形成粗糙圖案及 藉由在該粗糙圖案上進行氮化物半導體層的磊晶橫向過度 生長來形成該第一氮化物半導體層的連續層之步驟。 9. 如申請專利範圍第7或8項所述之複合基底的製 造方法’其中該第四步驟爲藉由進行氮化物半導體層的磊 晶橫向過度生長來形成該第二氮化物半導體層的連續層之 步驟。 10. 如申請專利範圍第7或8項所述之複合基底的製 造方法，其中在進行過第四步驟一次之後，分別進一步重 -59- 201006973 複該第二及該第四步驟N次（N20)，並且進一步重複 該第三步驟Μ次（MSN)。 11. 一種含氮化物半導體層之結構的製造方法，其特 徵在於包含： 藉由使用如申請專利範圍第7所述之複合基底的製造 方法來製造複合基底之步驟；以及 從該製造方法所製造的該複合基底移除基礎基底之步 驟。 12. 如申請專利範圍第11項所述之結構的製造方法 ’其中該移除該基礎基底的步驟包含藉由選擇性蝕刻或拋 光來移除該基礎基底之步驟。 13. 如申請專利範圍第11項所述之結構的製造方法 ’其中該移除該基礎基底的步驟爲一步驟，其中將如申請 專利範圍第5項所述之該基礎基底用爲該基礎基底並藉由 選擇性蝕刻來移除該中間膜。 14. 如申請專利範圍第11項所述之結構的製造方法 ’其中該移除該基礎基底的步驟爲一步驟，其中： 藍寶石用爲該基礎基底並從該基礎基底側進行雷射照 射；以及 在該藍寶石基底及該含氮化物半導體層的結構之間的 介面中分解該第一氮化物半導體層。 15_如申請專利範圍第π項所述之結構的製造方法 ’其中該移除該基礎基底的步驟爲一步驟，其中將如申請 專利範圍第5項所述之該基礎基底用爲該基礎基底並藉由 -60- 201006973 光電化學蝕刻來選擇性移除該基礎基底的該中間膜。 16.如申請專利範圍第11項所述之結構的製造方法 ’其中該移除該基礎基底的步驟包含一步驟，其中該含氮 化物半導體層之結構係接合至第二基底並接著移除該基礎 基底。201006973 VII. Patent application scope: 1. A structure containing a nitride semiconductor layer, characterized in that: the structure comprises a stacked structure based on at least two nitride layers; the structure comprises the two in the laminated structure a plurality of voids between the nitride semiconductor layers, the voids being surrounded by a wall surface including an inner wall of the depressed portion formed on the nitride semiconductor layer of the lower layer of the two nitride semiconductor layers; And a crystallinity-containing defect portion that suppresses lateral growth of the nitride semiconductor layer is formed on at least a portion of the inner walls of the recess portions to form the voids. A composite substrate comprising a nitride semiconductor layer, characterized in that the structure of the nitride-containing semiconductor layer according to claim 1 is formed on a base substrate. 3. The composite substrate of claim 2, comprising a plurality of voids between the base substrate and the nitride semiconductor layer that is a lower layer of the two nitride semiconductor layers, the void systems The wall faces of the inner walls of the recesses formed in the rough pattern formed on the nitride semiconductor layer of the lower layer are surrounded. 4. The composite substrate of claim 2, wherein the base substrate is a single crystal substrate. 5. The composite substrate of claim 3, wherein the base substrate is a base substrate, wherein an intermediate film that is homogenous or heterogeneous to the single crystal substrate is further formed on a single crystal substrate. 6. The composite substrate of claim 2, wherein the material of the single crystal substrate is any one of a nitride semiconductor, sapphire, bismuth (Si), and tantalum carbide (SiC). 7. A method of fabricating a composite substrate comprising a nitride semiconductor layer, comprising: a first step of forming a first nitride semiconductor layer on a base substrate; forming a rough pattern on the first nitride semiconductor layer a second step of forming a third step containing a crystallinity defect portion due to a state changed from a single crystal state on at least a portion of an inner wall of the depressed portion in the rough pattern of the first nitride semiconductor layer; A fourth step of forming a second nitride semiconductor layer on the rough pattern including the crystallinity defect portion formed on the first nitride semiconductor layer. 8. The method of manufacturing a composite substrate according to claim 7, wherein the first step is by forming a rough pattern on the base substrate and performing epitaxy of the nitride semiconductor layer on the rough pattern. The step of lateral overgrowth to form a continuous layer of the first nitride semiconductor layer. 9. The method of manufacturing a composite substrate according to claim 7 or 8, wherein the fourth step is to form a continuous layer of the second nitride semiconductor layer by performing epitaxial lateral overgrowth of the nitride semiconductor layer. The steps of the layer. 10. The method of manufacturing a composite substrate according to claim 7 or 8, wherein after the fourth step is performed once, the second and the fourth step are further repeated N times (N20). ), and the third step (MSN) is further repeated. A method of producing a structure containing a nitride semiconductor layer, comprising: a step of manufacturing a composite substrate by using a method of manufacturing a composite substrate according to claim 7; and manufacturing the same from the manufacturing method The step of removing the base substrate from the composite substrate. 12. The method of manufacturing the structure of claim 11, wherein the step of removing the base substrate comprises the step of removing the base substrate by selective etching or polishing. 13. The method of manufacturing the structure of claim 11, wherein the step of removing the base substrate is a step in which the base substrate as described in claim 5 is used as the base substrate. The intermediate film is removed by selective etching. 14. The method of manufacturing the structure of claim 11, wherein the step of removing the base substrate is a step wherein: sapphire is used as the base substrate and laser irradiation is performed from the base substrate side; The first nitride semiconductor layer is decomposed in an interface between the sapphire substrate and the structure of the nitride semiconductor layer. 15_ The manufacturing method of the structure as described in the § π of the patent application, wherein the step of removing the base substrate is a step in which the base substrate as described in claim 5 of the patent application is used as the base substrate The intermediate film of the base substrate is selectively removed by photoelectrochemical etching of -60-201006973. 16. The method of manufacturing the structure of claim 11, wherein the step of removing the base substrate comprises a step of bonding the nitride semiconductor layer-containing structure to the second substrate and then removing the Base substrate. ❹ -61 -❹ -61 -
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