JP2006232640A - R surface sapphire substrate, epitaxial substrate using the same, semiconductor device, and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing an epitaxial substrate which can grow an A axis oriented nitride-based semiconductor on an R surface sapphire substrate in a selected transverse direction, and to provide an epitaxial substrate manufactured by this method which has a low threading dislocation density and an excellent surface flatness. <P>SOLUTION: The method can grow a nitride-based semiconductor layer 15 via underlying layers 13, 14 or not on an R surface sapphire substrate 4 which has alternately a concave groove 11c and a convex terrace 11b on its main surface, wherein the width of the groove is 0.5-30 μm and its depth is 0.3-3 μm and the width of the terrace is 0.5-5 μm. When growing the nitride-based semiconductor layer, the growth in the selected transverse direction is accelerated by setting the ratio of the feeding amount of the group V material against the feeding amount of the group III material to 0.01-100. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a sapphire substrate, an epitaxial substrate made of a nitride semiconductor, and a semiconductor device using the same.

  Aluminum nitride (hereinafter referred to as AlN), gallium nitride (hereinafter referred to as GaN), indium nitride (hereinafter referred to as InN), or aluminum gallium indium nitride (hereinafter referred to as AlxGa1-xyInyN) which is a mixed crystal thereof. Nitride-based semiconductors such as (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) can be used for light emitting / receiving elements and electron transit elements. A wide range of research has been conducted on application to devices, and some light-emitting diodes and laser diodes have already been put into practical use.

  Since a nitride-based semiconductor cannot grow a large bulk single crystal, in general, (0001) sapphire (hereinafter referred to as C-plane sapphire), (11-20) sapphire, or (0001) 4H—SiC, (0001 ) Heteroepitaxial growth is performed using a substrate such as 6H-SiC.

  Epitaxial growth methods include metalorganic vapor phase epitaxy (MOVPE), molecular beam epitaxy (MBE), and halide vapor phase epitaxy (HVPE). The most common method for practical use is MOVPE. .

  As described above, nitride-based semiconductors used in semiconductor devices that have already been put into practical use have large piezoelectric properties due to the fact that the crystal structure is a hexagonal Wurtz steel structure that does not have reversibility. It has sex. FIG. 10 shows a heterojunction of a nitride semiconductor in which two layers (first layer 101 and second layer 102) made of different materials are stacked, but all crystal growth directions are heterojunctions. The interface 101a is orthogonal to the C axis 103, which is called C axis orientation. Therefore, when a heterojunction formed by laminating two layers having different lattice constants, a large piezo electric field is generated due to strain in the crystal.

  For example, in the case of a light-emitting device such as a light-emitting diode or a laser diode, if a C-axis oriented crystal is used, the piezo electric field is generated in an active layer composed of a heterojunction such as a multiple quantum well structure, and the band structure changes. This reduces the recombination probability of carriers. For this reason, the improvement in luminance is hindered, and there is a limit even if the growth conditions are optimized, so that it is difficult to manufacture a high-luminance light-emitting device.

  As described above, the problem of the piezo electric field in the nitride-based semiconductor greatly affects the characteristics of the semiconductor device. However, as a crystal growth method that does not have the problem due to the piezo electric field, the (11-20) orientation (hereinafter referred to as the A-axis) It is already reported in Non-Patent Document 1 that the alignment may be performed) or (10-10) alignment.

  While there is no effective method for orienting a nitride-based semiconductor in (10-10), as a method for orienting a nitride-based semiconductor in (11-20), a (1-102) sapphire substrate (hereinafter, Non-Patent Document 2 describes a method using an R-plane sapphire substrate, and Non-Patent Document 3 describes a method of growing AlN on a (11-20) 4H—SiC substrate. Among these, the latter method is not suitable because it is difficult to increase the size and the mass productivity is poor in the current technology for producing the (11-20) 4H—SiC substrate itself. On the other hand, the R-plane sapphire substrate can already be manufactured as an 8-inch substrate, and there is no problem with the substrate diameter.

  Further, considering the fact that a semiconductor device manufacturing process similar to a semiconductor device using silicon can be used, and that it can be applied in conjunction with an SOS (silicon on sapphire) device, the industrial attractiveness is great. Therefore, a method of growing a nitride-based semiconductor on an R-plane sapphire substrate is considered to be most advantageous from the viewpoint of mass productivity and cost.

  In addition, a prototype example of a light emitting device has already been reported, and Non-Patent Document 4 discloses a GaN / GaInN multiple quantum well structure light emitting device in which a (11-20) -plane GaN layer is formed on an R-plane sapphire substrate. Prototype examples have already been reported. According to the above document, as shown in FIG. 11, an n-type GaN layer (30 μm) 112 and an n-type Al0.1Ga0.9N clad layer (100 nm) are formed on a sapphire substrate 111 having an R plane as a main surface by the MOVPE method. 113, a GaN / In0.15Ga0.85N multiple quantum well structure active layer 114, a p-type Al0.1Ga0.9N cladding layer (50 nm) 115, and a p-type GaN layer (200 nm) 116 are sequentially stacked. Then, mesa processing by reactive ion etching and formation of the p-side electrode 117 and the n-side electrode 118 are performed to form a light emitting device.

  When a nitride meter semiconductor is grown on an R-plane sapphire substrate, the large lattice constant difference, a large number of threading dislocations due to the nonpolarity of sapphire, and stacking faults are introduced, and The present inventors and other studies have revealed that there is a problem of a poor crystal form that makes it difficult to form a steep interface necessary for manufacturing a semiconductor device.

  Non-Patent Document 5 shows selective lateral growth as one method for reducing threading dislocation density. As shown in FIG. 12, after a GaN layer 121 is grown by MOVPE method on a sapphire substrate 111 having an R plane as a main surface, a mask 122 made of SiO 2 is formed by existing photolithography technique and wet etching technique. Then, the regrowth GaN layer 123 is regrowth by MOVPE. By this method, the mask 122 prevents the threading dislocations from propagating to the regrowth layer, and the threading dislocation density is reduced.

  However, this paper only observed the dislocation behavior in the regrowth GaN layer 123 by changing the arrangement direction of the mask 122 with respect to the crystal orientation of the GaN layer, and the dimensions of the mask 122 have been studied. Not.

Further, Patent Document 1 discloses selective lateral growth after performing periodic step groove processing on a sapphire substrate, and Non-Patent Document 6 discloses selective lateral growth after performing periodic step groove processing on a nitride-based semiconductor layer. In addition, Patent Document 2 discloses selective lateral growth using a mask on a nitride-based semiconductor layer, respectively. These show a reduction in threading dislocation density by selective lateral growth, but all use a C-axis oriented nitride-based semiconductor layer. And there are some which prescribe the dimension. However, because the growth mechanism of the A-axis-oriented nitride semiconductors taken up this time is completely different from that of the C-axis-oriented ones, those findings are not applicable at all. This is because the lattice constant matching problem varies greatly depending on whether the sapphire substrate plane orientation is the C plane or the R plane due to the anisotropy of the atomic arrangement of sapphire.
Japanese Journal of Applied Physics, Vol.39 (2000) 413-416 Japanese Journal of Applied Physics, Vol. 42 (2003) L818-820 Applied Physics Letters Vol. 83, (2003) 5208-5210 Applied Physics Letters Vol. 84, (2004) 3663-3665 Applied Physics Letters, Vol. 81 (2002) 1201-1203 Published patent publication JP 2000-106455 Journal of Crystal Growth 272 (2004) 377-380 Published patent publication JP 2004-262757

  In view of the above, the present invention provides selective lateral growth for growing an A-axis-oriented nitride-based semiconductor on an R-plane sapphire substrate with low threading dislocation density and excellent surface flatness over the entire surface of the substrate. This makes it possible to provide an epitaxial substrate capable of manufacturing a high-performance semiconductor device such as a light emitting diode, a laser diode, or a transistor.

  In view of the above, the present invention has concave groove portions and convex terrace portions alternately on the main surface of a sapphire substrate having an R surface, and the groove portions have a width of 0.5 to 30 μm and a depth of An R-plane sapphire substrate having a thickness of 0.3 to 3 μm and a terrace portion width of 0.5 to 5 μm.

  Furthermore, a nitride-based semiconductor layer having an A surface as a main surface is provided on the main surface of the R-plane sapphire substrate.

  The epitaxial substrate according to claim 2, wherein the groove is filled with the nitride semiconductor layer.

  Further, the semiconductor device has a semiconductor element structure on the nitride-based semiconductor layer.

  Furthermore, the epitaxial substrate is used.

  Further, the nitride semiconductor layer is selectively grown in the lateral direction on the sapphire substrate.

A step of disposing a mask that does not generate crystal nuclei of the nitride semiconductor on the R-plane sapphire substrate;
And a step of selectively growing the nitride-based semiconductor layer in the lateral direction.

  Furthermore, the width between the masks is 0.5 to 30 μm, the width of the mask is 0.5 to 5 μm, and the height is 0.05 to 3 μm.

  Further, the ratio of the supply amount of the group V raw material to the supply amount of the group III raw material when growing the nitride-based semiconductor layer is set to 0.01 to 100.

  The present invention enables selective lateral growth for growing an A-axis oriented nitride-based semiconductor on an R-plane sapphire substrate with low threading dislocation density and excellent surface flatness, and a high-performance light-emitting diode. It is possible to provide an epitaxial substrate on which a laser diode can be manufactured.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a cross-sectional view showing the structure of an epitaxial substrate of a nitride semiconductor of the present invention when a periodic step groove structure is formed on an R-plane sapphire substrate and then grown by selective lateral growth.

  Periodic step groove processing is performed on the surface of the R-plane sapphire substrate 4 to form a groove 11c and a terrace 11b. On top of this, a first underlayer 13 and a second underlayer 14 are successively grown, and then a nitride-based semiconductor layer 15 is finally grown. The nitride-based semiconductor layer 15 grows selectively in the lateral direction, fills the periodic step groove structure formed in the R-plane sapphire substrate 11, and becomes the epitaxial substrate 1.

  Next, a method for manufacturing the epitaxial substrate 1 of FIG. 1 will be described.

  First, as shown in FIG. 2, a line-and-space mask 12 is formed on the R-plane sapphire substrate 11 using a photolithography technique and a vapor deposition technique. The periodic structure at that time is such that the mask portion 11b is not less than 0.5 μm and not more than 5 μm, and the width of the mask opening portion 11a is not less than 0.5 μm and not more than 30 μm. The height of the mask 12 is defined by the selection ratio of the materials of the R-plane sapphire 11 and the mask 12 in etching performed later, and it is desirable that the mask 12 be thicker than necessary.

  Next, as shown in FIG. 3, a part of the mask opening 11a on the surface of the R-plane sapphire substrate 11 is removed by etching to form a groove 11c. Since the mask portion 11b is not etched, it becomes the terrace portion 11b, and a periodic step groove structure is formed. For the etching method of the R-plane sapphire substrate 11, an existing technique may be used, and dry etching using a chlorine-based or fluorine-based gas is generally used. In this case, the mask 12 may be made of nickel or silicon oxide, but other materials may be used.

  Next, as shown in FIG. 4, the mask 12 is removed from the surface of the R-plane sapphire substrate 11. An appropriate chemical solution is selected according to the material of the mask 12. In this way, an R-plane sapphire substrate 4 having a periodic step groove structure is obtained.

  Next, a nitride-based semiconductor layer 15 is grown on the R-plane sapphire substrate 4 by MOVPE as shown in FIG. By controlling the film thickness and composition and sequentially laminating the first underlayer 13 and the second underlayer 14, an A-axis oriented nitride system having a flat surface and relatively good crystallinity is formed thereon. The semiconductor layer 15 can be grown. Although it is preferable to use AlN as the first underlayer 13 and Al0.5Ga0.5N as the second underlayer 14, this is not a point to be noted in the present invention. Therefore, if planarization is performed, the combination of the underlayers 11 and 12 is not limited, and the underlayer may be formed of only one layer, or may be directly nitrided without using the underlayer. The physical semiconductor layer 15 may be grown on the R-plane sapphire substrate 4.

  The V / III ratio is the ratio of the supply amount of ammonia (hereinafter referred to as NH3), which is a Group V material, to the supply amount of organic metal, which is a Group III material during growth. For example, 4000 μmol / min. When NH3 and 80 μmol / min trimethylgallium (hereinafter referred to as TMG) are supplied, the V / III ratio is 50. However, when the nitride-based semiconductor layer 15 is grown, the V / III ratio is It is good to set it as 0.01-100. By performing growth at a V / III ratio in this range, selective lateral growth is promoted, and the surface of the second underlayer 14 is flattened by embedding the uneven shape. V / III ratios below 0.01 are difficult to control and difficult to implement. On the other hand, when the V / III ratio is 100 or more, growth pits are formed on the surface of the nitride-based semiconductor layer 15 and flattening is impossible. This is because the growth rate anisotropy changes depending on the V / III ratio, and the crystal of the nitride-based semiconductor layer 15 does not extend in the lateral direction.

  In general, in the case of a nitride-based semiconductor with C-axis orientation, selective lateral growth is promoted by increasing the V / III ratio, so that the V / III ratio is further increased. Of course, depending on the material to be laminated, for example, in the case of GaN, it is often 600 or more and 2000 or less. In this respect, the selective lateral growth of the A-axis-oriented nitride-based semiconductor layer 15 grown on the R-plane sapphire substrate 11 is unique.

  In addition, as for the dimension of the periodic step groove processing formed on the sapphire substrate, a lot of threading dislocations are generated in the nitride-based semiconductor layer 15 in the mask portion of the line and space mask. The width should be small. However, if the width is too small, it is difficult to produce a mask. In addition, since the domain size of the first underlayer 13 or the second underlayer 14 at the initial growth stage is 1 to 3 μm, the width of the mask portion is desirably 5 μm or less, preferably 3 μm or less. There should be.

  A groove 11c is formed in the mask opening 11a in the line and space mask by etching. The selective lateral growth starts from the side wall, and the threading dislocations propagate in the lateral direction, so that the dislocations extending in the film thickness direction can be reduced, which contributes to the reduction of the threading dislocation density of the nitride-based semiconductor layer 15.

  Similarly to the mask portion 11b, the width of the mask opening portion 11a is preferably 0.5 μm or more because it is difficult to manufacture the mask 12 if the width is too small. If the width on the mask opening 11a is too wide, the initial growth domain of the nitride-based semiconductor layer 15 grows also from the bottom of the trench and grows in the film thickness direction, making it difficult to reduce the threading dislocation density. In the C-axis oriented nitride semiconductor layer, about 20 μm is the limit, but in the case of the A-axis oriented nitride semiconductor layer 15 grown on the R-plane sapphire substrate 4, the groove 11 c up to 30 μm is formed. It is possible to use. This is because, due to the growth orientation dependence, it is more advantageous to promote the growth of the domain that is growing in the selected lateral direction than the growth from the bottom of the groove 11c.

  Further, the depth of the periodic step groove structure on the surface of the R-plane sapphire substrate 4 formed by the etching method is preferably 0.3 μm or more, preferably 0.5 μm or more in order to obtain the effect of reducing the dislocation density. Good. On the other hand, since it is difficult to process sapphire that is mechanically robust and chemically stable, it is difficult to form a periodic step groove structure having a depth of 3 μm or more. In addition, the growth of the nitride-based semiconductor layer 15 for embedding deep grooves is not preferable because it takes a long time.

  The A-axis-oriented nitride-based semiconductor 15 grown as described above is excellent in surface flatness, and an improvement in light emission characteristics due to improvement in crystallinity is observed by a photoluminescence method or the like. In this way, the epitaxial substrate 5 is produced.

    Next, another embodiment of the present invention will be described. FIG. 5 is a cross-sectional view in the case where the nitride-based semiconductor layer grown on the R-plane sapphire substrate is subjected to periodic step groove processing and selectively grown in the lateral direction by regrowth.

  First, as in the first embodiment, the first underlayer 52 and the second underlayer 53 are first formed on the R-plane sapphire substrate 51 by controlling the film thickness and composition by the MOVPE method. By sequentially laminating, it is possible to grow the nitride-based semiconductor layer 54 having a flat surface and relatively high crystal quality and A-axis orientation. Thereafter, the sample is once removed from the reactor.

  Next, as shown in FIG. 6, a line-and-space mask 55 is formed on the nitride-based semiconductor layer 54 using a photolithography technique and a vapor deposition technique. As in the first embodiment, the periodic structure at that time is such that the width of the mask opening 54a is not less than 0.5 μm and not more than 30 μm, and the mask portion 55b is not less than 0.5 μm and not more than 5 μm. . The thickness of the mask 55 is defined by the selection ratio of the materials of the R-plane sapphire 51 and the mask 55 in the etching performed later, and it is desirable that the mask 55 be thicker than necessary.

  Next, a part of the mask opening on the surface of the nitride-based semiconductor layer 54 is removed by an etching method. The nitride semiconductor layer 15 may be etched using an existing technique, and dry etching using a chlorine-based or fluorine-based gas is generally used. The mask 55 is preferably made of nickel or silicon oxide, but may be other than this. Further, if there is an appropriate mask material and etching solution, wet etching may be performed.

  Next, an appropriate chemical solution is selected according to the material of the mask, and the mask 55 is removed from the surface of the nitride-based semiconductor layer 54.

  Thereafter, as shown in FIG. 7, the nitride-based semiconductor regrowth layer 56 is regrown on the nitride-based semiconductor layer 54 by MOVPE. The V / III ratio during growth is preferably 0.01 to 100 as in the first embodiment.

  In addition, with respect to the dimension of the periodic step groove formed in the nitride-based semiconductor layer 54, the width of the mask portion in the line-and-space mask 55 is 0.5 μm to 5 μm for the same reason as described above. It is good to do.

  The width of the mask opening 54a in the line and space mask is preferably 0.5 μm or more and 30 μm or less for the same reason as described above. In the mask opening 54a in the line and space mask, a groove 54c is formed by etching. Accordingly, selective lateral growth starts from the sidewall of the periodic step groove formed in the nitride-based semiconductor layer 54, and threading dislocations propagate in the lateral direction, so that dislocations extending in the film thickness direction can be reduced, and nitriding This contributes to the reduction of the threading dislocation density of the physical semiconductor layer 55. By doing so, it is possible to grow so as to bury the periodic step groove structure formed in the nitride-based semiconductor layer 54.

  Further, the depth of the groove 54c of the nitride-based semiconductor layer 54 formed by the etching method is preferably 0.3 μm or more, and preferably 0.5 μm or more in order to sufficiently obtain the effect of reducing the dislocation density. On the other hand, since the growth of the nitride-based semiconductor layer 15 for filling the deep groove is not preferable because it takes a long time, the depth of the groove 54c is preferably 3 μm or less.

  The A-axis oriented nitride-based semiconductor 55 grown as described above is excellent in surface flatness, and an improvement in light emission characteristics due to improvement in crystallinity is observed by a photoluminescence method or the like. In this way, the epitaxial substrate 5 is produced.

  Next, still another embodiment of the present invention will be described. FIG. 8 is a cross-sectional view when a mask periodically arranged on a nitride-based semiconductor layer is formed and the mask is embedded by selective lateral regrowth of the nitride-based semiconductor layer.

  First, the nitride semiconductor layer 84 is grown on the R-plane sapphire substrate 11 by the MOVPE method. Similar to the first embodiment, the first base layer 82 and the second base layer 83 are first laminated sequentially by controlling the film thickness and composition, so that the surface is flat and relatively crystalline. A nitride semiconductor layer 84 with high quality A-axis orientation can be grown. Thereafter, the sample is taken out once.

  Next, a line-and-space mask is formed on the nitride-based semiconductor layer 84 by using a photolithography technique and a vapor deposition technique. As in the first embodiment, the periodic structure at that time is such that the width of the mask opening 84a is not less than 0.5 μm and not more than 30 μm, and the width of the mask 85 is not less than 0.5 μm and not more than 5 μm. .

  Thereafter, the nitride semiconductor layer 84 is regrown on the nitride semiconductor layer 84 by MOVPE. The V / III ratio at the time of growth is preferably 0.01 to 100 as in the first embodiment. By doing so, the regrowth starts from the mask opening 84a, and the nitride-based semiconductor regrowth layer 86 gradually grows so as to cover the mask 85, and finally the mask 85 can be embedded. is there. Since the threading dislocations propagate in the lateral direction during the selective lateral growth, the dislocations extending in the film thickness direction can be reduced, which contributes to the reduction of the threading dislocation density in the nitride-based semiconductor regrowth layer 86.

  If the height of the mask 85 is 0.05 μm or more, the propagation of threading dislocation density can be sufficiently shielded. When the mask 85 having a large height is used, the growth of the nitride-based semiconductor layer 84 for filling the mask 85 is not preferable because it takes a long time. Therefore, the depth of the periodic step groove is preferably 5 μm or less.

  The A-axis oriented nitride semiconductor 85 grown as described above is excellent in surface flatness, and an improvement in light emission characteristics due to improvement in crystallinity is observed by a photoluminescence method or the like. In this way, the epitaxial substrate 8 is produced.

  Moreover, although the epitaxial substrate described in any of the above three embodiments has been stacked only up to the nitride-based semiconductor layer, it may have a semiconductor element structure.

  Examples of the semiconductor element structure include a light emitting diode, a laser diode, a field effect transistor, and a bipolar transistor. The semiconductor element structure can be formed by existing technology, but the nitride-based semiconductor layer has a low dislocation density.

  Therefore, this epitaxial substrate can produce a semiconductor device with good characteristics. In the case of a field effect transistor, an enhancement type operation can be performed by utilizing the fact that a piezoelectric field is not applied.

  Examples of the present invention will be described below.

(First embodiment)
A case where periodic step groove processing is performed on the R-plane sapphire substrate will be described.

  First, as shown in FIG. 2, a line-and-space mask 12 made of nickel was formed on the R-plane sapphire substrate 11 by using a photolithography technique and a vapor deposition technique. The film thickness was 150 nm. In addition, the periodic structure has a mask portion 11b width of 3 μm and a mask opening portion 11a width of 15 μm.

  Next, a part of the mask opening 11a on the sapphire surface was removed by reactive ion etching using chlorine to form a groove 11c. The depth was 2 μm.

  Next, the mask 12 was removed from the surface of the sapphire substrate 11 using aqua regia. In this way, a sapphire substrate 4 having a periodic step groove structure was produced.

  Next, 100 nm of the first underlayer 13 made of AlN and the second underlayer 14 made of Al0.5Ga0.5N were successively grown at a growth temperature of 1100 ° C. by the MOVPE method. During the growth of these layers, the V / III ratio was 800. Thereafter, the V / III ratio during growth was reduced to 60, and a nitride-based semiconductor layer 15 made of GaN was stacked. As a result, the periodic step groove structure formed in the R-plane sapphire substrate 4 was filled, and the nitride-based semiconductor layer 15 having a flat surface was obtained. X-ray diffraction confirmed that it was A-axis oriented, and when this surface was measured with an atomic force microscope (hereinafter referred to as AFM), the root mean square surface roughness was 0.3 nm. Further, the light emission distribution of the nitride-based semiconductor layer 15 was examined by a microphotoluminescence method using a helium-cadmium laser as a light source. The result is shown in FIG. Thereafter, a clear contrast corresponding to the periodic groove structure was confirmed, and in particular, the selected lateral growth region formed in the mask opening 11a was brightly lit. The light emission intensity ratio of the adjacent mask part 11b and the groove part 11c reached about 20 times. It can be presumed that the crystallinity is improved by selective lateral growth.

  The following experiments were conducted to evaluate surface flatness and threading dislocation density due to changes in the shape of the periodic step groove structure.

  First, in the line-and-space mask, the dimensions of the mask opening 11a and the mask portion 11b and the depth of the periodic step groove structure are variously changed to produce R-plane sapphire substrates 4 having various periodic step groove structures. did. Next, a structure similar to the above is grown on each R-plane sapphire substrate 4 by the MOVPE method, the surface flatness is measured using AFM, and the threading dislocation density is measured by observation with a plane transmission electron microscope (TEM). evaluated.

The results are shown in Table 1.

  When the conditions 1-15 (Examples 1-11 and Comparative Examples 1-4) which changed the groove part 11c width are compared, the conditions 13-15 (Comparative Examples 2-4) where the condition groove part 11c width is larger than 30 micrometers In this case, the RMS surface roughness is rough on the order of nm, and the threading dislocation density is 109 / cm 2, which is not suitable because the crystallinity is not good. Therefore, the width of the groove 11c is preferably 30 μm or less. On the other hand, as in Condition 1 (Comparative Example 1), when trying to produce a pattern having a groove 11c width of 0.4 μm by photolithography, it was too precise and difficult to produce. Therefore, as in Conditions 2 to 12 (Examples 1 to 11), the width of the groove 11c is preferably 0.5 μm or more and 30 μm or less.

  Moreover, when the conditions 16-22 (Examples 12-16 and Comparative Examples 5 and 6) which changed the terrace part 11b width are compared, in the case of the condition 22 (Comparative Example 6) where the terrace part 11b width is larger than 5 μm Is not suitable because the RMS surface roughness is rough on the order of nm, and the threading dislocation density is 109 / cm 2 or more, resulting in poor crystallinity. Therefore, the width of the groove 11c is preferably 5 μm or less. On the other hand, as in Condition 16 (Comparative Example 5), an attempt was made to produce a pattern with a groove 11c width of 0.4 μm by photolithography, but it was too precise and difficult to produce. That is, the groove width is preferably 0.5 μm or more and 5 μm or less as in Conditions 17 to 21 (Examples 12 to 16).

  Moreover, when the conditions 23-30 (Examples 17-22 and Comparative Examples 7 and 8) which changed the groove part 11c depth are compared, the depth of less than 0.3 micrometer like the conditions 23 (Comparative Example 7). Then, the selective lateral growth of the nitride-based semiconductor layer 15 is not sufficient, and crystal nucleation occurs from the groove 11c, so that the threading dislocation density is 109 / cm 2 or more and the crystallinity is not good. As in the conditions 24 to 30 (Examples 17 to 22 and Comparative Example 8), the threading dislocation density can be reduced by increasing the depth of the groove 11c, but the nitride-based semiconductor layer 15 necessary to fill the step is required. The growth time needs to be long. Since this leads to an increase in manufacturing cost, Condition 30 (Comparative Example 8) in which embedding is not completed within 120 minutes is not preferable. Accordingly, the groove depth is preferably set to 0.3 μm or more and 3 μm or less as in Conditions 24 to 29 (Examples 17 to 22).

(Second embodiment)
Hereinafter, a case where a nitride-based semiconductor layer is formed and regrowth is performed after performing periodic step groove processing will be described.

  First, as shown in FIG. 6, the first underlayer 52 made of AlN is grown on the R-plane sapphire substrate 51 at a growth temperature of 1100 ° C. by the MOVPE method to a thickness of 100 nm and the second underlayer made of Al0.5Ga0.5N. 53 were grown sequentially by 200 nm. During the growth of these layers, the V / III ratio was 800. Thereafter, the V / III ratio during growth was reduced to 60, and a nitride-based semiconductor layer 54 made of GaN was laminated to 2 μm. It was confirmed by X-ray diffraction that it was A-axis oriented, and when this surface was measured by AFM, the square root average surface roughness was 0.3 nm.

  A line-and-space mask 55 made of nickel was formed on the R-plane sapphire substrate 51 using a photolithography technique and a vapor deposition technique. The film thickness was 150 nm. Further, the periodic structure is such that the terrace portion 54b is 3 μm and the width of the mask opening 54a is 15 μm.

  Next, as shown in FIG. 7, a part of the mask opening 54a of the nitride-based semiconductor layer 54 was removed by reactive ion etching using chlorine. The depth was 2 μm.

  Next, the mask 55 was removed from the surface of the nitride-based semiconductor layer 54 using aqua regia. In this way, a nitride-based semiconductor layer 54 having a periodic step groove structure was produced.

  After that, as shown in FIG. 5, the nitride-based semiconductor layer 55 was regrown on the nitride-based semiconductor layer 54 by the MOVPE method. The V / III ratio during growth was 60. As a result, the periodic step groove structure formed in the nitride-based semiconductor layer 54 was filled, and a nitride-based semiconductor layer 55 having a flat surface was obtained. When this surface was measured by AFM, the surface roughness of the root mean square was 0.3 nm.

  The following experiments were conducted to evaluate surface flatness and threading dislocation density due to changes in the shape of the periodic step groove structure.

  First, a structure similar to the above was grown on each R-plane sapphire substrate 51 by the MOVPE method. Next, the line and space mask is adjusted to adjust the dimensions of the groove 54c and the terrace 54b, and the etching conditions are adjusted to change the depth of the periodic step groove structure. A nitride-based semiconductor layer 54 was produced. Further, the nitride-based semiconductor layer 55 was regrown by the MOVPE method, and the surface flatness using AFM and the threading dislocation density were evaluated by planar TEM observation.

The results are shown in Table 2.

  When the conditions 31 to 45 (Examples 23 to 33 and Comparative Examples 9 to 12) in which the groove 54c width is changed are compared, the conditions 43 to 45 (Comparative Examples 10 to 12) in which the groove 54c width is greater than 30 μm Is not suitable because the RMS surface roughness is rough on the order of nm, and the threading dislocation density is 109 / cm 2, resulting in poor crystallinity. Therefore, the width of the groove 54c is preferably 30 μm or less. On the other hand, as in Condition 31 (Comparative Example 9), an attempt was made to produce a pattern with a groove 54c width of 0.4 μm by photolithography, but it was too precise and difficult to produce. Therefore, as in conditions 32 to 42 (Examples 23 to 33), the width of the groove 54c is preferably 0.5 μm or more and 30 μm or less.

  Further, when the conditions 46 to 52 (Examples 34 to 38 and Comparative Examples 13 and 14) in which the width of the terrace portion 54b is changed are compared, the condition 52 (Comparative Example 14) in which the terrace portion 54b width is greater than 5 μm is compared. Is not suitable because the RMS surface roughness is rough on the order of nm, and the threading dislocation density is 109 / cm 2 or more, resulting in poor crystallinity. Therefore, the width of the terrace portion 54b is preferably 5 μm or less. On the other hand, as in Condition 46 (Comparative Example 13), an attempt was made to produce a pattern having a terrace portion 54b width of 0.4 μm by photolithography, but it was too precise and difficult to produce. Therefore, as in the conditions 47 to 51 (Examples 34 to 38), the width of the terrace portion 54b is preferably 0.5 μm or more and 5 μm or less.

  Further, when the conditions 53 to 60 (Examples 39 to 44 and Comparative Examples 15 and 16) in which the depth of the groove 54c part is changed are compared, the condition 53 (Comparative Example 15) is less than 0.3 μm. At the depth, the selective lateral growth of the nitride-based semiconductor layer 55 is not sufficient, and crystal nucleation occurs from the groove, so that the threading dislocation density is 109 / cm 2 or more and the crystallinity is not good. As in the conditions 54 to 60 (Examples 39 to 44 and Comparative Example 16), the threading dislocation density can be reduced by increasing the depth of the groove 54c, but the nitride-based semiconductor layer 55 necessary to fill the step is required. The growth time needed to be long. Since this leads to an increase in manufacturing cost, the condition 60 (Comparative Example 16) in which the embedding is not completed within 120 minutes is not preferable. Therefore, as in conditions 54 to 59 (Examples 39 to 44), the groove depth is preferably 0.3 μm or more and 3 μm or less.

(Third embodiment)
A case will be described below in which a nitride-based semiconductor layer is formed, a mask is formed, and then the mask is embedded by regrowth.

  First, as shown in FIG. 8, the first underlayer 82 made of AlN is grown on the R-plane sapphire substrate 81 at a growth temperature of 1100 ° C. by the MOVPE method, and the second underlayer made of Al0.5Ga0.5N is 100 nm. 83 was grown sequentially by 200 nm. During the growth of these layers, the V / III ratio was 800. Thereafter, the V / III ratio during growth was reduced to 60, and a nitride-based semiconductor layer 84 made of GaN was laminated to 2 μm. It was confirmed by X-ray diffraction that it was A-axis oriented, and when this surface was measured by AFM, the square root average surface roughness was 0.3 nm.

  A line-and-space mask 85 made of silicon carbide was formed on the nitride-based semiconductor layer 84 by using a photolithography technique and a vapor deposition technique. The film thickness was 150 nm. The periodic structure was such that the mask 85 part was 3 μm and the mask opening 84a was 15 μm wide.

  Thereafter, the nitride-based semiconductor regrowth layer 86 was regrown on the nitride-based semiconductor layer 84 by the MOVPE method. The V / III ratio during growth was 60. As a result, the mask 85 formed in the nitride-based semiconductor layer 84 was filled, and a nitride-based semiconductor regrowth layer 86 having a flat surface was obtained. When this surface was measured by AFM, the surface roughness of the root mean square was 0.3 nm.

  In order to evaluate the surface flatness and threading dislocation density due to changes in the shape of the line-and-space mask 85, the following experiments were conducted.

  First, a structure similar to the above was grown on each R-plane sapphire substrate 81 by the MOVPE method. Next, the line and space mask 85 is adjusted to change the dimensions of the mask portion 85 and the mask opening 84a, and the etching conditions are adjusted to change the depth of the periodic step groove structure in various ways. A nitride-based semiconductor layer 84 having a groove structure was produced. Furthermore, the nitride-based semiconductor regrowth layer 86 was regrown by the MOVPE method, the surface flatness was evaluated using AFM, and the threading dislocation density was evaluated by planar TEM observation.

The results are shown in Table 3.

  When the conditions 61 to 75 (Examples 45 to 55 and Comparative Examples 17 to 22) in which the width of the mask part 85 is changed are compared, the conditions 73 to 75 (Comparative Examples 18 to 20) where the width of the mask part 85 is larger than 30 μm. In this case, the RMS surface roughness is rough on the order of nm, and the threading dislocation density is 109 / cm 2, which is not suitable because the crystallinity is not good. Therefore, the width of the mask portion 85 is preferably 30 μm or less. On the other hand, a pattern having a mask portion 85 width of 0.4 μm as in Condition 61 (Comparative Example 17) was attempted to be produced by photolithography, but it was too precise and difficult to produce. Therefore, as in the conditions 62 to 72 (Examples 45 to 55), the width of the mask portion 85 is preferably 0.5 μm or more and 30 μm or less.

  Further, when the conditions 76 to 82 (Examples 56 to 60 and Comparative Examples 21 and 22) in which the width of the mask opening 84a is changed are compared, the condition 82 (Comparative Example 22) where the width of the mask opening 84a is larger than 5 μm. In this case, the RMS surface roughness is rough on the order of nm, and the threading dislocation density is 109 / cm 2 or more, which is not suitable because the crystallinity is not good. Therefore, the width of the mask opening 84a is preferably 5 μm or less. On the other hand, a pattern having a mask opening 84a width of 0.4 μm as in Condition 76 (Comparative Example 21) was attempted to be produced by photolithography, but it was too precise and difficult to produce. Accordingly, as in the conditions 77 to 81 (Examples 56 to 60), the width of the mask opening 84a is preferably 0.5 μm or more.

  Further, when the conditions 83 to 90 (Examples 61 to 66 and Comparative Examples 23 and 24) in which the height of the mask 85 is changed are compared, a mask of less than 0.05 μm is obtained as in the condition 83 (Comparative Example 23). The height is not suitable because it peels off during pattern formation. Therefore, a height of 0.05 μm or more is good. As in the conditions 84 to 90 (Examples 61 to 66 and Comparative Example 24), if the height of the mask 85 is increased, the growth time of the nitride-based semiconductor layer 85 necessary for embedding the mask 85 needs to be increased. occured. Since this leads to an increase in manufacturing cost, the condition 90 (Comparative Example 24) in which embedding is not completed within 120 minutes is not preferable. Therefore, as in the conditions 84 to 89 (Examples 61 to 66), the groove depth is preferably 0.3 μm or more and 3 μm or less. The threading dislocation density was almost the same when the embedding was completed.

It is sectional drawing explaining the epitaxial substrate of this invention. It is sectional drawing explaining the manufacturing method of the epitaxial substrate of this invention. It is sectional drawing explaining the manufacturing method of the epitaxial substrate of this invention. It is sectional drawing explaining the R surface sapphire substrate of this invention. It is sectional drawing explaining the epitaxial substrate of this invention. It is sectional drawing explaining the manufacturing method of the epitaxial substrate of this invention. It is sectional drawing explaining the manufacturing method of the epitaxial substrate of this invention. It is sectional drawing explaining the epitaxial substrate of this invention. It is a microphotoluminescence mapping image figure which shows the effect of this invention. It is a schematic diagram explaining the heterojunction of the nitride-based semiconductor aligned in C axis. It is sectional drawing which shows the conventional semiconductor device. It is sectional drawing which shows the conventional crystal growth method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Epitaxial substrate 4 R surface sapphire substrate 5 Epitaxial substrate 8 Epitaxial substrate 11a Mask opening part 11b Terrace part 11c Groove part 12 Mask 13 1st foundation layer 14 2nd foundation layer 15 Nitride system semiconductor layer 51 R surface sapphire substrate 52 1st First base layer 53 Second base layer 54 Nitride-based semiconductor layer 54a Mask opening 54b Terrace portion 54c Groove 55 Mask 56 Nitride-based semiconductor regrowth layer 81 R-plane sapphire substrate 82 First base layer 83 Second Underlayer 84 Nitride-based semiconductor layer 84a Mask opening 85 Mask 86 Nitride-based semiconductor regrowth layer 101 First layer 101a Heterojunction interface 102 Second layer 103 C-axis 111 R-plane sapphire substrate 112 n-type GaN layer 113 n-type Al0.1Ga0.9N cladding layer 114 GaN / In0.15Ga0.85N Quartz well structure active layer 115 p-type Al0.1Ga0.9N cladding layer 116 p-type GaN layer 117 p-side electrode 118 n-side electrode 121 GaN layer 122 mask 123 regrown GaN layer

Claims (9)

On the main surface of the sapphire substrate having the R surface, the groove portions and the convex terrace portions are alternately provided, the width of the groove portions is 0.5 to 30 μm, and the depth is 0.3 to 3 μm. And the width | variety of a terrace part is 0.5-5 micrometers, The R surface sapphire substrate characterized by the above-mentioned. An epitaxial substrate comprising a nitride-based semiconductor layer having an A-plane as a main surface on the main surface of the R-plane sapphire substrate according to claim 1. The epitaxial substrate according to claim 2, wherein the groove is filled with the nitride-based semiconductor layer. The epitaxial substrate according to claim 2, wherein the nitride-based semiconductor layer has a semiconductor element structure. A semiconductor device using the epitaxial substrate according to claim 1. 5. The method for manufacturing an epitaxial substrate according to claim 2, wherein the nitride-based semiconductor layer is selectively grown in the lateral direction on the sapphire substrate. Placing a mask on the R-plane sapphire substrate that does not generate nitride-based semiconductor crystal nuclei;
The epitaxial substrate manufacturing method according to claim 6, further comprising a step of selectively growing the nitride-based semiconductor layer in a lateral direction. The width between the masks is 0.5 to 30 µm, the width of the mask is 0.5 to 5 µm, and the height is 0.05 to 3 µm. Epitaxial substrate manufacturing method. The ratio of the supply amount of the group V raw material to the supply amount of the group III raw material when growing the nitride-based semiconductor layer is set to 0.01 to 100, according to any one of claims 6 to 8. Epitaxial substrate manufacturing method.

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