WO2012137540A1 - 液晶表示装置 - Google Patents
液晶表示装置 Download PDFInfo
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- WO2012137540A1 WO2012137540A1 PCT/JP2012/053544 JP2012053544W WO2012137540A1 WO 2012137540 A1 WO2012137540 A1 WO 2012137540A1 JP 2012053544 W JP2012053544 W JP 2012053544W WO 2012137540 A1 WO2012137540 A1 WO 2012137540A1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
- G02F1/133753—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers with different alignment orientations or pretilt angles on a same surface, e.g. for grey scale or improved viewing angle
- G02F1/133757—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers with different alignment orientations or pretilt angles on a same surface, e.g. for grey scale or improved viewing angle with different alignment orientations
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
Definitions
- Embodiments of the present invention relate to a liquid crystal display device.
- an active matrix liquid crystal display device in which a switching element is incorporated in each pixel has a structure using a lateral electric field (including a fringe electric field) such as an IPS (In-Plane Switching) mode or an FFS (Fringe Field Switching) mode. Attention has been paid.
- a horizontal electric field mode liquid crystal display device includes a pixel electrode and a counter electrode formed on an array substrate, and switches liquid crystal molecules with a horizontal electric field substantially parallel to the main surface of the array substrate.
- JP 2009-192822 A Japanese Patent Laid-Open No. 9-160041 US6,657,693B1
- An object of the present embodiment is to provide a liquid crystal display device with good display quality.
- a first auxiliary capacitance line and a second auxiliary capacitance line extending along the first direction, respectively, and extending between the first direction and positioned between the first auxiliary capacitance line and the second auxiliary capacitance line.
- a strip-shaped main pixel electrode extending along a direction, a strip-shaped first subpixel electrode connected to the main pixel electrode and facing the first auxiliary capacitance line and extending along a first direction; and the main pixel A strip-shaped second subpixel electrode connected to the electrode and spaced from the first subpixel electrode and extending in the first direction, and the main pixel electrode and the first subpixel electrode formed of a material having horizontal orientation And a first alignment film that covers the second subpixel electrode.
- a liquid crystal display device comprising: a second substrate; and a liquid crystal layer including liquid crystal molecules held between the first substrate and the second substrate.
- a first auxiliary capacitance line and a second auxiliary capacitance line extending along the first direction, respectively, and extending between the first direction and positioned between the first auxiliary capacitance line and the second auxiliary capacitance line.
- a strip-shaped main pixel electrode extending along a direction, a strip-shaped first subpixel electrode connected to the main pixel electrode and facing the first auxiliary capacitance line and extending along a first direction; and the main pixel A strip-shaped second subpixel electrode connected to the electrode and spaced apart from the first subpixel electrode and extending in the first direction, and opposed to the first source line and the second source line, respectively, along the second direction
- the first main common electrode extended and a material exhibiting horizontal orientation
- a first substrate comprising: the main pixel electrode; the first subpixel electrode; the second subpixel electrode; and a first alignment film covering the first main common electrode; and the first subpixel electrode;
- a second sub-common electrode extending along the first direction with the second sub-pixel electrode; and a second alignment film formed of a material exhibiting horizontal alignment and covering the second sub-common electrode.
- a liquid crystal display device comprising: a second substrate provided; and a liquid crystal layer including liquid crystal molecules held between the first substrate and the second substrate.
- a first auxiliary capacitance line and a second auxiliary capacitance line extending along the first direction, respectively, and extending between the first direction and positioned between the first auxiliary capacitance line and the second auxiliary capacitance line.
- a strip-shaped main pixel electrode extending along a direction, a strip-shaped first subpixel electrode connected to the main pixel electrode and facing the first auxiliary capacitance line and extending along a first direction; and the main pixel A strip-shaped second subpixel electrode connected to the electrode and extending from the first subpixel electrode and extending along the first direction; and a first subcommon electrode extending along the first direction facing the gate wiring And the main pixel electrode and the first subpixel electrode formed of a material exhibiting horizontal orientation.
- a first substrate including a first alignment film covering the second subpixel electrode and the first subcommon electrode, and extending along a second direction on both sides of the main pixel electrode.
- a second substrate comprising: a second main common electrode having the same potential as that of the first sub-common electrode; and a second alignment film formed of a material exhibiting horizontal alignment and covering the second main common electrode;
- a liquid crystal display device comprising a liquid crystal layer including liquid crystal molecules held between one substrate and the second substrate.
- FIG. 1 is a diagram schematically showing a configuration of a liquid crystal display device according to the present embodiment.
- FIG. 2 is a diagram schematically showing a configuration and an equivalent circuit of the liquid crystal display panel shown in FIG.
- FIG. 3 is a plan view schematically showing a minimum unit structure in one pixel in the basic configuration of the present embodiment.
- FIG. 4 is a cross-sectional view schematically showing a cross section of a liquid crystal display panel including switching elements.
- FIG. 5 is a plan view schematically showing the structure of one pixel on the counter substrate of the liquid crystal display panel in the first configuration example of the present embodiment.
- FIG. 1 is a diagram schematically showing a configuration of a liquid crystal display device according to the present embodiment.
- FIG. 2 is a diagram schematically showing a configuration and an equivalent circuit of the liquid crystal display panel shown in FIG.
- FIG. 3 is a plan view schematically showing a minimum unit structure in one pixel in the basic configuration of the present embodiment.
- FIG. 4 is a cross-
- FIG. 6 is a plan view schematically showing the structure of the array substrate when one pixel of the liquid crystal display panel in the first configuration example of the present embodiment is viewed from the counter substrate side.
- FIG. 7 is a plan view schematically showing the structure of one pixel on the counter substrate of the liquid crystal display panel in the second configuration example of the present embodiment.
- FIG. 8 is a plan view schematically showing the structure of the array substrate when one pixel of the liquid crystal display panel in the second configuration example of the present embodiment is viewed from the counter substrate side.
- FIG. 9 is a plan view schematically showing the structure of one pixel on the counter substrate of the liquid crystal display panel in the third configuration example of the present embodiment.
- FIG. 10 is a plan view schematically showing the structure of the array substrate when one pixel of the liquid crystal display panel in the third configuration example of the present embodiment is viewed from the counter substrate side.
- FIG. 11 is a plan view schematically showing the structure of the array substrate when one pixel of the liquid crystal display panel in the fourth configuration example of the present embodiment is viewed from the counter substrate side.
- FIG. 12 is a diagram summarizing the combinations of the array substrate described in the first to fourth configuration examples and the counter substrate described in the first to third configuration examples.
- FIG. 13 is a plan view schematically showing one variation of the present embodiment.
- FIG. 14 is a plan view schematically showing another variation of the present embodiment.
- FIG. 15 is a diagram for explaining the positional relationship between the pixel electrode, the gate wiring, and the auxiliary capacitance line, which can be applied in the present embodiment.
- FIG. 1 is a diagram schematically showing a configuration of a liquid crystal display device 1 in the present embodiment.
- the liquid crystal display device 1 includes an active matrix type liquid crystal display panel LPN, a drive IC chip 2 and a flexible wiring board 3 connected to the liquid crystal display panel LPN, a backlight 4 that illuminates the liquid crystal display panel LPN, and the like. .
- the liquid crystal display panel LPN is held between the array substrate AR, which is the first substrate, the counter substrate CT, which is the second substrate disposed to face the array substrate AR, and the array substrate AR and the counter substrate CT. And a liquid crystal layer (not shown).
- Such a liquid crystal display panel LPN includes an active area ACT for displaying an image.
- This active area ACT is composed of a plurality of pixels PX arranged in an m ⁇ n matrix (where m and n are positive integers).
- the backlight 4 is disposed on the back side of the array substrate AR in the illustrated example.
- various forms are applicable, and any of those using a light emitting diode (LED) as a light source or a cold cathode tube (CCFL) is applicable. Description of the detailed structure is omitted.
- LED light emitting diode
- CCFL cold cathode tube
- FIG. 2 is a diagram schematically showing a configuration and an equivalent circuit of the liquid crystal display panel LPN shown in FIG.
- the liquid crystal display panel LPN includes n gate lines G (G1 to Gn), n auxiliary capacitance lines C (C1 to Cn), m source lines S (S1 to Sm), and the like in the active area ACT. ing.
- the gate line G and the auxiliary capacitance line C extend substantially linearly along the first direction X.
- the gate lines G and the auxiliary capacitance lines C are adjacent to each other at intervals along the second direction Y intersecting the first direction X, and are alternately arranged in parallel.
- the first direction X and the second direction Y are orthogonal to each other.
- the source line S intersects with the gate line G and the auxiliary capacitance line C.
- the source line S extends substantially linearly along the second direction Y. Note that the gate wiring G, the auxiliary capacitance line C, and the source wiring S do not necessarily extend linearly, and some of them may be bent.
- Each gate line G is drawn outside the active area ACT and connected to the gate driver GD.
- Each source line S is drawn outside the active area ACT and connected to the source driver SD.
- At least a part of the gate driver GD and the source driver SD is formed on, for example, the array substrate AR, and is connected to the driving IC chip 2 with a built-in controller.
- Each pixel PX includes a switching element SW, a pixel electrode PE, a common electrode CE, and the like.
- the storage capacitor Cs is formed, for example, between the storage capacitor line C and the pixel electrode PE.
- the auxiliary capacitance line C is electrically connected to a voltage application unit VCS to which an auxiliary capacitance voltage is applied.
- the liquid crystal display panel LPN has a configuration in which the pixel electrode PE is formed on the array substrate AR while at least a part of the common electrode CE is formed on the counter substrate CT.
- the liquid crystal molecules in the liquid crystal layer LQ are switched mainly using an electric field formed between the PE and the common electrode CE.
- the electric field formed between the pixel electrode PE and the common electrode CE is the XY plane defined by the first direction X and the second direction Y, the substrate main surface of the array substrate AR, or the substrate main surface of the counter substrate CT. This is an oblique electric field slightly inclined with respect to the surface (or a transverse electric field substantially parallel to the main surface of the substrate).
- the switching element SW is composed of, for example, an n-channel thin film transistor (TFT).
- TFT thin film transistor
- the switching element SW is electrically connected to the gate line G and the source line S.
- ACT In the active area ACT, m ⁇ n switching elements SW are formed.
- the pixel electrode PE is disposed in each pixel PX and is electrically connected to the switching element SW. In the active area ACT, m ⁇ n pixel electrodes PE are formed.
- the common electrode CE is, for example, a common potential, and is disposed in common to the pixel electrodes PE of the plurality of pixels PX via the liquid crystal layer LQ.
- the array substrate AR includes a power supply unit VS for applying a voltage to the common electrode CE.
- the power supply unit VS is formed outside the active area ACT.
- the common electrodes CE at least a part of the common electrode CE formed on the counter substrate CT is drawn to the outside of the active area ACT, and the power supply unit VS formed on the array substrate AR via a conductive member (not shown) Electrically connected.
- a part of the common electrode CE is formed on the array substrate AR
- a part of the common electrode CE formed on the array substrate AR is electrically connected to the power supply unit VS, for example, outside the active area ACT. ing.
- FIG. 3 is a plan view schematically showing a minimum unit structure in one pixel PX.
- the pixel electrode PE has a main pixel electrode PA, a first subpixel electrode PB, and a second subpixel electrode PC.
- the main pixel electrode PA, the first subpixel electrode PB, and the second subpixel electrode PC are electrically connected to each other.
- the main pixel electrode PA, the first subpixel electrode PB, and the second subpixel electrode PC are all provided on the array substrate AR.
- the main pixel electrode PA extends along the second direction Y.
- the first subpixel electrode PB and the second subpixel electrode PC extend along a first direction X different from the second direction Y.
- the second subpixel electrode PC is separated from the first subpixel electrode PB.
- the pixel electrode PE is formed in a substantially I shape. More specifically, the main pixel electrode PA is formed in a strip shape extending linearly along the second direction Y at a substantially pixel central portion.
- the first subpixel electrode PB and the second subpixel electrode PC are each formed in a strip shape linearly extending along the first direction X at the upper end portion and the lower end portion of the pixel PX, respectively.
- first subpixel electrode PB and the second subpixel electrode PC may be disposed between pixels adjacent to the pixel PX in the vertical direction. That is, the first subpixel electrode PB may be disposed across the boundary between the pixel PX shown in the drawing and a pixel (not shown) below the pixel PX, and the second subpixel electrode PC is shown as the pixel PX shown in the drawing.
- the first sub-pixel electrode PB which may be disposed across the boundary between the pixel and the upper pixel (not shown), is coupled to, for example, one end of the main pixel electrode PA and extends from the main pixel electrode PA to both sides thereof. Is extended.
- the second subpixel electrode PC is coupled to, for example, the other end of the main pixel electrode PA, and extends from the main pixel electrode PA toward both sides thereof.
- the first subpixel electrode PB and the second subpixel electrode PC are substantially orthogonal to the main pixel electrode PA.
- the first subpixel electrode PB may be coupled slightly closer to the other end than the one end of the main pixel electrode PA.
- the second subpixel electrode PC is connected to the other end of the main pixel electrode PA. It may be coupled slightly closer to one end than the portion.
- the pixel electrode PE is electrically connected to a switching element (not shown) in the second subpixel electrode PC, for example.
- the common electrode CE has a main common electrode CA and a sub-common electrode CB.
- the main common electrode CA and the sub-common electrode CB are electrically connected to each other.
- Such a common electrode CE is electrically insulated from the pixel electrode PE.
- in the common electrode CE at least a part of the main common electrode CA and the sub-common electrode CB is provided on the counter substrate CT.
- the main common electrode CA extends along the second direction Y.
- the main common electrode CA is disposed on both sides of the main pixel electrode PA.
- none of the main common electrodes CA overlaps with the main pixel electrode PA in the XY plane, and a substantially equal interval is formed between each of the main common electrodes CA and the main pixel electrode PA. Yes. That is, the main pixel electrode PA is located approximately in the middle of the adjacent main common electrode CA.
- the sub-common electrode CB extends along the first direction X.
- the sub-common electrode CB is disposed between the first sub-pixel electrode PB and the second sub-pixel electrode PC.
- none of the sub-common electrodes CB overlaps the first sub-pixel electrode PB and the second sub-pixel electrode PC, and the first sub-pixel electrode PB and the second sub-pixel electrode PC do not overlap.
- a substantially equal interval is formed between each and the sub-common electrode CB. That is, the sub-common electrode CB is located approximately in the middle between the first sub-pixel electrode PB and the second sub-pixel electrode PC.
- the main common electrode CA is formed in a strip shape extending linearly along the second direction Y.
- the sub-common electrode CB is formed in a strip shape extending linearly along the first direction X. Note that the two main common electrodes CA are arranged in parallel at intervals along the first direction X.
- the main common electrode on the left side in the drawing is referred to as CAL.
- the right main common electrode is called CAR.
- the main common electrode CAL and the main common electrode CAR are at the same potential as the sub-common electrode CB.
- the main common electrode CAL and the main common electrode CAR are connected to the sub-common electrode CB, respectively.
- the main common electrode CAL and the main common electrode CAR are respectively disposed between the pixel PX and the adjacent pixels on the left and right. That is, the main common electrode CAL is disposed across the boundary between the illustrated pixel PX and the left pixel (not shown), and the main common electrode CAR is the illustrated pixel PX and the right pixel (not shown). ).
- the sub-common electrode CB crosses substantially the center of the pixel PX.
- One main pixel electrode PA is located between the adjacent main common electrode CAL and main common electrode CAR. For this reason, the main common electrode CAL, the main pixel electrode PA, and the main common electrode CAR are arranged in this order along the first direction X. That is, the main pixel electrode PA and the main common electrode CA are alternately arranged along the first direction X.
- the main pixel electrode PA, the main common electrode CAL, and the main common electrode CAR are disposed substantially parallel to each other.
- the distance along the first direction X between the main common electrode CAL and the main pixel electrode PA is substantially the same as the distance along the first direction X between the main common electrode CAR and the main pixel electrode PA.
- One sub-common electrode CB is located between the adjacent first sub-pixel electrode PB and second sub-pixel electrode PC.
- the first subpixel electrode PB, the subcommon electrode CB, and the second subpixel electrode PC are arranged in this order along the second direction Y. That is, the first subpixel electrode PB, the second subpixel electrode PC, and the subcommon electrode CB are alternately arranged along the second direction Y.
- the first sub-pixel electrode PB, the sub-common electrode CB, and the second sub-pixel electrode PC are disposed substantially parallel to each other.
- the distance along the second direction Y between the first subpixel electrode PB and the subcommon electrode CB is substantially the same as the distance along the second direction Y between the second subpixel electrode PC and the subcommon electrode CB. is there.
- four regions defined by the pixel electrode PE and the common electrode CE are mainly formed as openings or transmission portions that contribute to display.
- the initial alignment direction of the liquid crystal molecules LM is, for example, a direction substantially parallel to the second direction Y.
- At least one of the main common electrodes CA may be opposed to the source wiring S that extends substantially parallel to the main common electrode CA (or along the second direction Y).
- any one of the first subpixel electrode PB, the second subpixel electrode PC, and the subcommon electrode CB is substantially parallel to these (or along the first direction X). Or the storage capacitor line C.
- the main common electrode CA includes at least one of the first main common electrode CA1 provided on the array substrate AR and the second main common electrode CA2 provided on the counter substrate CT. Also good.
- the sub-common electrode CB may include at least one of the first sub-common electrode CB1 provided on the array substrate AR and the second sub-common electrode CB2 provided on the counter substrate CT.
- the first main common electrode CA1, the second main common electrode CA2, the first sub-common electrode CB1, and the second sub-common electrode CB2 are all at the same potential.
- FIG. 4 is a cross-sectional view schematically showing a cross section of the liquid crystal display panel LPN including the switching element SW.
- the illustration of the common electrode is omitted, and only the portions necessary for the description are shown.
- a backlight 4 is disposed on the back side of the array substrate AR constituting the liquid crystal display panel LPN.
- the array substrate AR is formed using a first insulating substrate 10 having optical transparency such as a glass substrate or a plastic substrate.
- the array substrate AR includes a switching element SW, a pixel electrode PE, a first alignment film AL1, and the like on the side of the first insulating substrate 10 facing the counter substrate CT.
- the switching element SW is a top-gate thin film transistor, but may be a bottom-gate thin film transistor.
- the semiconductor layer SC of the switching element SW is formed of, for example, polysilicon, but may be formed of amorphous silicon.
- the semiconductor layer SC has a source region SCS and a drain region SCD on both sides of the channel region SCC.
- An undercoat layer that is an insulating film may be interposed between the first insulating substrate 10 and the semiconductor layer SC.
- the semiconductor layer SC is covered with the gate insulating film 11.
- the gate insulating film 11 is also disposed on the first insulating substrate 10.
- the gate electrode WG of the switching element SW is formed on the gate insulating film 11 and is located above the channel region SCC of the semiconductor layer SC. Further, the gate wiring G and the auxiliary capacitance line C are also formed on the gate insulating film 11. The gate electrode WG, the gate line G, and the auxiliary capacitance line C can be formed in the same process using the same material. The gate electrode WG is electrically connected to the gate wiring G.
- the gate electrode WG, the gate wiring G, and the auxiliary capacitance line C are covered with the first interlayer insulating film 12.
- the first interlayer insulating film 12 is also disposed on the gate insulating film 11.
- the gate insulating film 11 and the first interlayer insulating film 12 are formed of an inorganic material such as silicon oxide and silicon nitride, for example.
- the source electrode WS and the drain electrode WD of the switching element SW are formed on the first interlayer insulating film 12.
- the source line S is also formed on the first interlayer insulating film 12.
- the source electrode WS, the drain electrode WD, and the source wiring S can be formed in the same process using the same material.
- the source electrode WS is electrically connected to the source line S.
- the source electrode WS is in contact with the source region SCS of the semiconductor layer SC through a contact hole that penetrates the gate insulating film 11 and the first interlayer insulating film 12.
- the drain electrode WD is in contact with the drain region SCD of the semiconductor layer SC through a contact hole that penetrates the gate insulating film 11 and the first interlayer insulating film 12.
- the gate electrode WG, the gate wiring G, the auxiliary capacitance line C, the source electrode WS, the drain electrode WD, and the source wiring S are formed of a conductive material such as molybdenum, aluminum, tungsten, or titanium.
- the switching element SW having such a configuration is covered with the second interlayer insulating film 13. That is, the source electrode WS, the drain electrode WD, and the source wiring S are covered with the second interlayer insulating film 13.
- the second interlayer insulating film 13 is also disposed on the first interlayer insulating film 12.
- the second interlayer insulating film 13 is formed of various organic materials such as an ultraviolet curable resin and a thermosetting resin.
- the pixel electrode PE is formed on the second interlayer insulating film 13. Although not described in detail, the main pixel electrode PA, the first subpixel electrode PB, and the second subpixel electrode PC constituting the pixel electrode PE are formed on the second interlayer insulating film 13.
- the pixel electrode PE is connected to the drain electrode WD through a contact hole that penetrates the second interlayer insulating film 13.
- the pixel electrode PE is formed of a light-transmitting conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but other metal materials such as aluminum. May be formed.
- the first alignment film AL1 is disposed on the surface of the array substrate AR that faces the counter substrate CT, and extends over substantially the entire active area ACT.
- the first alignment film AL1 covers the pixel electrode PE and is also disposed on the second interlayer insulating film 13.
- Such a first alignment film AL1 is formed of a material exhibiting horizontal alignment.
- the array substrate AR may further include a first main common electrode and a first sub-common electrode as part of the common electrode.
- the counter substrate CT is formed using a second insulating substrate 20 having optical transparency such as a glass substrate or a plastic substrate.
- This counter substrate CT is arranged on the side of the second insulating substrate 20 facing the array substrate AR, at least one of the second main common electrode and the second sub common electrode among the common electrodes not shown, and the second alignment film. AL2 etc. are provided.
- this counter substrate CT is arranged so as to partition each pixel PX (or to face wiring portions such as the source wiring S, the gate wiring G, the auxiliary capacitance line C, and the switching element SW).
- a black matrix, a color filter layer disposed corresponding to each pixel PX, an overcoat layer that alleviates the influence of unevenness on the surface of the black matrix and the color filter layer, and the like may be disposed.
- the common electrode is made of a light-transmitting conductive material such as ITO or IZO.
- the second alignment film AL2 is disposed on the surface of the counter substrate CT facing the array substrate AR, and extends over substantially the entire active area ACT.
- the second alignment film AL2 covers the common electrode and the like.
- Such a second alignment film AL2 is formed of a material exhibiting horizontal alignment.
- first alignment film AL1 and second alignment film AL2 are subjected to an alignment process (for example, a rubbing process or a photo-alignment process) for initial alignment of the liquid crystal molecules LM.
- the first alignment treatment direction PD1 in which the first alignment film AL1 initially aligns the liquid crystal molecules LM is parallel to the second alignment treatment direction PD2 in which the second alignment film AL2 initially aligns the liquid crystal molecules LM.
- the first alignment treatment direction PD1 and the second alignment treatment direction PD2 are substantially parallel to each other and are in the same direction.
- the first alignment treatment direction PD1 and the second alignment treatment direction PD2 are substantially parallel to each other and opposite to each other.
- the array substrate AR and the counter substrate CT as described above are arranged so that the first alignment film AL1 and the second alignment film AL2 face each other.
- a columnar spacer integrally formed on one substrate by a resin material is disposed between the first alignment film AL1 of the array substrate AR and the second alignment film AL2 of the counter substrate CT.
- a predetermined cell gap for example, a cell gap of 2 to 7 ⁇ m is formed.
- the array substrate AR and the counter substrate CT are bonded to each other with a sealing material outside the active area ACT in a state where a predetermined cell gap is formed.
- the liquid crystal layer LQ is held in a cell gap formed between the array substrate AR and the counter substrate CT, and is disposed between the first alignment film AL1 and the second alignment film AL2.
- the liquid crystal layer LQ includes liquid crystal molecules LM.
- Such a liquid crystal layer LQ is made of, for example, a liquid crystal material having a positive dielectric anisotropy (positive type).
- the first optical element OD1 is attached to the outer surface of the array substrate AR, that is, the outer surface of the first insulating substrate 10 constituting the array substrate AR with an adhesive or the like.
- the first optical element OD1 is located on the side facing the backlight 4 of the liquid crystal display panel LPN, and controls the polarization state of incident light incident on the liquid crystal display panel LPN from the backlight 4.
- the first optical element OD1 includes a first polarizing plate PL1 having a first polarization axis AX1. Note that another optical element such as a retardation plate may be disposed between the first polarizing plate PL1 and the first insulating substrate 10.
- the second optical element OD2 is adhered to the outer surface of the counter substrate CT, that is, the outer surface of the second insulating substrate 20 constituting the counter substrate CT with an adhesive or the like.
- the second optical element OD2 is located on the display surface side of the liquid crystal display panel LPN, and controls the polarization state of the outgoing light emitted from the liquid crystal display panel LPN.
- the second optical element OD2 includes a second polarizing plate PL2 having a second polarization axis AX2. Note that another optical element such as a retardation plate may be disposed between the second polarizing plate PL2 and the second insulating substrate 20.
- the first polarizing axis AX1 of the first polarizing plate PL1 and the second polarizing axis AX2 of the second polarizing plate PL2 are in a crossed Nicols positional relationship.
- one polarizing plate is arranged so that the polarization axis thereof is parallel or orthogonal to the initial alignment direction of the liquid crystal molecules LM, that is, the first alignment processing direction PD1 or the second alignment processing direction PD2.
- the initial alignment direction is parallel to the second direction Y
- the polarization axis of one polarizing plate is parallel to the second direction Y or parallel to the first direction X.
- the first polarizing plate PL1 is arranged so that the first polarization axis AX1 is orthogonal to the second direction Y, which is the initial alignment direction of the liquid crystal molecules LM, Further, the second polarizing plate PL2 is arranged so that the second polarization axis AX2 is parallel to the initial alignment direction of the liquid crystal molecules LM.
- the second polarizing plate PL2 is arranged so that the second polarization axis AX2 is orthogonal to the second direction Y that is the initial alignment direction of the liquid crystal molecules LM.
- the first polarizing plate PL1 is arranged so that the first polarization axis AX1 is parallel to the initial alignment direction of the liquid crystal molecules LM.
- the liquid crystal molecules LM of the liquid crystal layer LQ are aligned such that the major axis thereof faces the first alignment treatment direction PD1 of the first alignment film AL1 and the second alignment treatment direction PD2 of the second alignment film AL2.
- Such OFF time corresponds to the initial alignment state
- the alignment direction of the liquid crystal molecules LM at the OFF time corresponds to the initial alignment direction.
- the liquid crystal molecules LM are not always aligned parallel to the XY plane, and are often pretilted. Therefore, the strict initial alignment direction of the liquid crystal molecules LM is a direction obtained by orthogonally projecting the alignment direction of the liquid crystal molecules LM at the OFF time on the XY plane. However, in order to simplify the description, in the following description, it is assumed that the liquid crystal molecules LM are aligned in parallel to the XY plane and rotate in a plane parallel to the XY plane.
- both the first alignment treatment direction PD1 and the second alignment treatment direction PD2 are substantially parallel to the second direction Y.
- the liquid crystal molecules LM are initially aligned so that their major axes are oriented in a direction substantially parallel to the second direction Y, as indicated by a broken line in FIG. That is, the initial alignment direction of the liquid crystal molecules LM is parallel to the second direction Y (or 0 ° with respect to the second direction Y).
- the liquid crystal molecules LM are substantially near the middle portion of the liquid crystal layer LQ. Alignment is performed horizontally (pretilt angle is substantially zero), and is aligned with a pretilt angle that is symmetrical in the vicinity of the first alignment film AL1 and in the vicinity of the second alignment film AL2 (spray alignment).
- the liquid crystal molecules LM in the vicinity of the first alignment film AL1 and the liquid crystal molecules LM in the vicinity of the second alignment film AL2 in the direction inclined from the normal direction of the substrate Is optically compensated. Therefore, when the first alignment processing direction PD1 and the second alignment processing direction PD2 are parallel to each other and in the same direction, light leakage is small in the case of black display, and a high contrast ratio can be realized. It becomes possible to improve the quality.
- the liquid crystal molecules LM are in the vicinity of the first alignment film AL1, in the second alignment film AL2 in the cross section of the liquid crystal layer LQ. And in the middle part of the liquid crystal layer LQ with a substantially uniform pretilt angle (homogeneous alignment).
- Part of the backlight light from the backlight 4 passes through the first polarizing plate PL1 and enters the liquid crystal display panel LPN.
- the light incident on the liquid crystal display panel LPN is linearly polarized light orthogonal to the first polarization axis AX1 of the first polarizing plate PL1.
- Such a polarization state of linearly polarized light hardly changes when it passes through the liquid crystal display panel LPN in the OFF state. Therefore, the linearly polarized light transmitted through the liquid crystal display panel LPN is absorbed by the second polarizing plate PL2 having a crossed Nicol positional relationship with the first polarizing plate PL1 (black display).
- the substrate is interposed between the pixel electrode PE and the common electrode CE.
- a horizontal electric field (or an oblique electric field) substantially parallel to the line is formed.
- the liquid crystal molecules LM are affected by the electric field and rotate in a plane whose major axis is substantially parallel to the XY plane as indicated by the solid line in the figure.
- the liquid crystal molecules LM in the upper half region of the region between the pixel electrode PE and the main common electrode CAL rotate clockwise with respect to the second direction Y in the drawing.
- the liquid crystal molecules LM in the lower half region are aligned so as to face the lower left, and are rotated counterclockwise with respect to the second direction Y so as to face the upper left in the drawing.
- the liquid crystal molecules LM in the upper half region rotate counterclockwise with respect to the second direction Y and are oriented so as to face the lower right in the figure.
- the liquid crystal molecules LM in the lower half region rotate clockwise with respect to the second direction Y and are aligned so as to face the upper right in the drawing.
- each pixel PX in a state where an electric field is formed between the pixel electrode PE and the common electrode CE, the alignment direction of the liquid crystal molecules LM is divided into a plurality of directions with the position overlapping the pixel electrode PE as a boundary. , A domain is formed in each orientation direction. That is, a plurality of domains are formed in one pixel PX.
- linearly polarized light orthogonal to the first polarization axis AX1 of the first polarizing plate PL1 is incident on the liquid crystal display panel LPN, and the polarization state is the alignment of the liquid crystal molecules LM when passing through the liquid crystal layer LQ. It changes according to the state.
- the second polarizing plate PL2 (white display).
- the viewing angles in the four directions can be optically compensated, and a wide viewing angle can be achieved. Become. Therefore, it is possible to provide a liquid crystal display device with high display quality, which can realize display with high transmittance without gradation inversion.
- the transmittance of each region becomes substantially equal, The light transmitted through the part optically compensates for each other, and a uniform display can be realized over a wide viewing angle range.
- the present embodiment has a wide viewing angle and bright brightness even in a halftone, as compared with a vertical alignment type liquid crystal display device in which the initial alignment state of liquid crystal molecules is perpendicular to the substrate.
- the pixel electrode PE and the common electrode CE are not necessarily formed of a transparent conductive material, and may be formed using a conductive material such as aluminum or silver.
- the minimum unit structure in one pixel PX described above is not limited to a square, and is not limited to expansion and contraction in the second direction Y or the first direction X, and may be a rectangle. That is, a desired pixel size can be designed by combining the unit structure itself or the unit structure. Even if the dimensions of the unit structure are freely designed in this way, the liquid crystal molecules LM are horizontally aligned on the substrate due to the electric field generated between the electrodes, so that the influence on the normal direction retardation with respect to the substrate is small. Therefore, the change in pixel size has little influence on the luminance and viewing angle.
- FIG. 5 is a plan view schematically showing the structure of one pixel PX in the counter substrate CT1 of the liquid crystal display panel LPN in the first configuration example of the present embodiment.
- the common electrode CE includes a second main common electrode CA2 provided on the counter substrate CT1 as a main common electrode, and a second sub common electrode CB2 provided on the counter substrate CT1 as a sub common electrode. Have. These second main common electrode CA2 and second sub-common electrode CB2 are covered with the second alignment film AL2.
- the illustrated counter substrate CT1 includes a strip-shaped second main common electrode CA2 that linearly extends along the second direction Y, and a strip-shaped second sub electrode that extends linearly along the first direction X. And a common electrode CB2.
- the second main common electrode CA2 and the second sub-common electrode CB2 are electrically connected.
- the second main common electrode CA2 and the second sub-common electrode CB2 are formed integrally (or continuously). That is, in the counter substrate CT1, the common electrode CE is formed in a lattice shape.
- the two second main common electrodes CA2 shown in the figure are arranged in parallel along the first direction X at intervals, and in the following, in order to distinguish them, the second main common electrode on the left side in the drawing is used. Is called CAL2, and the second main common electrode on the right side in the figure is called CAR2.
- the second main common electrode CAL2 and the second main common electrode CAR2 are connected to the second sub-common electrode CB2, respectively.
- the common electrode CE having such a configuration is drawn out of the active area, electrically connected to a power feeding unit formed on the array substrate via a conductive member, and a common potential is fed. .
- FIG. 6 is a plan view schematically showing the structure of the array substrate AR1 when one pixel PX of the liquid crystal display panel LPN in the first configuration example of the present embodiment is viewed from the counter substrate CT1 side.
- the common electrode CE is illustrated by a broken line. Further, only the configuration necessary for the description of one pixel PX is illustrated, and the illustration of the switching element and the like is omitted.
- the array substrate AR1 extends along the first direction X, the auxiliary capacitance line C1 and the auxiliary capacitance line C2, the gate wiring G1 extended along the first direction X, and the second direction Y.
- the auxiliary capacitance line C1, the auxiliary capacitance line C2, and the gate wiring G1 are formed on the gate insulating film 11 and covered with the first interlayer insulating film 12.
- the source wiring S 1 and the source wiring S 2 are formed on the first interlayer insulating film 12 and are covered with the second interlayer insulating film 13.
- the pixel electrode PE is formed on the second interlayer insulating film 13.
- the pixel PX corresponds to a region indicated by a broken line in the drawing, and has a rectangular shape whose length along the second direction Y is longer than the length along the first direction X.
- the source line S1 is disposed at the left end, and the source line S2 is disposed at the right end. Strictly speaking, the source line S1 is disposed across the boundary between the pixel PX and the pixel adjacent to the left side, and the source line S2 is disposed over the boundary between the pixel PX and the pixel adjacent to the right side. Yes.
- the storage capacitor line C1 is disposed at the upper end, the storage capacitor line C2 is disposed at the lower end, and the gate line G1 is disposed substantially at the center of the pixel. That is, the distance along the second direction Y between the gate line G1 and the auxiliary capacitance line C1 is substantially the same as the distance along the second direction Y between the gate line G1 and the auxiliary capacitance line C2.
- the storage capacitor line C1 may be disposed across the boundary between the pixel PX and the upper pixel.
- the storage capacitor line C2 may be disposed across the boundary between the pixel PX and the lower pixel.
- the pixel electrode PE is disposed between the source wiring S1 and the source wiring S2, and is electrically connected to a switching element (not shown).
- a pixel electrode PE includes a strip-shaped main pixel electrode PA extending linearly along the second direction Y, a strip-shaped first subpixel electrode PB extending linearly along the first direction X, and A second subpixel electrode PC is provided.
- the main pixel electrode PA, the first subpixel electrode PB, and the second subpixel electrode PC are electrically connected.
- the main pixel electrode PA, the first subpixel electrode PB, and the second subpixel electrode PC are formed integrally (or continuously). That is, in the array substrate AR1, the pixel electrode PE is formed in an I shape.
- the main pixel electrode PA, the first subpixel electrode PB, and the second subpixel electrode PC are all covered with the first alignment film AL1.
- the main pixel electrode PA is located inside the pixel PX from the position immediately above each of the adjacent source line S1 and source line S2, and is disposed approximately in the middle between the source line S1 and the source line S2. Such a main pixel electrode PA extends from the vicinity of the upper end of the pixel PX to the vicinity of the lower end.
- the first sub-pixel electrode PB is disposed at the lower end of the pixel PX and is connected to one end of the main pixel electrode PA.
- the first sub-pixel electrode PB is linear from the main pixel electrode PA toward both sides thereof, that is, the source line S1 on the left side of the main pixel electrode PA and the source line S2 on the right side of the main pixel electrode PA. It extends to.
- the second subpixel electrode PC is disposed at the upper end portion of the pixel PX and connected to the other end portion of the main pixel electrode PA. Such a second subpixel electrode PC extends linearly from the main pixel electrode PA toward both sides thereof, that is, toward the source line S1 and the source line S2. In the first configuration example, the second subpixel electrode PC is opposed to the storage capacitor line C1. In the illustrated example, the second subpixel electrode PC is disposed above the auxiliary capacitance line C1. A first interlayer insulating film 12 and a second interlayer insulating film 13 are interposed as insulating films between the second subpixel electrode PC and the auxiliary capacitance line C1.
- the lengths of the first subpixel electrode PB and the second subpixel electrode PC along the first direction X may be substantially the same or different. Regarding the length along the first direction X of the second subpixel electrode PC, when the second subpixel electrode PC covers the auxiliary capacitance line C1, the auxiliary located between the source line S1 and the source line S2. It is equal to or longer than the length along the first direction X of the capacitance line C1.
- the widths of the first subpixel electrode PB and the second subpixel electrode PC along the second direction Y may be substantially the same or different.
- the width of the second subpixel electrode PC is wider than the width of the first subpixel electrode PB when the second subpixel electrode PC is electrically connected to a switching element (not shown) on the auxiliary capacitance line C1. It may be.
- the width of the second subpixel electrode PC covers the auxiliary capacitance line C1
- the width of the second subpixel electrode PC is equal to or greater than the width of the auxiliary capacitance line C1.
- the second subpixel electrode PC is connected to the source line S1 and the source line S2. They can be arranged so as to cover the auxiliary capacitance line C1 located between them.
- the first subpixel electrode PB can be arranged so as to cover the auxiliary capacitance line C2 located between the source wiring S1 and the source wiring S2. It is.
- first subpixel electrode PB and the second subpixel electrode PC of two pixel electrodes adjacent in the second direction Y may be disposed on one auxiliary capacitance line.
- the first subpixel electrode of the pixel electrode disposed in the pixel above the pixel PX is disposed on the storage capacitor line C1 together with the second subpixel electrode PC of the pixel electrode PE of the pixel PX illustrated in the drawing. May be.
- the first subpixel electrode PB of the pixel electrode PE of the pixel PX is disposed on the auxiliary capacitance line C2.
- the gate line G1 may be disposed at the upper end or the lower end of the pixel PX, and the auxiliary capacitance line C1 may be disposed substantially at the center of the pixel.
- the first subpixel electrode PB or the second subpixel electrode PC may be opposed to the gate line G1 (or the first subpixel electrode PB or the second subpixel electrode PC is the gate line G1). It may be arranged above.
- the second main common electrode CAL2 and the second main common electrode CAR2 are disposed on both sides of the position immediately above the main pixel electrode PA, and the second sub-common electrode CB2 is the first sub-pixel.
- the electrode is disposed between a position immediately above the electrode PB and a position immediately above the second subpixel electrode PC.
- the main pixel electrode PA is disposed between the second main common electrode CAL2 and the second main common electrode CAR2, and the first subpixel electrode PB and the second subpixel electrode PC sandwich the second subcommon electrode CB2. It is arranged on both sides.
- the second main common electrode CAL2 is disposed at the left end of the pixel PX and faces the source line S1 (or the second main common electrode CAL2 is disposed above the source line S1. )
- the second main common electrode CAR2 is arranged at the right end of the pixel PX and faces the source line S2 (or the second main common electrode CAR2 is arranged above the source line S2).
- the second sub-common electrode CB2 is disposed substantially in the center of the pixel and faces the gate line G1 (or the second sub-common electrode CB2 is disposed above the gate line G1).
- the second main common electrode CAL2 and the second main common electrode CAR2 are opposed to the source line S1 and the source line S2, respectively.
- the second main common electrode CAL2 and the second main common electrode CAR2 are disposed above the source line S1 and the source line S2, respectively, the second main common electrode CAL2 and the second main common electrode CAR2 are the source.
- the opening contributing to display can be enlarged, and the transmittance of the pixel PX can be improved.
- the second main common electrode CAL2 and the second main common electrode CAR2 are disposed above the source line S1 and the source line S2, respectively, so that the main pixel electrode PA, the second main common electrode CAL2, and the second main common electrode CAR2 are disposed. It is possible to increase the distance between and a horizontal electric field closer to the horizontal. For this reason, it is possible to maintain the wide viewing angle, which is an advantage of the IPS mode, which is a conventional configuration.
- the first subpixel electrode PB or the second subpixel electrode PC of the pixel electrode PE is disposed so as to face the auxiliary capacitance line or the gate wiring, an undesired electric field from the auxiliary capacitance line or the gate wiring. Can be shielded. For this reason, it is possible to suppress an undesired bias from being applied to the liquid crystal layer LQ from the storage capacitor line or the gate wiring, and it is possible to suppress the occurrence of display defects such as burn-in. Therefore, a liquid crystal display device with better display quality can be provided.
- FIG. 7 is a plan view schematically showing the structure of one pixel PX in the counter substrate CT2 of the liquid crystal display panel LPN in the second configuration example of the present embodiment.
- the common electrode CE includes a first main common electrode CA1 provided on an array substrate to be described later as a main common electrode, and a second sub-common electrode CB2 provided on the counter substrate CT2 as a sub-common electrode. have.
- the second sub-common electrode CB2 is covered with the second alignment film AL2.
- the counter substrate CT2 shown in the figure includes a strip-shaped second sub-common electrode CB2 that extends linearly along the first direction X, and does not include a main common electrode. That is, in the counter substrate CT2, the common electrode CE is formed in a stripe shape extending in the first direction X.
- the second sub-common electrode CB2 of the common electrode CE is drawn out to the outside of the active area and is electrically connected to a power feeding unit formed on the array substrate through a conductive member. Potential is supplied.
- FIG. 8 is a plan view schematically showing the structure of the array substrate AR2 when one pixel PX of the liquid crystal display panel LPN in the second configuration example of the present embodiment is viewed from the counter substrate CT2.
- the common electrode CE is illustrated by a broken line. Further, only the configuration necessary for the description of one pixel PX is illustrated, and the illustration of the switching element and the like is omitted.
- the array substrate AR2 includes the auxiliary capacitance line C1 and the auxiliary capacitance line C2 extending along the first direction X, the gate wiring G1 extending along the first direction X, and the second A source line S1 and a source line S2 extending along the direction Y, and a pixel electrode PE are provided.
- the pixel electrode PE is covered with the first alignment film AL1.
- the array substrate AR2 includes a part of the common electrode CE, that is, a strip-shaped first main common electrode CA1 extending linearly along the second direction Y.
- the first main common electrode CA1 has the same potential as the second sub-common electrode CB2.
- the two first main common electrodes CA1 shown in the figure are arranged in parallel along the first direction X at intervals, and in the following, in order to distinguish them, the first main common electrode on the left side in the drawing is used. Is called CAL1, and the first main common electrode on the right side in the figure is called CAR1.
- These first main common electrode CAL1 and first main common electrode CAR1 are formed on the second interlayer insulating film 13 and covered with the first alignment film AL1, for example, like the pixel electrode PE.
- the first main common electrode CAL1 and the first main common electrode CAR1 can be formed in the same process using the same material (for example, ITO) as the pixel electrode PE.
- the first main common electrode CAL1 is disposed at the left end portion of the pixel PX and faces the source line S1 (or the first main common electrode CAL1 is disposed above the source line S1. )
- the first main common electrode CAR1 is arranged at the right end of the pixel PX and faces the source line S2 (or the first main common electrode CAR1 is arranged above the source line S2).
- a second interlayer insulating film 13 is interposed as an insulating film between the first main common electrode CAL1 and the first main common electrode CAR1, and the source wiring S1 and the source wiring S2.
- Each of the first main common electrode CAL1 and the first main common electrode CAR1 extends linearly within the active area, is drawn out of the active area, and is electrically connected to the power feeding unit formed on the array substrate AR2. Connected and supplied with common potential.
- the first main common electrode CAL1 and the first main common electrode CAR1 covers the source wiring S1 and the source wiring S2 in the active area, the first main common electrode CAL1 and the first main common electrode CAR1
- the width along the first direction X is equal to or greater than the width along the first direction X of the source wiring S1 and the source wiring S2.
- the pixel electrode PE is disposed between the source line S1 and the source line S2, that is, between the first main common electrode CAL1 and the first main common electrode CAR1, as in the first configuration example.
- the pixel electrode PE includes a main pixel electrode PA, a first subpixel electrode PB, and a second subpixel electrode PC.
- the main pixel electrode PA is disposed at a substantially middle position between the first main common electrode CAL1 and the first main common electrode CAR1.
- Each of the first subpixel electrode PB and the second subpixel electrode PC extends toward the first main common electrode CAL1 and the first main common electrode CAR1.
- the first subpixel electrode PB and the second subpixel electrode PC are arranged so as not to contact the first main common electrode CAL1 and the first main common electrode CAR1 (or each of the first subpixel electrode PB and the second subpixel electrode PC is the first main common electrode).
- the electrode CAL1 and the first main common electrode CAR1 are disposed apart from each other).
- the second subpixel electrode PC is opposed to the auxiliary capacitance line C1 (or the second subpixel electrode PC is disposed above the auxiliary capacitance line C1).
- the gate line G1 may be disposed at the upper end or the lower end of the pixel PX, and the auxiliary capacitance line C1 may be disposed substantially at the center of the pixel.
- the first subpixel electrode PB or the second subpixel electrode PC may be opposed to the gate line G1 (or the first subpixel electrode PB or the second subpixel electrode PC is the gate line G1). It may be arranged above.
- the second sub-common electrode CB2 is disposed between a position immediately above the first sub-pixel electrode PB and a position directly above the second sub-pixel electrode PC.
- the main pixel electrode PA is disposed between the first main common electrode CAL1 and the first main common electrode CAR1, and the first subpixel electrode PB and the second subpixel electrode PC sandwich the second subcommon electrode CB2. It is arranged on both sides.
- the second sub-common electrode CB2 is disposed substantially in the center of the pixel and faces the gate line G1 (or the second sub-common electrode CB2 is disposed above the gate line G1). .
- the first main common electrodes CA1 of the common electrode CE is disposed so as to face the source wiring, so that it is undesirable from the source wiring. It is possible to shield the electric field. For this reason, it is possible to suppress an undesired bias from being applied to the liquid crystal layer LQ from the source wiring, and crosstalk (for example, in a state where the pixel PX is set to a pixel potential for displaying black).
- the common electrode CE includes a first main common electrode CA1 provided on the array substrate AR2 and a second main common electrode CA2 provided on the counter substrate CT1 as main common electrodes.
- an undesired vertical electric field that is, an electric field along the normal direction of the substrate main surface
- FIG. 9 is a plan view schematically showing the structure of one pixel PX in the counter substrate CT3 of the liquid crystal display panel LPN in the third configuration example of the present embodiment.
- the common electrode CE includes a second main common electrode CA2 provided on the counter substrate CT3 as a main common electrode, and a first sub-common electrode CB1 provided on an array substrate described later as a sub-common electrode. have.
- the second main common electrode CA2 is covered with the second alignment film AL2.
- the counter substrate CT3 shown in the figure includes a strip-shaped second main common electrode CA2 extending linearly along the second direction Y, and does not include a sub-common electrode. That is, in the counter substrate CT3, the common electrode CE is formed in a stripe shape extending in the second direction Y.
- the two second main common electrodes CA2 shown in the figure are arranged in parallel along the first direction X at intervals, and in the following, in order to distinguish them, the second main common electrode on the left side in the drawing is used. Is called CAL2, and the second main common electrode on the right side in the figure is called CAR2.
- the second main common electrode CA2 of the common electrode CE is drawn to the outside of the active area, and is electrically connected to a power feeding unit formed on the array substrate via a conductive member. Potential is supplied.
- FIG. 10 is a plan view schematically showing the structure of the array substrate AR3 when one pixel PX of the liquid crystal display panel LPN in the third configuration example of the present embodiment is viewed from the counter substrate CT3 side.
- the common electrode CE is illustrated by a broken line. Further, only the configuration necessary for the description of one pixel PX is illustrated, and the illustration of the switching element and the like is omitted.
- the array substrate AR3 includes the auxiliary capacitance line C1 and the auxiliary capacitance line C2 extending along the first direction X, the gate wiring G1 extending along the first direction X, and the second A source line S1 and a source line S2 extending along the direction Y, and a pixel electrode PE are provided.
- the pixel electrode PE is covered with the first alignment film AL1.
- the array substrate AR3 includes a strip-shaped first sub-common electrode CB1 extending linearly along the first direction X as a part of the common electrode CE.
- the first sub-common electrode CB1 has the same potential as the second main common electrode CA2.
- the first alignment film AL1 is located above both the pixel electrode PE and the first sub-common electrode CB1.
- the first sub-common electrode CB1 is disposed between the first sub-pixel electrode PB and the second sub-pixel electrode PC.
- the first sub-common electrode CB1 is disposed substantially at the center of the pixel and faces the gate line G1 (or the first sub-common electrode CB1 is disposed above the gate line G1).
- At least a first interlayer insulating film 12 and a second interlayer insulating film 13 are interposed as insulating films between the first sub-common electrode CB1 and the gate wiring G1.
- the first sub-common electrode CB1 extends linearly within the active area, is drawn out of the active area, is electrically connected to a power feeding unit formed on the array substrate AR3, and is supplied with a common potential. .
- the width of the first sub-common electrode CB1 along the second direction Y is along the second direction Y of the gate line G1. It is equal to or greater than the width.
- the pixel electrode PE is disposed between the source line S1 and the source line S2 as in the first configuration example.
- the pixel electrode PE includes a main pixel electrode PA, a first subpixel electrode PB, and a second subpixel electrode PC.
- the main pixel electrode PA is disposed at a substantially middle position between the source line S1 and the source line S2.
- the first subpixel electrode PB and the second subpixel electrode PC are disposed on both sides of the first subcommon electrode CB1.
- the second subpixel electrode PC is opposed to the auxiliary capacitance line C1 (or the second subpixel electrode PC is disposed above the auxiliary capacitance line C1).
- the gate line G1 may be disposed at the upper end or the lower end of the pixel PX, and the auxiliary capacitance line C1 may be disposed substantially at the center of the pixel.
- the first subpixel electrode PB or the second subpixel electrode PC may be opposed to the gate line G1 (or the first subpixel electrode PB or the second subpixel electrode PC is the gate line G1).
- the first sub-common electrode CB1 may be opposed to the auxiliary capacitance line C1 (or the first sub-common electrode CB1 is arranged above the auxiliary capacitance line C1). Is also good).
- the second main common electrode CAL2 and the second main common electrode CAR2 are disposed on both sides of the position directly above the main pixel electrode PA.
- the main pixel electrode PA is disposed between the second main common electrode CAL2 and the second main common electrode CAR2.
- the second main common electrode CAL2 is disposed at the left end portion of the pixel PX and is opposed to the source line S1 (or the second main common electrode CAL2 is disposed above the source line S1. )
- the second main common electrode CAR2 is disposed at the right end of the pixel PX and faces the source line S2 (or the second main common electrode CAR2 is disposed above the source line S2).
- the first sub-common electrode CB1 of the common electrode CE is disposed so as to face the gate wiring, so that an undesired electric field from the gate wiring is shielded. It becomes possible. For this reason, it is possible to suppress an undesired bias from being applied to the liquid crystal layer LQ from the gate wiring, and it is possible to suppress the occurrence of display defects such as burn-in. Therefore, a liquid crystal display device with better display quality can be provided.
- the structure in which the interlayer insulating film is interposed between the pixel electrode PE and the first sub-common electrode CB1 increases the number of manufacturing steps as compared with other configuration examples.
- the total number of manufacturing steps of this configuration example is the same as the number of manufacturing steps of the conventional FFS mode liquid crystal display device.
- a conventional FFS mode liquid crystal display device one configuration in which a multi-domain is formed in one pixel is a configuration in which a pixel electrode is shaped like a dogleg. In the vicinity of the center of this square-shaped pixel electrode, disclination is likely to occur, which may reduce the luminance of the entire pixel.
- the disclination does not occur unlike the FFS mode liquid crystal display device, the luminance is improved.
- the common electrode CE includes a first sub-common electrode CB1 provided on the array substrate AR3 and a second sub-common electrode CB2 provided on the counter substrate CT1 as sub-common electrodes.
- an undesired vertical electric field that is, an electric field along the normal direction of the main surface of the substrate. Can be suppressed.
- FIG. 11 is a plan view schematically showing the structure of the array substrate AR4 when one pixel PX of the liquid crystal display panel LPN in the fourth configuration example of the present embodiment is viewed from the counter substrate CT side. Note that only the configuration necessary for the description of one pixel PX is shown, and the illustration of the switching element and the like is omitted.
- the common electrode CE includes a first main common electrode CA1 provided on the array substrate AR4 as a main common electrode, and a first sub-common electrode CB1 provided on the array substrate AR4 as a sub-common electrode.
- the array substrate AR4 includes the auxiliary capacitance line C1 and the auxiliary capacitance line C2 extending along the first direction X, the gate wiring G1 extending along the first direction X, and the second A source line S1 and a source line S2 extending along the direction Y, and a pixel electrode PE are provided. Further, the array substrate AR4 includes a strip-shaped first main common electrode CA1 (CAL1 and CAR1) linearly extending along the second direction Y and a strip-shaped first linearly extending along the first direction X. A common electrode CE having one sub-common electrode CB1 is provided. That is, in the array substrate AR4, the common electrode CE is formed in a lattice shape.
- the configuration of the first main common electrode CA1 is as described for the array substrate AR2.
- the configuration of the first sub-common electrode CB1 is as described for the array substrate AR3.
- the first alignment film AL1 is located above any of the pixel electrode PE, the first main common electrode CA1, and the first sub-common electrode CB1.
- the first main common electrode CA1 and the first sub-common electrode CB1 of the common electrode CE are drawn to the outside of the active area and formed on the array substrate AR4 via the conductive member. And a common potential is supplied.
- the array substrate AR4 described in the fourth configuration example is any of the counter substrate CT1 described in the first configuration example, the counter substrate CT2 described in the second configuration example, and the counter substrate CT3 described in the third configuration example. Can be combined.
- the combinations with the counter substrate CT3 are summarized in FIG.
- the hatched lines in the figure correspond to combinations that cannot realize the basic configuration of the present embodiment
- the double circles ( ⁇ ) in the figure correspond to the combinations described in each configuration example
- the white circles ( ⁇ ) in the figure indicate each configuration. It corresponds to a possible combination in the example.
- FIG. 13 is a plan view schematically showing one variation of the present embodiment.
- the pixel electrode PE includes two main pixel electrodes PA extending along the second direction Y and parallel to each other along the first direction X, and the first main electrode PA extending along the first direction X. It has a subpixel electrode PB and a second subpixel electrode PC. Such a pixel electrode PE is provided on the array substrate.
- the common electrode CE has a main common electrode CA extending along the second direction Y and a sub-common electrode CB extending along the first direction X.
- the main common electrode CA is disposed on both sides of each of the two main pixel electrodes PA. That is, three main common electrodes CA and two main pixel electrodes PA are alternately arranged.
- the sub-common electrode CB is disposed between the first sub-pixel electrode PB and the second sub-pixel electrode PC. That is, the first sub-pixel electrode PB and the second sub-pixel electrode PC and one sub-common electrode CB are alternately arranged.
- at least a part of the main common electrode CA and the sub-common electrode CB is provided on the counter substrate.
- FIG. 14 is a plan view schematically showing another variation of the present embodiment.
- the pixel electrode PE has a main pixel electrode PA extending along the second direction Y, a first subpixel electrode PB and a second subpixel electrode PC extending along the first direction X.
- the first subpixel electrode PB and the second subpixel electrode PC are coupled to the main pixel electrode PA at a position near the center of the pixel, not at the end of the main pixel electrode PA.
- Such a pixel electrode PE is provided on the array substrate.
- the common electrode CE has a main common electrode CA extending along the second direction Y and a sub-common electrode CB extending along the first direction X.
- the main common electrode CA is disposed on both sides of the pixel electrode PE. That is, two main common electrodes CA and one main pixel electrode PA are alternately arranged.
- the sub-common electrode CB is disposed on both sides of the first sub-pixel electrode PB and the second sub-pixel electrode PC. That is, the three sub-common electrodes CB, the first sub-pixel electrode PB, and the second sub-pixel electrode PC are alternately arranged.
- at least a part of the main common electrode CA and the sub-common electrode CB is provided on the counter substrate.
- FIG. 15 illustrates the positional relationship among the first subpixel electrode PB and the second subpixel electrode PC of the pixel electrode PE and the gate wiring G1, the auxiliary capacitance line C1, and the auxiliary capacitance line C2 that can be applied in the present embodiment. It is a figure for doing.
- FIGS. 15A and 15B correspond to the case where the gate wiring G1 is located approximately in the middle between the auxiliary capacitance line C1 and the auxiliary capacitance line C2.
- the examples shown in FIGS. 15C to 15F correspond to the case where the gate wiring G1 is closer to the auxiliary capacitance line C2 than the auxiliary capacitance line C1.
- the second subpixel electrode PC is located above the auxiliary capacitance line C1.
- the first subpixel electrode PB is located above the auxiliary capacitance line C2.
- the sub-pixel electrode of the pixel electrode adjacent to the upper side of the illustrated pixel electrode PE is also located above the auxiliary capacitance line C1
- the sub-pixel electrode of the pixel electrode adjacent to the lower side of the illustrated pixel electrode PE is also Located above the auxiliary capacitance line C2.
- the first subpixel electrode PB is located between the gate wiring G1 and the auxiliary capacitance line C2. In the example shown in (c) in the drawing, the first subpixel electrode PB is located above the gate line G1. In the example shown by (d) in the drawing, the first subpixel electrode PB is located between the gate line G1 and the auxiliary capacitance line C1.
- the counter substrates CT1 to CT3 are applicable, the array substrate AR2 including the first main common electrode CA1, the array substrate AR3 including the first sub-common electrode CB1, and the first main common. Any of the array substrate AR4 including the electrode CA1 and the first sub-common electrode CB1 is applicable.
- CCDI driving capacitive coupling dot inversion driving
- the storage capacitor Cs and the pixel capacitor are made substantially equal in order to reach a predetermined voltage by superimposing the storage capacitor signal on the pixel electrode PE through the storage capacitor Cs of each pixel.
- the signal voltage amplitude can be substantially halved.
- CCDI driving the storage capacitors Cs of adjacent pixels PX are connected to different storage capacitor lines C, and the storage capacitor voltages supplied to the storage capacitors Cs of adjacent pixels PX have different polarities.
- the storage capacitor Cs of the pixel PX in FIG. 6 when the storage capacitor Cs of the pixel PX in FIG. 6 is connected to the storage capacitor line C1, the storage capacitor Cs of the adjacent pixel PX is connected to the storage capacitor line C2.
- the storage capacitor voltage supplied to the storage capacitor Cs of the adjacent pixel PX can be set to different voltages (for example, high and low).
- the above-described gate driver GD, source driver SD, drive IC chip 2 incorporating a controller, and the like function as a drive mechanism for performing such CCDI drive, and are provided on the array substrate AR.
- a liquid crystal display device with good display quality can be provided.
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Abstract
Description
第1方向に沿ってそれぞれ延出した第1補助容量線及び第2補助容量線と、第1方向に沿って延出し前記第1補助容量線と前記第2補助容量線との間に位置するゲート配線と、第1方向に交差する第2方向に沿ってそれぞれ延出した第1ソース配線及び第2ソース配線と、前記第1ソース配線と前記第2ソース配線との間に位置し第2方向に沿って延出した帯状の主画素電極と、前記主画素電極に繋がり前記第1補助容量線と対向し第1方向に沿って延出した帯状の第1副画素電極と、前記主画素電極に繋がり前記第1副画素電極から離間し第1方向に沿って延出した帯状の第2副画素電極と、水平配向性を示す材料によって形成され前記主画素電極、前記第1副画素電極、及び、前記第2副画素電極を覆う第1配向膜と、を備えた第1基板と、前記主画素電極を挟んだ両側で第2方向に沿ってそれぞれ延出した第2主共通電極と、前記第2主共通電極に繋がり前記第1副画素電極と前記第2副画素電極との間で第1方向に沿って延出した第2副共通電極と、水平配向性を示す材料によって形成され前記第2主共通電極及び前記第2副共通電極を覆う第2配向膜と、を備えた第2基板と、前記第1基板と前記第2基板との間に保持された液晶分子を含む液晶層と、を備えたことを特徴とする液晶表示装置が提供される。
第1方向に沿ってそれぞれ延出した第1補助容量線及び第2補助容量線と、第1方向に沿って延出し前記第1補助容量線と前記第2補助容量線との間に位置するゲート配線と、第1方向に交差する第2方向に沿ってそれぞれ延出した第1ソース配線及び第2ソース配線と、前記第1ソース配線と前記第2ソース配線との間に位置し第2方向に沿って延出した帯状の主画素電極と、前記主画素電極に繋がり前記第1補助容量線と対向し第1方向に沿って延出した帯状の第1副画素電極と、前記主画素電極に繋がり前記第1副画素電極から離間し第1方向に沿って延出した帯状の第2副画素電極と、前記第1ソース配線及び前記第2ソース配線とそれぞれ対向し第2方向に沿って延出した第1主共通電極と、水平配向性を示す材料によって形成され前記主画素電極、前記第1副画素電極、前記第2副画素電極、及び、前記第1主共通電極を覆う第1配向膜と、を備えた第1基板と、前記第1副画素電極と前記第2副画素電極との間で第1方向に沿って延出した第2副共通電極と、水平配向性を示す材料によって形成され前記第2副共通電極を覆う第2配向膜と、を備えた第2基板と、前記第1基板と前記第2基板との間に保持された液晶分子を含む液晶層と、を備えたことを特徴とする液晶表示装置が提供される。
第1方向に沿ってそれぞれ延出した第1補助容量線及び第2補助容量線と、第1方向に沿って延出し前記第1補助容量線と前記第2補助容量線との間に位置するゲート配線と、第1方向に交差する第2方向に沿ってそれぞれ延出した第1ソース配線及び第2ソース配線と、前記第1ソース配線と前記第2ソース配線との間に位置し第2方向に沿って延出した帯状の主画素電極と、前記主画素電極に繋がり前記第1補助容量線と対向し第1方向に沿って延出した帯状の第1副画素電極と、前記主画素電極に繋がり前記第1副画素電極から離間し第1方向に沿って延出した帯状の第2副画素電極と、前記ゲート配線と対向し第1方向に沿って延出した第1副共通電極と、水平配向性を示す材料によって形成され前記主画素電極、前記第1副画素電極、前記第2副画素電極、及び、前記第1副共通電極を覆う第1配向膜と、を備えた第1基板と、前記主画素電極を挟んだ両側で第2方向に沿ってそれぞれ延出し前記第1副共通電極と同電位の第2主共通電極と、水平配向性を示す材料によって形成され前記第2主共通電極を覆う第2配向膜と、を備えた第2基板と、前記第1基板と前記第2基板との間に保持された液晶分子を含む液晶層と、を備えたことを特徴とする液晶表示装置が提供される。
第1副画素電極PBは、例えば主画素電極PAの一端部に結合し、主画素電極PAからその両側に向かって延出している。第2副画素電極PCは、例えば主画素電極PAの他端部に結合し、主画素電極PAからその両側に向かって延出している。これらの第1副画素電極PB及び第2副画素電極PCは、主画素電極PAと略直交している。なお、第1副画素電極PBは主画素電極PAの一端部よりもわずかに他端部寄りに結合していても良いし、同様に、第2副画素電極PCは主画素電極PAの他端部よりもわずかに一端部寄りに結合していても良い。画素電極PEは、例えば、第2副画素電極PCにおいて図示を省略したスイッチング素子と電気的に接続されている。
まず、本実施形態の第1構成例について説明する。
次に、本実施形態の第2構成例について説明する。なお、第1構成例と同一構成については同一の参照符号を付して詳細な説明を省略する。
次に、本実施形態の第3構成例について説明する。なお、第1構成例と同一構成については同一の参照符号を付して詳細な説明を省略する。
次に、本実施形態の第4構成例について説明する。なお、第1構成例と同一構成については同一の参照符号を付して詳細な説明を省略する。
Claims (20)
- 第1方向に沿ってそれぞれ延出した第1補助容量線及び第2補助容量線と、第1方向に沿って延出し前記第1補助容量線と前記第2補助容量線との間に位置するゲート配線と、第1方向に交差する第2方向に沿ってそれぞれ延出した第1ソース配線及び第2ソース配線と、前記第1ソース配線と前記第2ソース配線との間に位置し第2方向に沿って延出した帯状の主画素電極と、前記主画素電極に繋がり前記第1補助容量線と対向し第1方向に沿って延出した帯状の第1副画素電極と、前記主画素電極に繋がり前記第1副画素電極から離間し第1方向に沿って延出した帯状の第2副画素電極と、水平配向性を示す材料によって形成され前記主画素電極、前記第1副画素電極、及び、前記第2副画素電極を覆う第1配向膜と、を備えた第1基板と、
前記主画素電極を挟んだ両側で第2方向に沿ってそれぞれ延出した第2主共通電極と、前記第2主共通電極に繋がり前記第1副画素電極と前記第2副画素電極との間で第1方向に沿って延出した第2副共通電極と、水平配向性を示す材料によって形成され前記第2主共通電極及び前記第2副共通電極を覆う第2配向膜と、を備えた第2基板と、
前記第1基板と前記第2基板との間に保持された液晶分子を含む液晶層と、
を備えたことを特徴とする液晶表示装置。 - 前記主画素電極と前記第2主共通電極との間に電界が形成されていない状態で、前記液晶分子の初期配向方向は、第2方向に略平行であることを特徴とする請求項1に記載の液晶表示装置。
- 前記第1基板は、さらに、前記第1ソース配線及び前記第2ソース配線とそれぞれ対向し第2方向に沿って延出し前記第1配向膜によって覆われ前記第2主共通電極と同電位の第1主共通電極を備えたことを特徴とする請求項2に記載の液晶表示装置。
- 前記第1基板は、さらに、前記ゲート配線と対向し第1方向に沿って延出し前記第1配向膜によって覆われ前記第2主共通電極と同電位の第1副共通電極を備えたことを特徴とする請求項2に記載の液晶表示装置。
- 前記第1基板は、さらに、前記ゲート配線と対向し第1方向に沿って延出し前記第1配向膜によって覆われ前記第2主共通電極と同電位の第1副共通電極と、前記第1副共通電極と繋がり前記第1ソース配線及び前記第2ソース配線とそれぞれ対向し第2方向に沿って延出し前記第1配向膜によって覆われた第1主共通電極と、を備えたことを特徴とする請求項2に記載の液晶表示装置。
- 第1方向に沿ってそれぞれ延出した第1補助容量線及び第2補助容量線と、第1方向に沿って延出し前記第1補助容量線と前記第2補助容量線との間に位置するゲート配線と、第1方向に交差する第2方向に沿ってそれぞれ延出した第1ソース配線及び第2ソース配線と、前記第1ソース配線と前記第2ソース配線との間に位置し第2方向に沿って延出した帯状の主画素電極と、前記主画素電極に繋がり前記第1補助容量線と対向し第1方向に沿って延出した帯状の第1副画素電極と、前記主画素電極に繋がり前記第1副画素電極から離間し第1方向に沿って延出した帯状の第2副画素電極と、前記第1ソース配線及び前記第2ソース配線とそれぞれ対向し第2方向に沿って延出した第1主共通電極と、水平配向性を示す材料によって形成され前記主画素電極、前記第1副画素電極、前記第2副画素電極、及び、前記第1主共通電極を覆う第1配向膜と、を備えた第1基板と、
前記第1副画素電極と前記第2副画素電極との間で第1方向に沿って延出した第2副共通電極と、水平配向性を示す材料によって形成され前記第2副共通電極を覆う第2配向膜と、を備えた第2基板と、
前記第1基板と前記第2基板との間に保持された液晶分子を含む液晶層と、
を備えたことを特徴とする液晶表示装置。 - 前記主画素電極と前記第1主共通電極との間に電界が形成されていない状態で、前記液晶分子の初期配向方向は、第2方向に略平行であることを特徴とする請求項6に記載の液晶表示装置。
- 前記第1基板は、さらに、前記第1主共通電極と繋がり前記ゲート配線と対向し第1方向に沿って延出し前記第1配向膜によって覆われた第1副共通電極を備えたことを特徴とする請求項7に記載の液晶表示装置。
- 第1方向に沿ってそれぞれ延出した第1補助容量線及び第2補助容量線と、第1方向に沿って延出し前記第1補助容量線と前記第2補助容量線との間に位置するゲート配線と、第1方向に交差する第2方向に沿ってそれぞれ延出した第1ソース配線及び第2ソース配線と、前記第1ソース配線と前記第2ソース配線との間に位置し第2方向に沿って延出した帯状の主画素電極と、前記主画素電極に繋がり前記第1補助容量線と対向し第1方向に沿って延出した帯状の第1副画素電極と、前記主画素電極に繋がり前記第1副画素電極から離間し第1方向に沿って延出した帯状の第2副画素電極と、前記ゲート配線と対向し第1方向に沿って延出した第1副共通電極と、水平配向性を示す材料によって形成され前記主画素電極、前記第1副画素電極、前記第2副画素電極、及び、前記第1副共通電極を覆う第1配向膜と、を備えた第1基板と、
前記主画素電極を挟んだ両側で第2方向に沿ってそれぞれ延出し前記第1副共通電極と同電位の第2主共通電極と、水平配向性を示す材料によって形成され前記第2主共通電極を覆う第2配向膜と、を備えた第2基板と、
前記第1基板と前記第2基板との間に保持された液晶分子を含む液晶層と、
を備えたことを特徴とする液晶表示装置。 - 前記主画素電極と前記第2主共通電極との間に電界が形成されていない状態で、前記液晶分子の初期配向方向は、第2方向に略平行であることを特徴とする請求項9に記載の液晶表示装置。
- 前記第1基板は、さらに、前記第1副共通電極と繋がり前記第1ソース配線及び前記第2ソース配線とそれぞれ対向し第2方向に沿って延出し前記第1配向膜によって覆われた第1主共通電極を備えたことを特徴とする請求項10に記載の液晶表示装置。
- 前記第2副画素電極は、前記第2補助容量線と前記ゲート配線との間、または、前記第1補助容量線と前記ゲート配線との間に位置することを特徴とする請求項1乃至11のいずれか1項に記載の液晶表示装置。
- 前記第2副画素電極は、前記第2補助容量線の上方に位置することを特徴とする請求項1乃至11のいずれか1項に記載の液晶表示装置。
- 前記第1副画素電極は前記主画素電極の一端部に繋がり、前記第2副画素電極は前記主画素電極の他端部に繋がったことを特徴とする請求項1乃至11のいずれか1項に記載の液晶表示装置。
- 前記主画素電極は、前記第1ソース配線と前記第2ソース配線との略中間に位置していることを特徴とする請求項14に記載の液晶表示装置。
- 前記第2主共通電極は、前記第1ソース配線及び前記第2ソース配線の上方にそれぞれ位置することを特徴とする請求項1乃至5、9乃至11のいずれか1項に記載の液晶表示装置。
- 前記第2副共通電極は、前記ゲート配線の上方に位置することを特徴とする請求項1乃至8のいずれか1項に記載の液晶表示装置。
- 前記第1配向膜が前記液晶分子を初期配向させる第1配向処理方向及び前記第2配向膜が前記液晶分子を初期配向させる第2配向処理方向は互いに略平行であり、
前記液晶分子は、前記第1基板と前記第2基板との間においてスプレイ配向またはホモジニアス配向していることを特徴とする請求項1乃至11のいずれか1項に記載の液晶表示装置。 - さらに、前記第1基板の外面に配置され第1偏光軸を備えた第1偏光板と、第2基板の外面に配置され第1偏光軸とクロスニコルの位置関係にある第2偏光軸を備えた第2偏光板を備え、前記第1偏光板の第1偏光軸が前記液晶分子の初期配向方向と直交する或いは平行であることを特徴とする請求項18に記載の液晶表示装置。
- 前記第1基板は、容量結合ドット反転駆動を行うための駆動機構を備えたことを特徴とする請求項1乃至11のいずれか1項に記載の液晶表示装置。
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KR1020137026141A KR101635668B1 (ko) | 2011-04-08 | 2012-02-15 | 액정 표시 장치 |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150098042A1 (en) * | 2013-10-04 | 2015-04-09 | Japan Display Inc. | Liquid crystal display device |
US9164333B2 (en) | 2013-03-14 | 2015-10-20 | Japan Display Inc. | Liquid crystal display device |
US9429798B2 (en) | 2014-03-24 | 2016-08-30 | Japan Display Inc. | Liquid crystal display device |
US9709860B2 (en) | 2015-01-22 | 2017-07-18 | Japan Display Inc. | Liquid crystal display device |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6336762B2 (ja) | 2014-01-24 | 2018-06-06 | 株式会社ジャパンディスプレイ | 液晶表示装置 |
CN104007590A (zh) * | 2014-06-17 | 2014-08-27 | 深圳市华星光电技术有限公司 | Tft阵列基板结构 |
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JP6531313B2 (ja) * | 2015-05-01 | 2019-06-19 | 凸版印刷株式会社 | 液晶表示装置 |
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US10916168B2 (en) * | 2019-05-24 | 2021-02-09 | Hannstouch Solution Incorporated | Panel and pixel structure thereof |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000310791A (ja) * | 1999-04-27 | 2000-11-07 | Matsushita Electric Ind Co Ltd | 液晶表示装置 |
JP2001282205A (ja) * | 2000-03-31 | 2001-10-12 | Matsushita Electric Ind Co Ltd | アクティブマトリクス型液晶表示装置およびその駆動方法 |
JP2003241213A (ja) * | 2002-02-18 | 2003-08-27 | Matsushita Electric Ind Co Ltd | 液晶表示素子及びそれを備えた画像表示応用装置 |
JP2006053592A (ja) * | 2005-10-31 | 2006-02-23 | Lg Philips Lcd Co Ltd | 液晶表示装置 |
JP2007516464A (ja) * | 2004-01-26 | 2007-06-21 | シャープ株式会社 | 液晶表示素子及びその駆動方法 |
JP2009192822A (ja) * | 2008-02-14 | 2009-08-27 | Toshiba Mobile Display Co Ltd | 液晶表示装置 |
JP2009216793A (ja) * | 2008-03-07 | 2009-09-24 | Hitachi Displays Ltd | 液晶表示装置 |
JP2009244287A (ja) * | 2008-03-28 | 2009-10-22 | Toshiba Mobile Display Co Ltd | 液晶表示装置および液晶表示装置の駆動方法 |
Family Cites Families (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06222397A (ja) * | 1993-01-25 | 1994-08-12 | Sony Corp | 液晶表示装置 |
JP2701698B2 (ja) | 1993-07-20 | 1998-01-21 | 株式会社日立製作所 | 液晶表示装置 |
JPH07159807A (ja) | 1993-12-06 | 1995-06-23 | Hitachi Ltd | アクティブマトリクス型液晶表示装置 |
TW454101B (en) | 1995-10-04 | 2001-09-11 | Hitachi Ltd | In-plane field type liquid crystal display device comprising liquid crystal molecules with more than two different kinds of reorientation directions and its manufacturing method |
JPH09160041A (ja) | 1995-12-08 | 1997-06-20 | Toshiba Corp | 液晶表示素子 |
JPH09160042A (ja) | 1995-12-08 | 1997-06-20 | Toshiba Corp | 液晶表示素子 |
JPH09160061A (ja) | 1995-12-08 | 1997-06-20 | Toshiba Corp | 液晶表示素子 |
JP3486859B2 (ja) * | 1996-06-14 | 2004-01-13 | 大林精工株式会社 | 液晶表示装置 |
JPH1026765A (ja) | 1996-07-10 | 1998-01-27 | Toshiba Corp | 液晶表示素子、投影型液晶表示装置及び基板 |
JP3644653B2 (ja) | 1996-08-07 | 2005-05-11 | 三菱電機株式会社 | 液晶表示装置 |
JPH1090708A (ja) * | 1996-09-17 | 1998-04-10 | Toshiba Corp | 液晶表示素子 |
JPH10186366A (ja) * | 1996-12-26 | 1998-07-14 | Fujitsu Ltd | 液晶表示装置 |
JP3883244B2 (ja) * | 1997-01-23 | 2007-02-21 | エルジー フィリップス エルシーディー カンパニー リミテッド | 液晶表示装置 |
JP4364332B2 (ja) | 1998-06-23 | 2009-11-18 | シャープ株式会社 | 液晶表示装置 |
KR100303351B1 (ko) | 1998-12-17 | 2002-06-20 | 박종섭 | 수직 배향 모드 액정 표시 장치 |
JP4107978B2 (ja) | 2003-02-21 | 2008-06-25 | スタンレー電気株式会社 | 液晶表示素子 |
KR100698047B1 (ko) * | 2003-04-19 | 2007-03-23 | 엘지.필립스 엘시디 주식회사 | 횡전계형 액정 표시 장치 및 그 제조 방법 |
JP2004325953A (ja) * | 2003-04-25 | 2004-11-18 | Nec Lcd Technologies Ltd | 液晶表示装置 |
JP2005003802A (ja) | 2003-06-10 | 2005-01-06 | Toshiba Matsushita Display Technology Co Ltd | 液晶表示装置 |
JP2005084233A (ja) * | 2003-09-05 | 2005-03-31 | Toshiba Matsushita Display Technology Co Ltd | 表示装置および表示装置の製造方法 |
KR100959367B1 (ko) * | 2003-10-13 | 2010-05-25 | 엘지디스플레이 주식회사 | 횡전계형 액정표시장치 |
KR100606410B1 (ko) * | 2003-12-11 | 2006-07-28 | 엘지.필립스 엘시디 주식회사 | 박막트랜지스터 어레이 기판 및 그 제조 방법 |
JP4088619B2 (ja) | 2004-01-28 | 2008-05-21 | シャープ株式会社 | アクティブマトリクス基板及び表示装置 |
KR100617040B1 (ko) | 2004-03-16 | 2006-08-30 | 엘지.필립스 엘시디 주식회사 | 횡전계방식 액정표시소자 및 그 제조방법 |
JP2005292515A (ja) | 2004-03-31 | 2005-10-20 | Sharp Corp | 液晶表示装置およびその駆動方法ならびに電子機器 |
KR101247113B1 (ko) | 2005-11-22 | 2013-04-01 | 삼성디스플레이 주식회사 | 표시장치 |
KR101320494B1 (ko) | 2006-04-12 | 2013-10-22 | 엘지디스플레이 주식회사 | 수평전계방식 액정표시장치 및 그 제조방법 |
TW200813535A (en) | 2006-09-12 | 2008-03-16 | Wintek Corp | Liquid crystal panel and liquid crystal display |
KR101413275B1 (ko) | 2007-01-29 | 2014-06-30 | 삼성디스플레이 주식회사 | 액정 표시 패널 및 이의 제조 방법 |
KR20080071231A (ko) | 2007-01-30 | 2008-08-04 | 삼성전자주식회사 | 액정 표시 장치 |
KR101427708B1 (ko) | 2007-02-01 | 2014-08-11 | 삼성디스플레이 주식회사 | 액정 표시 패널 |
JP2009294633A (ja) * | 2007-09-26 | 2009-12-17 | Nec Lcd Technologies Ltd | 液晶表示装置 |
JP5380416B2 (ja) * | 2010-10-20 | 2014-01-08 | 株式会社ジャパンディスプレイ | 液晶表示装置 |
-
2012
- 2012-02-15 CN CN201280017222.3A patent/CN103534642B/zh not_active Expired - Fee Related
- 2012-02-15 WO PCT/JP2012/053544 patent/WO2012137540A1/ja active Application Filing
- 2012-02-15 KR KR1020137026141A patent/KR101635668B1/ko active IP Right Grant
- 2012-02-15 JP JP2013508783A patent/JP5707487B2/ja not_active Expired - Fee Related
-
2013
- 2013-10-08 US US14/048,361 patent/US9025097B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000310791A (ja) * | 1999-04-27 | 2000-11-07 | Matsushita Electric Ind Co Ltd | 液晶表示装置 |
JP2001282205A (ja) * | 2000-03-31 | 2001-10-12 | Matsushita Electric Ind Co Ltd | アクティブマトリクス型液晶表示装置およびその駆動方法 |
JP2003241213A (ja) * | 2002-02-18 | 2003-08-27 | Matsushita Electric Ind Co Ltd | 液晶表示素子及びそれを備えた画像表示応用装置 |
JP2007516464A (ja) * | 2004-01-26 | 2007-06-21 | シャープ株式会社 | 液晶表示素子及びその駆動方法 |
JP2006053592A (ja) * | 2005-10-31 | 2006-02-23 | Lg Philips Lcd Co Ltd | 液晶表示装置 |
JP2009192822A (ja) * | 2008-02-14 | 2009-08-27 | Toshiba Mobile Display Co Ltd | 液晶表示装置 |
JP2009216793A (ja) * | 2008-03-07 | 2009-09-24 | Hitachi Displays Ltd | 液晶表示装置 |
JP2009244287A (ja) * | 2008-03-28 | 2009-10-22 | Toshiba Mobile Display Co Ltd | 液晶表示装置および液晶表示装置の駆動方法 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9164333B2 (en) | 2013-03-14 | 2015-10-20 | Japan Display Inc. | Liquid crystal display device |
US20150098042A1 (en) * | 2013-10-04 | 2015-04-09 | Japan Display Inc. | Liquid crystal display device |
US9429798B2 (en) | 2014-03-24 | 2016-08-30 | Japan Display Inc. | Liquid crystal display device |
US10025144B2 (en) | 2014-03-24 | 2018-07-17 | Japan Display Inc. | Liquid crystal display device |
US9709860B2 (en) | 2015-01-22 | 2017-07-18 | Japan Display Inc. | Liquid crystal display device |
US10203568B2 (en) | 2015-01-22 | 2019-02-12 | Japan Display Inc. | Liquid crystal display device |
US10613395B2 (en) | 2015-01-22 | 2020-04-07 | Japan Display Inc. | Liquid crystal display device |
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CN103534642B (zh) | 2016-01-27 |
KR20130131463A (ko) | 2013-12-03 |
WO2012137540A8 (ja) | 2013-01-10 |
JPWO2012137540A1 (ja) | 2014-07-28 |
US20140036214A1 (en) | 2014-02-06 |
CN103534642A (zh) | 2014-01-22 |
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US9025097B2 (en) | 2015-05-05 |
JP5707487B2 (ja) | 2015-04-30 |
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