WO2012133433A1 - Procédé de formation de film d'isolation de grille et procédé de fabrication d'un dispositif à semi-conducteur - Google Patents

Procédé de formation de film d'isolation de grille et procédé de fabrication d'un dispositif à semi-conducteur Download PDF

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WO2012133433A1
WO2012133433A1 PCT/JP2012/057971 JP2012057971W WO2012133433A1 WO 2012133433 A1 WO2012133433 A1 WO 2012133433A1 JP 2012057971 W JP2012057971 W JP 2012057971W WO 2012133433 A1 WO2012133433 A1 WO 2012133433A1
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layer
hfo
forming
insulating film
gate insulating
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PCT/JP2012/057971
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English (en)
Japanese (ja)
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行則 森田
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独立行政法人産業技術総合研究所
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Priority to JP2013507625A priority Critical patent/JP5652926B2/ja
Publication of WO2012133433A1 publication Critical patent/WO2012133433A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02356—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment to change the morphology of the insulating layer, e.g. transformation of an amorphous layer into a crystalline layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Definitions

  • the present invention relates to a method for forming a gate insulating film and a method for manufacturing a semiconductor device using the method for forming a gate insulating film.
  • a gate insulating film made of a material having a high dielectric constant (high-k) is used instead of SiO 2 as a gate insulating film of a MOS transistor.
  • This is a technique for directly suppressing the tunnel current by increasing the actual film thickness by increasing the dielectric constant of the insulating film while reducing the electrical equivalent oxide film thickness according to the scaling law.
  • HfO 2 hafnium oxide, hafnia; dielectric constant about 13-20
  • the first is to use an alloy such as TiN or TaN doped with a certain metal as the gate electrode, and to reduce and decompose the SiO 2 layer present at the interface between HfO 2 and Si during heat treatment by the oxygen defect injection effect of the doped metal.
  • HfO 2 is formed directly on Si to suppress an increase in equivalent oxide thickness due to the low dielectric constant interface SiO 2 layer (see Non-Patent Documents 1 and 2).
  • a high-k insulating film having a dielectric constant of about 13 to 20 is used. This method is not sufficient because it is necessary to reduce the film thickness to a region where the tunnel current directly flows.
  • the present invention relates to a method for forming a gate insulating film using an HfO 2 layer as a gate insulating film, and a gate that realizes a higher-k gate stack having an extremely thin equivalent oxide film thickness without an SiO 2 layer formed at the interface.
  • An object of the present invention is to provide a method for forming an insulating film together with a method for manufacturing a semiconductor device using the method for forming a gate insulating film.
  • the method for forming a gate insulating film of the present invention that solves the above problems includes a step of forming an HfO 2 layer on a silicon substrate by an atomic layer growth method, and an oxygen control metal layer having an oxygen absorption effect on the HfO 2 layer. forming a, and a step of heat treatment of the HfO 2 layer is heated to a temperature to crystallize, and, before the thermal treatment process, to control the amount of crystal growth nuclei contained in the HfO 2 layer in It is characterized by.
  • the amount of crystal growth nuclei can be controlled by reducing the thickness of the HfO 2 layer to be formed. Further, the above heat treatment, along with increasing the dielectric constant of the HfO 2 layer by crystallizing the HfO 2 layer, vital absorb oxygen released from the HfO 2 layer during the heat treatment in the oxygen-controlled metal layer, HfO 2 grid It is possible to perform a heat treatment for removing SiO 2 formed at the HfO 2 / Si interface by using the effect of removing oxygen from the surface.
  • the oxygen control metal layer having an oxygen absorption effect is preferably one kind of metal layer selected from Ti layer, Hf layer and Zr layer or one kind of metal nitride layer selected from HfN and AlN.
  • the method for forming a gate insulating film of the present invention can include a step of forming a gate electrode layer on the oxygen control metal layer before the heat treatment.
  • the method for manufacturing a semiconductor device of the present invention includes a step of forming a gate insulating film by the above-described method for forming a gate insulating film of the present invention.
  • an oxygen control metal layer having an oxygen absorption effect is formed on the HfO 2 layer, and a heat treatment for crystallization by rapid heating is performed, so that no SiO 2 layer is formed at the interface, A higher-k gate stack with a thin equivalent oxide thickness can be realized.
  • FIG. 1 is a schematic cross-sectional view illustrating a method for forming a gate insulating film according to the present invention.
  • FIG. 2 is a time-series schematic diagram illustrating the relationship between the thickness of the HfO 2 layer during film formation and the crystal phase after heat treatment.
  • FIG. 3 is a schematic diagram illustrating the amount of impurities in the HfO 2 layer.
  • FIG. 4 is a schematic cross-sectional view of the gate stack in the embodiment.
  • FIG. 5 is a graph showing the CV characteristics of the example.
  • an amorphous HfO 2 layer 2 serving as a gate insulating film is formed on a silicon substrate 1 as a semiconductor substrate (FIG. 1A).
  • the amorphous HfO 2 layer 2 is formed by an atomic layer deposition (ALD) method.
  • ALD atomic layer deposition
  • the atomic layer growth method is excellent in in-plane uniformity of a silicon wafer having a large diameter of 300 mm as compared with the sputtering method, and is therefore suitable for mass production, and is generally used in practice. Therefore, since the present invention is a method suitable for actual mass production, the amorphous HfO 2 layer 2 is formed by the atomic layer growth method.
  • an oxygen control metal layer 3 having an oxygen absorption effect is formed on the HfO 2 layer 2 (FIG. 1B).
  • the oxygen control metal layer 3 has an effect as a protective film at the time of a heat treatment performed later, and also has an effect of absorbing oxygen generated from the HfO 2 layer 2 at the time of the heat treatment.
  • the oxygen control metal layer 3 is composed of a metal layer having an oxygen absorption effect or a metal nitride layer having an oxygen absorption effect similar to that of the metal layer.
  • the oxygen control metal layer 3 is selected from a Ti layer, a Hf layer, and a Zr layer A metal layer or a kind of metal nitride layer selected from HfN and AlN is preferable.
  • the oxygen control metal layer 3 can be formed by vapor deposition, ion plating, sputtering, or the like.
  • the film thickness of the oxygen control metal layer 3 can be about 1 to 100 nm. A more preferable film thickness is about 10 to 100 nm.
  • heat treatment is performed to heat to a temperature at which the HfO 2 layer 2 is crystallized (FIG. 1C).
  • This heat treatment is a rapid heat treatment for crystallizing the amorphous HfO 2 layer 2 and preferentially generating the HfO 2 layer 4 having a crystal phase having a dielectric constant higher than that of the amorphous HfO 2 .
  • the heat treatment is performed, for example, in an N 2 (nitrogen gas) atmosphere at 400 to 1000 ° C., preferably about 800 to 900 ° C.
  • the crystal phase of HfO 2 includes a cubic phase, a monoclinic phase, and the like, and in particular, a high dielectric constant is obtained when the phase is a cubic phase.
  • the heat treatment is a heat treatment for increasing the dielectric constant of the HfO 2 layer by crystallizing the HfO 2 layer 2 to obtain the HfO 2 layer 4 having a cubic phase.
  • oxygen released from the HfO 2 layer 2 during the heat treatment is absorbed by the oxygen control metal layer 3 and SiO 2 formed at the HfO 2 / Si interface using the effect of removing oxygen from the HfO 2 lattice. It is the heat processing which removes. More specifically, when the amorphous HfO 2 layer 2 is crystallized into the cubic phase HfO 2 layer 4 by heat treatment, excess oxygen generated by recombination of the crystal lattice is released from the HfO 2 layer 2. This oxygen oxidizes the silicon substrate 1 at the interface between the HfO 2 layer 2 and the silicon substrate 1 and forms an inner layer of SiO 2 .
  • SiO 2 has a lower dielectric constant than the cubic HfO 2 layer 4 as a gate insulating film, and the equivalent oxide film thickness of the entire gate stack increases, it is not suitable for increasing the dielectric constant of the gate insulating film. is there.
  • this regard because it forms an oxygen control metal layer 3 on the HfO 2 layer 2, directly absorb the oxygen released from the HfO 2 layer 2 by an oxygen control metal layer 3. Thus, to suppress the formation of SiO2 in the HfO 2 / Si interface. Even if the inner layer of SiO 2 is formed, the oxygen control metal layer 3 is formed, so that oxygen is removed from the HfO 2 lattice of the HfO 2 layer 4 and oxygen defects (Vo) are removed from the HfO 2 layer 4. By introducing it, SiO 2 formed at the HfO 2 / Si interface is reduced and removed by reductive decomposition.
  • the gate insulating film can have a high dielectric constant.
  • the amount of crystal growth nuclei contained in the HfO 2 layer is controlled before the heat treatment step.
  • the cubic HfO 2 layer 4 can be easily obtained by the above heat treatment.
  • the growth method it has been difficult to easily obtain a cubic phase by the heat treatment.
  • the inventors have studied the cause, and as shown in FIG. 2A, when the HfO 2 layer 102 is formed by the conventional atomic layer growth method, impurities in the HfO 2 layer 102 are compared with the sputtering method.
  • the monoclinic phase is preferentially generated over the cubic phase using the impurities in the HfO 2 layer 102 as growth nuclei.
  • the monoclinic phase is a crystal phase having a lower dielectric constant than the cubic phase.
  • the gate insulating film having a high dielectric constant is obtained. Is difficult to get. Therefore, in the present invention, the amount of crystal growth nuclei contained in the HfO 2 layer is controlled before the heat treatment step. Thereby, a cubic phase is preferentially generated.
  • the control of the amount of crystal growth nuclei contained in the HfO 2 layer performed before the heat treatment step is to reduce the amount of impurities serving as crystal growth nuclei in the HfO 2 layer.
  • HfO 2 As a specific means for reducing the amount of impurities in the HfO 2 layer, as shown in FIG. 2B, when forming the HfO 2 layer on the silicon substrate 1 by atomic layer growth, HfO 2 is used. The thickness of the two layers 2 is reduced.
  • the HfO 2 layer 2 has a predetermined impurity density according to film forming conditions determined by a film forming apparatus, a film forming process, and the like. As an example, as shown in FIG.
  • the HfO 2 layer 2 formed by depositing on the silicon substrate by the atomic layer growth method has a residual impurity per unit area (cm 2 ) of the 1 nm thick HfO 2 layer. About 1 ⁇ 10 13 pieces. Therefore, when the thickness is about 8.7 nm as in the prior art, there are about 8.7 ⁇ 10 13 impurities per unit area (cm 2 ), in other words, monoclinic crystal growth nuclei. . If the thickness of the HfO 2 layer is 2.4 nm, there are about 2.4 ⁇ 10 13 impurities per unit area (cm 2 ), in other words, monoclinic crystal growth nuclei. The number of crystal growth nuclei is 1/3 or less of the conventional one. Therefore, after the heat treatment, the HfO 2 layer 2 can be made into a cubic crystal having a high dielectric constant.
  • a cubic HfO 2 layer was easily obtained on a silicon substrate by using an atomic layer growth method suitable for mass production without interposing an SiO 2 inner layer, and a high dielectric constant was obtained.
  • specific means for reducing the amount of impurities in the HfO 2 layer in is not limited to reducing the thickness of the HfO 2 layer 2.
  • the HfO 2 layer 2 is heated to a temperature at which crystallization does not occur before the heat treatment for crystallization. Can be considered. By heating to a temperature at which crystallization does not occur, the amount of impurities and the amount of crystal growth nuclei in the HfO 2 layer 2 can be reduced.
  • the manufacturing method of the semiconductor device of the present invention including the HfO 2 layer as the gate insulating film includes a step of forming the gate electrode layer 5 on the HfO 2 layer 4.
  • the gate electrode layer 5 may be formed on the oxygen control metal layer 3 when the oxygen control metal layer 3 having an oxygen absorption effect as a protective layer is formed on the HfO 2 layer 4. , also by removing the oxygen control metal layer 3 on the HfO 2 layer 4 may be formed on the HfO 2 layer 4 in contact with the HfO 2 layer 4.
  • Examples of the gate electrode layer 5 include a TiN electrode layer and a TaN electrode layer.
  • the material of the gate electrode layer 5 is not limited to TiN or TaN, and any known material used for MOS transistors can be used. Different materials may be used for the gate electrode layer 5 of the pMOS transistor and the gate electrode layer 5 of the nMOS transistor.
  • the formation of the gate electrode layer 5 may be performed before the heat treatment for crystallization of the HfO 2 layer described above.
  • Example 1 In manufacturing the transistor, as shown in a schematic cross-sectional view of the gate stack of one embodiment of the present invention in FIG. 4A, an HfO 2 layer is 2.4 nm thick on the silicon substrate 11 by atomic layer growth. Formed with. Next, a Ti layer having a thickness of 6 nm was formed as an oxygen control metal layer on the HfO 2 layer. Next, a TiN layer having a thickness of 10 nm was formed as a gate electrode layer on the Ti layer. After forming the TiN layer, heat treatment was performed by rapidly heating to 900 ° C. When the HfO 2 layer after the heat treatment was analyzed with an XRD apparatus, the HfO 2 layer was in a cubic phase. Further, no SiO 2 inner layer was present at the interface between the HfO 2 layer and the silicon substrate. The relative dielectric constant of the HfO 2 layer after heat treatment was 40, and the equivalent oxide thickness as a gate stack for transistors was 0.25 nm.
  • Example 2 As shown in the schematic cross-sectional view of the gate stack of another embodiment of the present invention in FIG. 4B, an Hf layer having a thickness of 6 nm was formed as an oxygen control metal layer instead of the Ti layer of the first embodiment.
  • a gate stack was formed in the same manner as in Example 1 except for the above.
  • the HfO 2 layer after the heat treatment was analyzed with an XRD apparatus, the HfO 2 layer was in a cubic phase. Further, no SiO 2 inner layer was present at the interface between the HfO 2 layer and the silicon substrate.
  • the relative dielectric constant of the HfO 2 layer after heat treatment was 40, and the equivalent oxide thickness as a gate stack for transistors was 0.25 nm.
  • FIG. 5 shows the measurement results of the CV characteristics of the gate stacks formed in Example 1 and Example 2.
  • the CV characteristics of Example 1 shown in FIG. 5A and Example 2 shown in FIG. 5B were good.

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Abstract

La présente invention concerne un procédé de formation d'un film d'isolation de grille transformant une couche de HfO2 en film d'isolation de grille, un empilement de grilles à constante diélectrique plus élevée présentant une épaisseur de film d'oxydation équivalente extrêmement petite étant obtenu sans former de couche de SiO2 à l'interface. Le procédé de formation d'un film d'isolation de grille comprend une étape de formation d'une couche de HfO2 (2) sur un substrat en silicium (1) par un procédé de croissance par couche atomique, une étape de formation d'une couche métallique de commande d'oxygène (3) présentant un effet d'absorption d'oxygène sur la couche HfO2 (2) et une étape de traitement thermique chauffant la couche de fO2 (2) jusqu'à la température de cristallisation. Avant l'étape de traitement thermique, la quantité de noyaux de croissance cristalline dans la couche de HfO2 (2) est contrôlée.
PCT/JP2012/057971 2011-03-28 2012-03-27 Procédé de formation de film d'isolation de grille et procédé de fabrication d'un dispositif à semi-conducteur WO2012133433A1 (fr)

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Cited By (2)

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CN110379709A (zh) * 2019-07-25 2019-10-25 上海华力集成电路制造有限公司 氧化铪薄膜的制造方法
JP2021531661A (ja) * 2018-07-26 2021-11-18 東京エレクトロン株式会社 半導体デバイス用の結晶学的に安定化された強誘電性ハフニウムジルコニウムベースの膜を形成する方法

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JP2011049531A (ja) * 2009-07-31 2011-03-10 Hitachi Kokusai Electric Inc 半導体デバイスの製造方法、半導体デバイス及び基板処理装置
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JP2010177675A (ja) * 2002-02-28 2010-08-12 Hitachi Kokusai Electric Inc 半導体装置の製造方法
JP2008537359A (ja) * 2005-04-21 2008-09-11 インターナショナル・ビジネス・マシーンズ・コーポレーション 自己整合され積極的にスケーリングされたｃｍｏｓデバイスにおけるゲート電極の金属／金属窒化物二重層のｃｍｏｓ構造体及び半導体構造体
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JP2011049531A (ja) * 2009-07-31 2011-03-10 Hitachi Kokusai Electric Inc 半導体デバイスの製造方法、半導体デバイス及び基板処理装置
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021531661A (ja) * 2018-07-26 2021-11-18 東京エレクトロン株式会社 半導体デバイス用の結晶学的に安定化された強誘電性ハフニウムジルコニウムベースの膜を形成する方法
JP7369899B2 (ja) 2018-07-26 2023-10-27 東京エレクトロン株式会社 半導体デバイス用の結晶学的に安定化された強誘電性ハフニウムジルコニウムベースの膜を形成する方法
CN110379709A (zh) * 2019-07-25 2019-10-25 上海华力集成电路制造有限公司 氧化铪薄膜的制造方法

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