WO2012132624A1 - 表示装置及び表示装置制御回路 - Google Patents
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- WO2012132624A1 WO2012132624A1 PCT/JP2012/053942 JP2012053942W WO2012132624A1 WO 2012132624 A1 WO2012132624 A1 WO 2012132624A1 JP 2012053942 W JP2012053942 W JP 2012053942W WO 2012132624 A1 WO2012132624 A1 WO 2012132624A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
- G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/136—Incoming video signal characteristics or properties
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/66—Transforming electric information into light information
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2370/00—Aspects of data communication
- G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/115—Selection of the code volume for a coding unit prior to coding
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/132—Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
- H04N19/17—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object
- H04N19/176—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
Definitions
- the present invention relates to a display device and a display device control circuit, and more particularly to data transfer from the display device control circuit to a display device driver.
- liquid crystal display devices and other panel display devices are required to display various contents.
- Examples of content displayed on the panel display device include still images, 2D (2-dimensional) moving images, and 3D (3-dimensional) moving images.
- the inventors consider that in displaying such various contents, it is appropriate to switch the frame rate (the number of frame images per unit time) according to the contents. For example, when a liquid crystal display device is used as a TV, even when a still image content or content with a lot of still images (for example, Web content) is displayed, even if a frame rate (120 Hz) corresponding to double speed is used, Fewer images can be displayed. On the other hand, when displaying a 2D moving image, it is desirable to use a higher frame rate, for example, a frame rate (180 Hz) corresponding to triple speed in order to reduce blur. In the display of 3D moving images, it is further required to alternately display an image for the right eye and an image for the left eye.
- a higher frame rate for example, a frame rate (240 Hz) corresponding to quadruple speed should be used. Is desirable. If only the image quality is considered, a high frame rate may be used regardless of the content. However, since the power consumption of the display device increases when the frame rate is high, the inventors consider that it is desirable that the frame rate be variable rather than always displaying at a high frame rate.
- One of the problems that the inventors have recognized in developing a display device in which the frame rate is variable is that the amount of necessary display data transfer varies greatly depending on the frame rate. For example, when displaying at a frame rate of 3 ⁇ speed, the transfer amount of display data is 1.5 times that when displaying at a frame rate of 2 ⁇ speed. There are two problems that the transfer amount of display data changes. One is that it is difficult to design wiring boards and transfer cables for EMI countermeasures. If the transfer amount of display data changes, the frequency range of EMI widens and it becomes difficult to take measures against EMI.
- Another problem is that if the clock signal used in data transfer is generated by PLL (phase locked loop) or DLL (delay locked loop), the PLL or DLL is relocked when the display data transfer amount is changed. It is a point that needs to be done. The display data cannot be transferred until the relocking of the PLL or DLL is completed, which is not preferable for image display.
- PLL phase locked loop
- DLL delay locked loop
- the data transfer of display data in the display device is disclosed in, for example, Japanese Patent Application Laid-Open No. 2010-141775.
- This publication discloses a technique for compressing display data and storing it in a frame memory and driving a display panel in accordance with decompressed data obtained by decompressing (or decompressing) compressed data read from the frame memory. Yes.
- the compression rate is adjusted according to the display image. In the case of a display image whose image quality does not deteriorate greatly even when the compression rate is increased, the compression rate is set high, and power consumption is reduced. On the other hand, if the compression rate is increased, the compression rate is set low in the case of a display image having a large image quality deterioration, and sufficient image quality is ensured in image display corresponding to the developed data.
- Japanese Patent No. 4507265 discloses a technique for storing display data after compressing the display data. This publication discloses selecting a compression method according to the correlation of pixel data of four pixels.
- JP 2010-141775 A Japanese Patent No. 4507265
- an object of the present invention is to provide a display device and a display device control circuit that can cope with the problem of a change in the transfer amount of display data accompanying a change in frame rate.
- a display device includes a display device, a display device driver for driving the display device, a compression unit corresponding to an operation for generating compressed data by compression processing on image data, and compressed data from the compression unit.
- a transmission unit that transmits the compressed data to the display device driver by a serial data signal when receiving the data.
- the compression unit performs compression processing at a compression rate selected according to the frame rate at which the display device driver drives the display device.
- the display device driver receives the serial data signal from the transmission unit, expands the compressed data transmitted by the serial data signal, generates expanded data, and drives the display device in response to the expanded data.
- the compression rate in the compression process is set so that the transfer rate from the serial data signal transmission unit to the display device driver is constant regardless of the frame rate.
- the compression unit performs compression processing at a compression rate selected according to the frame rate at which the display device driver drives the display device.
- the display device driver receives the serial data signal from the transmission unit, expands the compressed data transmitted by the serial data signal, generates expanded data, and drives the display device in response to the expanded data.
- the compression rate is set so that the transfer rate from the serial data signal transmission unit to the display device driver is constant regardless of the frame rate.
- a display device and a display device control circuit that can cope with the problem of a change in the transfer amount of display data accompanying a change in frame rate.
- FIG. 1 is a block diagram showing the configuration of the display device according to the first embodiment of the present invention.
- the display device of the present invention is applied to the liquid crystal display device 1.
- the present invention is not limited to other display devices (for example, PDP (plasma display panel) display devices, organic EL (electroluminescence) display devices, etc.). It will be apparent to those skilled in the art that the present invention can also be applied.
- the liquid crystal display device 1 is configured to display an image on the liquid crystal display panel 2 in accordance with image data transferred from the outside.
- the liquid crystal display panel 2 includes pixels, data lines (signal lines), and gate lines (scanning lines).
- Each of the pixels is composed of an R subpixel (a subpixel for displaying red color), a G subpixel (a subpixel for displaying green color), and a B subpixel (a subpixel for displaying blue color).
- Each sub-pixel is provided at a position where the corresponding data line and gate line intersect.
- pixels corresponding to the same gate line are referred to as pixel lines.
- the image data is supplied as data representing the gradation of each of the R subpixel, G subpixel, and B subpixel in 8 bits, that is, data representing the gradation of each pixel in 24 bits.
- the number of bits of the image data is not limited to this.
- the liquid crystal display device 1 includes a timing control circuit 3, a driver 4, and a gate line driving circuit 5.
- the timing control circuit 3 controls the driver 4 and the gate line driving circuit 5 so that a desired image is displayed on the liquid crystal display panel 2.
- the driver 4 drives the data lines of the liquid crystal display panel 2, and the gate line drive circuit 5 drives the gate lines of the liquid crystal display panel 2.
- the timing control circuit 3, the driver 4, and the gate line driving circuit 5 are mounted as separate ICs (integrated circuits).
- the driver 4 is configured such that the frame rate of image display on the liquid crystal display panel 2 is variable.
- the variable frame rate means that various contents (for example, WWW, 2D (2-dimensional) video, and 3D (3-dimensional) video) are optimally displayed while suppressing power consumption. Useful.
- the liquid crystal display device 1 is provided with a plurality of drivers 4, and the timing control circuit 3 and each driver 4 are Peer-to-Peer connected. Specifically, the timing control circuit 3 and each driver 4 are connected to each driver 4 via a dedicated serial signal line 6 and a clock signal line 7. Data transfer between the timing control circuit 3 and each driver 4 is performed by serial data transfer via the serial signal line 6.
- an architecture in which a timing controller and a driver are connected by a bus is also known.
- the timing control circuit 3 and each driver 4 are connected to a Peer.
- the architecture connected by -to-Peer connection is useful in that the transfer rate required for data transfer between the timing control circuit 3 and each driver 4 can be reduced.
- the timing control circuit 3 generally has two roles. First, the timing control circuit 3 performs timing control of the entire liquid crystal display device 1 in response to a timing control signal supplied from the outside. Specifically, the timing control circuit 3 transmits various control data to each driver 4 via the serial signal line 6, and also transmits a timing control signal to the gate line driving circuit 5, and the driver 4 and the gate line driving circuit. 5 is controlled. Transfer of control data from the timing control circuit 3 to each driver 4 is performed during the blanking period of each horizontal synchronization period.
- the control data sent from the timing control circuit 3 to each driver 4 includes polarity inversion data and timing control data.
- the polarity inversion data is data specifying the polarity of the drive signal for the data line.
- the timing control data includes, for example, data informing each driver 4 of the start of the vertical synchronization period and horizontal synchronization period, data indicating data start (data instructing each driver 4 to take in image data), data line driving Contains data for starting.
- Each driver 4 operates at an operation timing corresponding to the timing control data. Control of the frame rate of image display on the liquid crystal display panel 2 is performed by these timing control data.
- the timing control circuit 3 supplies the image data to each driver 4 via the serial signal line 6.
- the timing control circuit 3 has a function of compressing image data and supplying the image data to each driver 4.
- the compression processing for the image data will be described later in detail.
- the image data is supplied to each driver 4 during the display period of each horizontal synchronization period.
- the timing control circuit 3 and the driver 4 will be described in detail.
- the timing control circuit 3 includes a compression circuit 11 and a serial transmission circuit 12.
- the compression circuit 11 performs compression processing on the image data to generate compressed data.
- image data is compressed with 4 pixels as a unit. As described above, since the image data corresponding to one pixel is 24 bits, the image data is compressed in units of 96-bit image data.
- the compression rate of the compression processing in the compression circuit 11 is variable.
- the compression rate is defined as the ratio of the number of bits of compressed data to the number of bits of original image data.
- the compression rate of 100% means that the compression circuit 11 outputs the image data as it is without performing the compression process.
- the compression circuit includes the case where the compression rate is 100%.
- the data output from 11 is called compressed data.
- the compression circuit 11 is supplied with frame rate specifying data for specifying the frame rate, and the compression rate of the compression processing is selected according to the frame rate specifying data. That is, the compression rate is adjusted according to the frame rate of image display on the liquid crystal display panel 2. This is because the transfer rate of serial data transfer is kept constant by changing the compression rate according to the frame rate, as will be described later. For example, when the frame rate is high, it is required to supply a large amount of image data to each driver 4, but when the frame rate is high, the transfer rate of serial data transfer is set by setting the compression rate high. Can be kept constant.
- the compression circuit 11 supplies the compressed data generated by the compression process and the compression mode data indicating the compression rate to the serial transmission device 12.
- the serial transmission circuit 12 generates a serial data signal incorporating the compressed data and compression mode data received from the compression circuit 11 and timing control data to be sent to each driver 4, and transmits the serial data signal to each driver 4 by serial data communication.
- the serial transmission circuit 12 includes a PLL circuit 13 that generates a clock signal, and transmits a serial data signal to each driver 4 via the serial signal line 6 in synchronization with the generated clock signal.
- the serial transmission circuit 12 transmits the clock signal generated by the PLL circuit 13 to each driver 4 via the clock signal line 7.
- each driver 4 includes a serial receiving circuit 14, a developing circuit 15, a display latch unit 16, and a data line driving circuit 17.
- the serial reception circuit 14 receives the serial data signal sent from the serial transmission circuit 12 in synchronization with the clock signal supplied via the clock signal line 7, and samples the serial data signal to compress the compressed data and the compressed data. Extract mode data and timing control data. The extracted compressed data and compressed mode data are sent to the decompression circuit 15.
- the expansion circuit 15 expands the received compressed data to generate display data, and sequentially transfers the generated display data to the display latch unit 16.
- the decompression circuit 15 recognizes the compression rate from the compression mode data, and decompresses the compressed data in accordance with the recognized compression rate.
- the display latch unit 16 sequentially latches display data received from the expansion circuit 15.
- the display latch unit 16 of each driver 4 stores display data of a pixel corresponding to the driver 4 among the pixels of one pixel line.
- the data line driving circuit 17 drives the data lines in response to the display data latched by the display latch unit 16. In each horizontal synchronization period, in response to the display data stored in the display latch unit 16, the data lines corresponding to the display data are driven. 1 shows only the configuration of one driver 4, it should be noted that other drivers 4 are configured in the same manner.
- the frame rate of image display on the liquid crystal display panel 2 is variable.
- the frame rate is selected from 120 Hz (2 ⁇ speed), 180 Hz (3 ⁇ speed), and 240 Hz (4 ⁇ speed).
- the frame rate is designated by frame rate designation data given to the timing control circuit 3, and the timing control circuit 3 and the driver 4 operate so as to display an image at the frame rate designated by the frame rate designation data.
- the frame rate is switched according to the content displayed on the liquid crystal display panel 2.
- the frame rate is set to 120 Hz.
- Still images that are not seriously blurred are displayed at a relatively low frame rate in order to reduce power consumption.
- the frame rate is set to a higher value, specifically, 180 Hz in order to reduce blur.
- the frame rate is set to a higher value, specifically 240 Hz.
- the compression rate of the compression circuit 11 is switched in response to the switching of the frame rate, whereby the transfer rate of serial data transfer from the timing control circuit 3 to each driver 4 is changed. Is kept constant.
- the combination of the compression rate and the frame rate can be changed in various ways, but it is important that the product of the compression rate and the frame rate is constant regardless of the frame rate.
- the PLL circuit 13 need not be relocked.
- the frame rate is switched without changing the compression rate, it is necessary to increase or decrease the data transfer rate in serial data transfer, and it is necessary to switch the frequency band of the clock signal generated by the PLL circuit 13.
- the frame rate is switched from 120 Hz to 180 Hz with the compression rate kept constant, the data transfer amount in serial data transfer is 1.5 times, and the data transfer speed is also 1.5 times. .
- the frequency band of the clock signal generated by the PLL circuit 13 to a frequency band including a frequency 1.5 times the original frequency.
- the problem is that the PLL circuit 13 needs to be relocked when switching the frequency band of the clock signal generated by the PLL circuit 13. This means that display data cannot be transferred until the re-lock is completed, which is not preferable for image display.
- the transfer rate of serial data transfer is kept constant even when the frame rate is switched, it is not necessary to switch the frequency band of the clock signal generated by the PLL circuit 13. This produces the advantage of eliminating the need to relock the PLL circuit 13.
- FIG. 3A shows a circuit configuration of a general PLL circuit
- FIG. 3B is a block diagram showing an example of a circuit configuration of the PLL circuit 13 of the present embodiment.
- a general PLL circuit as shown in FIG. 3A, a configuration including a phase comparator 21, a VCO (voltage-controlled oscillator) 22, and a frequency divider 123 is known.
- the phase comparator 21 outputs an output voltage corresponding to the phase of the primary clock and the output signal from the frequency divider 123, and the VCO 22 outputs the output clock in response to the output voltage received from the phase comparator 21.
- a signal is output.
- the frequency divider 123 outputs an output signal obtained by dividing the output clock signal.
- a low-pass filter LPF is often provided between the phase comparator 21 and the VCO 22, but is not shown in FIG. 3A.
- the frequency band of the output clock signal output from the VCO 22 is generally not so wide. For this reason, when the frequency of the output clock signal is greatly changed, the frequency division ratio of the frequency divider 123 is switched by the frequency division ratio changing circuit 123 a provided in the frequency divider 123. Therefore, if a configuration is adopted in which the frequency band of the clock signal generated by the PLL circuit 13 is switched in accordance with the switching of the frame rate, the frequency divider 123 shown in FIG. It is necessary to adopt a circuit configuration in which the frequency division ratio can be switched.
- the frequency band of the clock signal generated by the PLL circuit 13 is not switched.
- the configuration of the frequency divider 23 is simplified. This is advantageous in the implementation of the PLL circuit 13. Note that the frequency divider 23 is not necessary when generating a clock signal having the same frequency as the original clock.
- the output of the VCO 22 is directly connected to the input of the phase comparator 21 or a signal having the same frequency as the output of the VCO 22 is input to the input of the phase comparator 21 via some circuit (for example, a delay circuit). Supplied.
- a DLL (delay locked loop) circuit may be used instead of the PLL circuit 13. Even in this case, since the transfer rate of the serial data transfer is kept constant, it is not necessary to provide the DLL circuit with a function of switching the frequency band. This contributes to simplification of the configuration of the DLL circuit.
- the frame rate is switched according to the content displayed on the liquid crystal display panel 2. Further, the compression rate of the compression circuit 11 is switched in response to the switching of the frame rate, whereby the transfer rate of serial data transfer from the timing control circuit 3 to each driver 4 is kept constant. This facilitates EMI countermeasures and eliminates the need to relock the PLL circuit 13. In addition, in this embodiment, it is not necessary to switch the frequency band of the clock signal generated by the PLL circuit 13, and the circuit configuration of the PLL circuit 13 can be simplified.
- FIG. 4 is a block diagram showing the configuration of the display device according to the second embodiment of the present invention.
- the driver 4 employs an architecture that performs clock recovery from a serial data signal transmitted to the driver 4 through the serial signal line 6.
- the clock signal line 7 is not provided.
- the architecture for performing clock recovery from a serial data signal is effective for reducing the number of signal lines of a cable connecting the timing control circuit 3 and the driver 4.
- An example of a serial data transfer method corresponding to such an architecture is LVDS (low voltage differential signaling).
- the PLL circuit 18 is provided in the serial reception circuit 14A of the driver 4.
- the PLL circuit 18 generates a clock signal synchronized with the serial data signal transmitted to the driver 4.
- the serial reception circuit 14A samples the serial data signal at a timing synchronized with the clock signal generated by the PLL circuit 18, and extracts compressed data, compressed mode data, and timing control data.
- a DLL circuit may be used instead of the PLL circuit 18.
- the frame rate is switched according to the content displayed on the liquid crystal display panel 2 as in the first embodiment. Further, the compression rate of the compression circuit 11 is switched in response to the switching of the frame rate, whereby the transfer rate of serial data transfer from the timing control circuit 3 to each driver 4 is kept constant.
- both circuits 13 and 18 need not be relocked.
- the PLL circuit 13 not only the PLL circuit 13 but also the PLL circuit 18 can adopt a simple circuit configuration that does not have a function of switching the frequency division ratio as shown in FIG. 3B.
- a reproduction signal obtained by performing waveform reproduction on the serial data signal is sent to the phase comparator 21 instead of the original clock signal. Entered.
- FIG. 5 is a block diagram showing a display device according to the third embodiment of the present invention.
- the display device of the present invention is applied to an image processing device 50 including the liquid crystal display device 1.
- the image processing device 50 includes a processing device 51 that performs graphic processing, a memory 52, and an external input interface 53.
- Examples of the processing device 51 include a CPU (central processing unit) and a DSP (digital signal). processor).
- the processing device 51 performs graphic processing using the memory 52 as a work area.
- the external input interface 53 is connected to an external device such as an optical disk drive.
- the external input interface 53 includes a compression circuit 53a, and the external input interface 53 performs compression processing on image data received from an external device.
- the operation of the compression circuit 53a is the same as that of the compression circuit 11 of the first embodiment and the second embodiment.
- the compression circuit 53a is supplied with frame rate specifying data for specifying a frame rate, and performs compression processing on the image data at a compression rate selected according to the frame rate specifying data.
- the data generated by the compression process is sent to the timing control circuit 3 via the bus 54 and further sent to the driver 4 by serial data transfer.
- the frame rate is switched according to the content displayed on the liquid crystal display panel 2, as in the first and second embodiments. Further, the compression rate of the compression circuit 11 is switched in response to the switching of the frame rate, and thereby the transfer rate of serial data transfer from the timing control circuit 3 to the driver 4 is kept constant.
- the frame rate is set according to the type of content to be displayed.
- the present invention is applicable even when the frame rate is variably adjusted due to factors other than the type of content.
- Block Configuration As described above, in the present embodiment, block coding is performed in which compression is performed for each block composed of a plurality of pixels as compression processing. More specifically, in the present embodiment, one block is composed of four pixels belonging to the same pixel line, and image data (total 96 bits) of the four pixels is compressed together.
- FIG. 6 shows an arrangement of four pixels in each block.
- the four pixels included in each block may be referred to as a pixel A, a pixel B, a pixel C, and a pixel D, respectively.
- Each of the pixels A to D has an R subpixel, a G subpixel, and a B subpixel.
- the R sub-pixel, the G sub-pixel, and the B sub-pixel of the pixel A are referred to by symbols R A , G A , and B A , respectively.
- the subpixels R A , G A , B A , R B , G B , B B , R C , G C , B C , R D , G D , B D of the four pixels of each block are Are located on the same pixel line and connected to the same gate line.
- a block that is a target of compression processing is referred to as a target block.
- the compression circuit 11 is configured to compress image data by the following five compression methods: -Uncompressed-(1x4) pixel compression-(2 + 1x2) pixel compression-(2x2) pixel compression-(4x1) pixel compression
- the (1 ⁇ 4) pixel compression is a method in which processing for reducing the number of bit planes for each of all four pixels of the target block (dither processing using a dither matrix in this embodiment) is performed independently. This (1 ⁇ 4) pixel compression is suitable when the correlation between the image data of the four pixels is low. (2 + 1 ⁇ 2) pixel compression defines a representative value representing image data of two pixels out of all four pixels of the target block, while reducing the number of bit planes for each of the other two pixels. This is a method for processing.
- This (2 + 1 ⁇ 2) pixel compression is suitable when the correlation between the image data of two of the four pixels is high and the correlation between the image data of the other two pixels is low.
- (2 ⁇ 2) pixel compression means that all four pixels of a target block are divided into two sets of two pixels, and a representative value representative of image data is determined for each of the two pixel sets.
- a method for compressing data This (2 ⁇ 2) pixel compression is suitable when the correlation between the image data of two of the four pixels is high and the correlation between the image data of the other two pixels is high.
- (4 ⁇ 1) pixel compression is a method in which representative values representing the image data of the four pixels of the target block are determined and the image data is compressed. This (4 ⁇ 1) pixel compression is suitable when the correlation between the image data of all four pixels of the target block is high.
- the compression ratio is variable in the above-described four compression methods ((1 ⁇ 4) pixel compression, (2 + 1 ⁇ 2) pixel compression, (2 ⁇ 2) pixel compression, and (4 ⁇ 1) pixel compression)). It is.
- the compression method is (1 ⁇ 4) pixel compression, (2 + 1 ⁇ 2) pixels according to the correlation between the image data of the four pixels constituting the target block.
- the compression is selected from compression, (2 ⁇ 2) pixel compression, and (4 ⁇ 1) pixel compression.
- (4 ⁇ 1) pixel compression is used, the correlation between the image data of two of the four pixels is high, and the other When the correlation between the image data of two pixels is high, (2 ⁇ 2) pixel compression is used.
- the compression rate is 100%, non-compression is selected regardless of the correlation between the image data of the four pixels constituting the target block.
- the compression circuit 11 includes a shape recognition unit 31, a (1 ⁇ 4) pixel compression unit 32, and a (2 + 1 ⁇ 2) pixel compression unit 33, as illustrated in FIG. 7A. , A (2 ⁇ 2) pixel compression unit 34, a (4 ⁇ 1) pixel compression unit 35, and a compressed data selection unit 36.
- the shape recognition unit 31 When the shape recognition unit 31 receives the image data of the pixels of the target block, it recognizes the correlation between the received image data of the pixels. For example, the shape recognizing unit 31 determines which combination of the image data of the pixels in the first row and the fourth column has high correlation, or which pixel has low correlation of the image data with respect to other pixels. Recognize Further, the shape recognition unit 31 has five compression methods: non-compression, (1 ⁇ 4) pixel compression, (2 + 1 ⁇ 2) pixel compression, (2 ⁇ 2) pixel compression, depending on the recognition result and the compression rate to be used. Generate compressed data selection data that indicates which of (4 ⁇ 1) pixel compression should be used.
- the (1 ⁇ 4) pixel compressing unit 32, the (2 + 1 ⁇ 2) pixel compressing unit 33, the (2 ⁇ 2) pixel compressing unit 34, and the (4 ⁇ 1) pixel compressing unit 35 are respectively described in the above (1 ⁇ 4).
- Pixel compression, (2 + 1 ⁇ 2) pixel compression, (2 ⁇ 2) pixel compression, and (4 ⁇ 1) pixel compression are performed on the image data, respectively (1 ⁇ 4) compressed data and (2 + 1 ⁇ 2) Generate compressed data, (2 ⁇ 2) compressed data, and (4 ⁇ 1) compressed data.
- the (1 ⁇ 4) pixel compression unit 32, the (2 + 1 ⁇ 2) pixel compression unit 33, the (2 ⁇ 2) pixel compression unit 34, and the (4 ⁇ 1) pixel compression unit 35 include frame rate designation data.
- the compression rate of the compression processing is switched according to the frame rate.
- the compressed data selection unit 36 is based on the compressed data selection data received from the shape recognition unit 31, the image data itself, (1 ⁇ 4) compressed data, (2 + 1 ⁇ 2) compressed data, (2 ⁇ 2) compressed data, And (4 ⁇ 1) compressed data is selected and output as compressed data.
- (1 ⁇ 4) compressed data, (2 + 1 ⁇ 2) compressed data, (2 ⁇ 2) compressed data, and (4 ⁇ 1) compressed data is selected as the compressed data.
- a compression type recognition bit indicating which of the above four compression methods is used is included.
- the compressed data output from the compressed data selection unit 36 is sent to the serial transmission circuit 12.
- a decompression circuit 15 provided on the reception side determines which of the above-described five compression methods the compressed data received from the serial reception circuit 14 (14A) is compressed. At the same time, the compression rate is recognized from the compression mode data, and the compressed image data is expanded by the compression method used for compression and the expansion method corresponding to the compression rate.
- the expansion circuit 15 includes a shape recognition unit 41, a (1 ⁇ 4) pixel expansion unit 42, a (2 + 1 ⁇ 2) pixel expansion unit 43, and a (2 ⁇ 2) pixel expansion unit. 44, a (4 ⁇ 1) pixel development unit 45, and a display data selection unit 46.
- the (1 ⁇ 4) pixel development unit 42, the (2 + 1 ⁇ 2) pixel development unit 43, the (2 ⁇ 2) pixel development unit 44, and the (4 ⁇ 1) pixel development unit 45 are each (1 ⁇ 4) pixels. It has a function of expanding compressed data compressed by compression, (2 + 1 ⁇ 2) pixel compression, (2 ⁇ 2) pixel compression, and (4 ⁇ 1) pixel compression.
- the (1 ⁇ 4) pixel expansion unit 42, the (2 + 1 ⁇ 2) pixel expansion unit 43, the (2 ⁇ 2) pixel expansion unit 44, and the (4 ⁇ 1) pixel expansion unit 45 recognize the compression rate based on the compression mode data. Then, decompression processing is performed according to the recognized compression rate.
- the expanded data is described as (1 ⁇ 4) expanded data, (2 + 1 ⁇ 2) expanded data, (2 ⁇ 2) expanded data, and (4 ⁇ 1) expanded data, respectively.
- the shape recognition unit 41 recognizes the compression method actually used for compression from the compression type recognition bit and the compression mode data, and (1 ⁇ 4) decompressed data, (2 + 1 ⁇ 2) decompressed data, (2 ⁇ 2) Display data selection data that indicates which of the expanded data, (4 ⁇ 1) expanded data, and compressed data should be selected as display data is generated.
- the display data selection unit 46 selects any one of (1 ⁇ 4) expanded data, (2 + 1 ⁇ 2) expanded data, (2 ⁇ 2) expanded data, (4 ⁇ 1) expanded data, and compressed data according to the display data selection data. Is output as display data.
- the compressed data is selected as display data as it is when the compression rate is 100% (that is, when non-compression is used as the compression method).
- the display data output from the expansion circuit 15 is supplied to the display latch unit 16 and the data line driving circuit 17 and used for driving the liquid crystal display panel 2.
- the gradation values of the G sub-pixels of the pixels A, B, C, and D are described as G A , G B , G C , and G D , respectively, and the B sub-pixels of the pixels A, B, C, and D are used.
- the gradation values of the pixels are described as B A , B B , B C , and B D , respectively.
- the compression circuit 11 determines which of the following cases the image data of 4 pixels in 1 row and 4 columns of the target block corresponds to: Case A: Correlation between image data of arbitrary combinations of pixels among the four pixels is low. Case B: There is a high correlation between the image data of two pixels, and the image data of the other two pixels has a low correlation with the previous two pixels and has a low correlation with each other. Case C: There is a high correlation between 4-pixel image data. Case D: There is a high correlation between the image data of two pixels, and there is a high correlation between the image data of the other two pixels.
- FIG. 8 is a flowchart showing a procedure for selecting a compression method according to the correlation between pixels.
- i ⁇ ⁇ A, B, C, D ⁇ j ⁇ ⁇ A, B, C, D ⁇ i ⁇ j When the following condition (A) is not satisfied for all combinations of i and j, the compression circuit 11 corresponds to case A (that is, correlation between image data of pixels of an arbitrary combination of four pixels). Is low) (step S01).
- the compression circuit 11 defines a first set of two pixels and a second set of two pixels for four pixels, and the first set of two pixels for all the combinations. It is determined whether or not the condition that the difference between the image data between the two pixels is smaller than a predetermined value and the difference between the image data between the second set of two pixels is smaller than the predetermined value is satisfied (step S02). . More specifically, the compression circuit 11 determines whether any of the following conditions (B1) to (B3) is satisfied.
- Condition (B1)
- the compression circuit 11 falls under Case B (that is, there is a high correlation between the image data of two pixels and the other two pixels It is determined that the image data has a low correlation with each other. In this case, the compression circuit 11 determines to perform (2 + 1 ⁇ 2) pixel compression.
- the compression circuit 11 determines that the difference between the maximum value and the minimum value of the image data of the four subpixels is greater than a predetermined value for each of all the colors of the four pixels. It is determined whether or not the condition of small is satisfied. More specifically, the compression circuit 11 determines whether or not the following condition (C) is satisfied (step S03).
- the compression circuit 11 determines that it corresponds to case C (there is high correlation between the image data of 4 pixels). In this case, the compression circuit 11 determines to perform (4 ⁇ 1) pixel compression.
- the compression circuit 11 determines to perform (2 ⁇ 2) pixel compression.
- the shape recognition unit 31 of the compression circuit 11 performs (1 ⁇ 4) pixel compression, (2 + 1 ⁇ 2) pixel compression, (2 ⁇ 2) pixel compression, and (3 + 1) pixel based on the correlation recognition result as described above. Either compression or (4 ⁇ 1) pixel compression is selected. As will be described later, the image data of the target block is compressed using the selected compression method.
- FIGS. 9A and 9B are conceptual diagrams showing the format of (1 ⁇ 4) compressed data.
- (1 ⁇ 4) pixel compression is a compression method that is employed when the correlation between image data of arbitrary combinations of four pixels is low.
- the format of compressed data is shown.
- the basic format is the same regardless of the compression ratio, except that the overall bit number and the bit number distribution are different.
- (1 ⁇ 4) compressed data includes a header (attribute data) including a compression type recognition bit, R A , G A , B A data corresponding to the image data of pixel A, , R B , G B , B B data corresponding to the image data of the pixel B, R C , G C , B C data corresponding to the image data of the pixel C, and R D , corresponding to the image data of the pixel D , G D, composed of the B D data.
- the compression type recognition bit is data indicating the type of compression method used for compression.
- (1 ⁇ 4) pixel compression 1 bit is assigned to the compression type recognition bit.
- the value of the compression type recognition bit of (1 ⁇ 4) compressed data is “0”.
- the R A , G A , and B A data are bit plane reduction data obtained by performing a process of reducing the number of bit planes on the gradation values of the R, G, and B subpixels of the pixel A
- R B , G B , B B data is bit plane reduction data obtained by performing a process of reducing the number of bit planes on the gradation values of the R, G, B subpixels of the pixel B
- R C , G C , and B C data are bit plane reduction data obtained by performing a process of reducing the number of bit planes on the gradation values of the R, G, and B subpixels of the pixel C
- R D , G D , and B D data are bit plane reduction data obtained by performing a process of reducing the number of bit planes on the gradation values of the R, G, and B subpixels of the pixel D.
- the compression ratio when the compression ratio is 50% (FIG. 9A), only the BD data corresponding to the B subpixel of the pixel D is 3-bit data, and the others are 4-bit data. In such bit allocation, the total number of bits including the compression type recognition bits is 48 bits. On the other hand, if the compression ratio is 66.7 percent (Fig. 9B), a G A, G B, G C data 6-bit data corresponding to the pixel A, B, G subpixels and C, other 5-bit data. In such bit allocation, the total number of bits including the compression type recognition bits is 64 bits.
- FIG. 10A is a conceptual diagram illustrating (1 ⁇ 4) pixel compression.
- FIG. 10A illustrates (1 ⁇ 4) pixel compression when the compression rate is 50%, but even when the compression rate is 66.7%, similar compression processing is performed except that the number of bits is different. Note that is done.
- dither processing using a dither matrix is performed for each of the pixels A to D, thereby reducing the number of bit planes of the image data of the pixels A to D. Specifically, first, processing for adding the error data ⁇ to each of the image data of the pixels A, B, C, and D is performed.
- the error data ⁇ of each pixel is determined from the coordinates of the pixel using a basic matrix that is a Bayer matrix. The calculation of the error data ⁇ will be described later separately. In the following description, it is assumed that the error data ⁇ determined for the pixels A, B, C, and D are 0, 5, 10, and 15, respectively.
- rounding is performed to generate R A , G A , B A data, R B , G B , B B data, R C , G C , BC data, and R D , G D , B D data.
- the rounding process is a process of adding the value 2 (n-1) to desired n and then cutting off the lower n bits.
- the compression ratio is 50%
- the gradation value of the B sub-pixel of the pixel D is subjected to processing of truncating the lower 5 bits after adding the value 16, and the value 8 is set for the other gradation values.
- a process of truncating the lower 4 bits is performed.
- FIG. 10B is a diagram showing a decompression method of (1 ⁇ 4) compressed data.
- FIG. 10B illustrates the decompression process of (1 ⁇ 4) compressed data when the compression rate is 50%. However, even when the compression rate is 66.7%, the processing is the same except that the number of bits is different. Note that the expansion process is performed.
- BD data bit advance is performed.
- the number of bits carried is the same as the number of bits truncated in (1 ⁇ 4) pixel compression. That is, when the compression rate is 50%, the BD data corresponding to the B subpixel of the pixel D is subjected to a 5-bit carry, and the other data is subjected to a 4-bit carry.
- the compression ratio is 66.7%, 2-bit carry is performed for the gradation values of the G sub-pixels of the pixels A, B, and C, and 3-bit carry is performed for the other gradation values. .
- the error data ⁇ is subtracted to complete the decompression of the (1 ⁇ 4) compressed data.
- (1 ⁇ 4) expanded data indicating the gradation of each sub-pixel of the pixels A to D is generated.
- the (1 ⁇ 4) expanded data is generally data obtained by restoring the original image data. If the gradation values of the subpixels of the pixels A to D of the (1 ⁇ 4) expanded data in FIG. 10B are compared with the gradation values of the subpixels of the pixels A to D of the original image data in FIG. 10A. It will be understood that the original image data of the pixels A to D is generally restored by the above expansion method.
- FIGS. 11A and 11B are conceptual diagrams showing the format of (2 + 1 ⁇ 2) compressed data.
- the (2 + 1 ⁇ 2) pixel compression has a high correlation between the image data of two pixels, and the image data of the other two pixels has a low correlation with the previous two pixels, and Used when the correlation is low.
- the format of compressed data is shown.
- the basic format is the same regardless of the compression ratio, except that the overall bit number and the bit number distribution are different.
- (2 + 1 ⁇ 2) compressed data includes a header including compression type recognition bits, shape recognition data, an R representative value, a G representative value, and B It consists of representative values, size recognition data, ⁇ comparison result data, R i , G i , B i data, and R j , G j , B j data.
- the compression type recognition bit is data indicating the type of compression method used for compression, and in the (2 + 1 ⁇ 2) compressed data, 2 bits are assigned to the compression type recognition bit. In this embodiment, the value of the compression type recognition bit of (2 + 1 ⁇ 2) compressed data is “10”.
- the shape recognition data is 3-bit data indicating which of the pixels A to D has high correlation between the image data of two pixels.
- (2 + 1 ⁇ 2) pixel compression is used, among the pixels A to D, the correlation between the image data of two pixels is high, and the remaining two pixels are correlated with the image data of other pixels. Is low. Therefore, there are the following six combinations of two pixels with high correlation of image data: ⁇ Pixels A and C ⁇ Pixels B and D ⁇ Pixels A and B ⁇ Pixels C and D ⁇ Pixels B and C ⁇ Pixels A and D
- 3 bits indicate which of these 6 combinations is 2 pixels having high correlation between the image data.
- the R representative value, the G representative value, and the B representative value are values that represent the gradation values of the R sub-pixel, the G sub-pixel, and the B sub-pixel of two pixels having high correlation, respectively.
- the R representative value and the G representative value are 5-bit or 6-bit data
- the B representative value is 5-bit data.
- the R representative value, the G representative value, and the B representative value are all 7-bit or 8-bit data.
- ⁇ comparison data is data indicating whether or not the difference in gradation value of sub-pixels of the same color between two highly correlated pixels is larger than a predetermined threshold ⁇ .
- the ⁇ comparison data includes the difference between the gradation values of the R subpixels of the two pixels having high correlation and the gradation value of the G subpixel of the two pixels having high correlation. Is 2-bit data indicating whether or not the difference is greater than a predetermined threshold value ⁇ .
- the ⁇ comparison data includes the difference in the gradation values of the R subpixels of the two pixels having high correlation and the G subpixels of the two pixels having high correlation. This is 3-bit data indicating whether or not the difference between the image data and the difference between the image data of the B subpixels of the two pixels having high correlation is larger than a predetermined threshold value ⁇ .
- the size recognition data is data indicating which gradation value is larger among sub-pixels of the same color of two pixels having high correlation.
- the size recognition data indicates which of the two highly correlated pixels has the larger gradation value of the R sub-pixel of which pixel and which of the G sub-pixel of which pixel. This is data indicating whether the gradation value is large.
- the large / small recognition data includes two pixels having high correlation, which of the R sub-pixels has the larger gradation value, and which pixel has the G sub-value.
- the size recognition data corresponding to the R sub-pixel is generated only when the difference between the gradation values of the R sub-pixels of two pixels having high correlation is larger than the threshold ⁇
- the size recognition data corresponding to the G sub-pixel is The magnitude recognition data corresponding to the B subpixel is generated only when the difference between the gradation values of the G subpixels of the two pixels having high correlation is larger than the threshold ⁇ , and It is generated only when the difference between the gradation values of the subpixels is larger than the threshold value ⁇ . Therefore, the size recognition data is data of 0 to 2 bits when the compression rate is 50%, and data of 0 to 3 bits when the compression rate is 66.7%.
- R i , G i , B i data, and R j , G j , B j data reduce the number of bit planes for the R, G, B sub-pixel gradation values of two pixels with low correlation This is bit plane reduction data obtained by processing.
- R i , G i , B i data, and R j , G j , B j data are all 4-bit data.
- the G i and G j data are 6-bit data
- the R i and B i data and the R j and B j data are 5-bit data.
- (2 + 1 ⁇ 2) pixel compression will be described with reference to FIG. 12A.
- the compression rate is 50%
- the correlation between the image data of the pixels A and B is high
- the image data of the pixels C and D is low in correlation with the image data of the pixels A and B
- generation of (2 + 1 ⁇ 2) compressed data when the correlation between the image data of the pixels C and D is low is described. It is easily understood by those skilled in the art that (2 + 1 ⁇ 2) compressed data can be generated in the same manner when the compression rate is 66.7% and when the combination of highly correlated pixels is different.
- the compression rate is 66.7% and when the combination of highly correlated pixels is different.
- the compression processing of the image data of the pixels A and B will be described.
- the average value of the gradation values is calculated for each of the R subpixel, the G subpixel, and the B subpixel.
- between the gradation values of the G subpixel are larger than the predetermined threshold ⁇ . Whether or not is compared. Further, when the compression rate is 66.7%, it is compared whether or not the difference
- the size recognition data is created by the following procedure.
- between the gradation values of the R subpixels of the pixels A and B is larger than the threshold value ⁇
- the magnitude recognition data indicates which of the R subpixels of the pixels A and B has the larger gradation value. Described in When the difference
- any of the pixels A and B Whether the gradation value of the B subpixel is large is described in the size recognition data.
- the compression ratio is 50%, or when the difference
- the compression rate is 50%
- the gradation values of the R subpixels of the pixels A and B are 50 and 59, respectively
- the threshold value ⁇ is 4.
- of the gradation value is larger than the threshold value ⁇ , this is described in the ⁇ comparison data
- the gradation value of the R sub-pixel of the pixel B is the R value of the pixel A.
- the gradation values of the G subpixels of the pixels A and B are 2 and 1, respectively.
- the magnitude recognition data does not describe the magnitude relation between the gradation values of the G subpixels of the pixels A and B.
- the size recognition data is 1-bit data.
- error data ⁇ is added to the average values Rave, Gave, and Bave of the gradation values of the R subpixel, the G subpixel, and the B subpixel.
- the error data ⁇ is determined using a basic matrix from the coordinates of two pixels in each combination. The calculation of the error data ⁇ will be described later separately. In the following description, in the present embodiment, the error data ⁇ determined for the pixels A and B is assumed to be zero.
- rounding is performed to calculate the R representative value, the G representative value, and the B representative value.
- the numerical value added in the rounding process and the number of bits rounded down in the bit truncation process are the difference between the gradation values
- the compression rate is 50%
- of the R sub-pixel gradation value is larger than the threshold ⁇
- the average value Rave of the R sub-pixel gradation values is After adding the value 5, a process of truncating the lower 3 bits is performed, whereby an R representative value is calculated. Otherwise, a process of adding the value 2 to the average value Rave and then truncating the lower 2 bits is performed, whereby the R representative value is calculated.
- is larger than the threshold value beta
- the lower 3 bits after adding a value 5 to the average value Gave of the gradation values of the G subpixels A truncation process is performed, whereby a G representative value is calculated. Otherwise, the process of adding the value 2 to the average value Gave and then truncating the lower 2 bits is performed, whereby the G representative value is calculated.
- the threshold value beta the lower 3 bits after adding a value 5 to the average value Gave of the gradation values of the G subpixels A truncation process is performed, whereby a G representative value is calculated.
- a G representative value is calculated. Otherwise, the average value Gave is calculated as it is as the G representative value. Further, when the difference of gradation values
- processing similar to (1 ⁇ 4) pixel compression is performed. That is, dither processing using a dither matrix is performed independently for each of the pixels C and D, thereby reducing the number of bit planes of the image data of the pixels C and D.
- a process of adding the error data ⁇ to each of the image data of the pixels C and D is performed. As described above, the error data ⁇ of each pixel is calculated from the coordinates of the pixel. In the following description, it is assumed that the error data ⁇ determined for the pixels C and D is 10 and 15, respectively.
- rounding is performed to generate R C , G C , B C data, R D , G D , and B D data.
- the compression rate is 50%
- a process of adding the value 8 to each of the gradation values of the R, G, and B subpixels of each of the pixels C and D and then truncating the lower 4 bits is performed. Is called.
- R C, G C, B C data, R D, G D, B D data is calculated.
- the compression rate is 66.7%
- a value 4 is added to each of the gradation values of the R and B subpixels of each of the pixels C and D, and then processing of truncating the lower 3 bits is performed.
- FIG. 12B is a diagram showing a decompression method of (2 + 1 ⁇ 2) compressed data.
- the compression rate is 50%
- the correlation between the image data of the pixels A and B is high
- the image data of the pixels C and D is low in correlation with the image data of the pixels A and B
- (2 + 1 ⁇ 2) compressed data when the correlation between the image data of the pixels C and D is low is described.
- (2 + 1 ⁇ 2) compressed data can be expanded in the same manner when the compression rate is 66.7% and when the correlation between pixels is different.
- bit advance processing is performed for the R representative value, the G representative value, and the B representative value.
- bit advance processing is performed for the R representative value, the G representative value, and the B representative value.
- the threshold ⁇ described in the ⁇ comparison data and the compression rate
- execution / non-execution of the bit carry processing is determined.
- bit advance processing when the compression rate is 50% will be described. If the difference
- error data ⁇ is subtracted for each of the R representative value, the G representative value, and the B representative value, and further, (2 + 1) from the R representative value, the G representative value, and the B representative value.
- X2 A process of restoring the gradation values of the R, G, and B subpixels of the pixels A and B of the development data is performed.
- the ⁇ comparison data and the size recognition data are used.
- the ⁇ comparison data when it is described that the difference
- the gradation values of the R sub-pixels of the pixels A and B are restored as matching the R representative value.
- the gradation value of the R subpixel of the pixel A is restored as a value obtained by subtracting the value 5 from the R representative value
- the gradation value of the R subpixel of the pixel B is restored to the value 5 from the R representative value. It has been restored as a value added.
- the same processing is performed using the ⁇ comparison data and the size recognition data.
- the values of the G sub-pixels of the pixels A and B are restored as matching with the G representative value.
- the same processing is performed using the ⁇ comparison data and the size recognition data in restoring the gradation values of the B subpixels of the pixels A and B.
- the compression ratio is 50%, there is no ⁇ comparison data and size recognition data for the B subpixels of the pixels A and B, and therefore the B of the pixels A and B is independent of the ⁇ comparison data and the size recognition data. All subpixel values are restored as matching the B representative value.
- the same process as the decompression process of the (1 ⁇ 4) compressed data described above is performed.
- the compression ratio is 50%
- a 4-bit bit is used for each of the R C , G C , B C data, and R D , G D , B D data.
- a carry process is performed.
- the error data ⁇ is subtracted, whereby the gradation values of the R subpixel, G subpixel, and B subpixel of the pixels C and D are restored.
- R C , B C data, and R D , B D data are each subjected to 3-bit bit advance processing, and each of G C and G D data 2 bits are carried forward. Further, the error data ⁇ is subtracted, whereby the gradation values of the R subpixel, G subpixel, and B subpixel of the pixels C and D are restored.
- FIGS. 13A and 13B are conceptual diagrams showing the format of (2 ⁇ 2) compressed data.
- (2 ⁇ 2) pixel compression is used when there is a high correlation between the image data of two pixels and a high correlation between the image data of the other two pixels. Compression method.
- the format of compressed data is shown.
- the basic format is the same regardless of the compression ratio, except that the overall bit number and the bit number distribution are different.
- the (2 ⁇ 2) compressed data includes compression type recognition bits, shape recognition data, R representative value # 1, G representative value # 1, B representative value # 1, and R representative value #. 2, G representative value # 2, B representative value # 2, magnitude recognition data, and ⁇ comparison result data.
- the compression type recognition bit is data indicating the type of compression method used for compression.
- 2 ⁇ 2) compressed data 3 bits are assigned to the compression type recognition bit.
- the value of the compression type recognition bit of (2 ⁇ 2) compressed data is “110”.
- the shape recognition data is 2-bit data indicating which two pixels of the pixels A to D are highly correlated.
- (2 ⁇ 2) pixel compression is used, among the pixels A to D, there is a high correlation between the image data of the two pixels and a high correlation between the image data of the other two pixels. is there. Therefore, there are the following three combinations of two pixels having high correlation of image data: ⁇ High correlation between pixels A and B, high correlation between pixels C and D ⁇ High correlation between pixels A and C, high correlation between pixels B and D ⁇ High correlation between pixels A and D
- the shape recognition data having a high correlation between the pixels B and C indicates which of these three combinations is indicated by 2 bits.
- R representative value # 1, G representative value # 1, and B representative value # 1 are values representative of the gradation values of one of the R subpixel, G subpixel, and B subpixel, respectively.
- the value # 2, the G representative value # 2, and the B representative value # 2 are values representing the gradation values of the other two R subpixels, G subpixels, and B subpixels, respectively.
- the G representative value # 2 is 6-bit or 7-bit data.
- R representative value # 1, G representative value # 1, B representative value # 1, R representative value # 2, and G representative value # 2 are 8 bits or 9 bits.
- the B representative value # 2 is data of 7 or 8 bits.
- ⁇ comparison data refers to a difference in gradation values of R subpixels of two pixels having high correlation, a difference in image data of G subpixels of the two pixels having high correlation, and a B sub of the two pixels. This is data indicating whether or not the difference in pixel image data is greater than a predetermined threshold value ⁇ .
- ⁇ comparison data of (2 ⁇ 2) compressed data is 6-bit data in which 3 bits are assigned to each of two pairs of two pixels.
- the size recognition data corresponding to the R sub-pixel is generated only when the difference between the gradation values of the R sub-pixels of two pixels having high correlation is larger than the threshold ⁇
- the size recognition data corresponding to the G sub-pixel is
- the magnitude recognition data corresponding to the B subpixel is generated only when the difference between the gradation values of the G subpixels of the two pixels having high correlation is larger than the threshold ⁇ , and It is generated only when the difference between the gradation values of the subpixels is larger than the threshold value ⁇ . Therefore, the size recognition data of (2 ⁇ 2) compressed data is 0 to 6 bit data.
- FIG. 14A shows (2 ⁇ 2) compressed data when the compression rate is 50%, the correlation between the image data of the pixels A and B is high, and the correlation between the image data of the pixels C and D is high. Describes the generation of. Those skilled in the art will readily understand that (2 ⁇ 2) compressed data can be generated in the same manner when the compression rate is 66.7% and when the correlation between pixels is different.
- the average value of the gradation values is calculated for each of the R subpixel, the G subpixel, and the B subpixel.
- , and the difference between the gradation values of the B sub pixels It is compared whether or not
- , and the gradation value of the B subpixel It is compared whether or not the difference
- size recognition data is created for each of the combination of pixels A and B and the combination of pixels C and D.
- the gradation values of the R subpixels of the pixels A and B are 50 and 59, respectively, and the threshold value ⁇ is 4.
- of the gradation value is larger than the threshold value ⁇ , this is described in the ⁇ comparison data, and the gradation value of the R sub-pixel of the pixel B is the R value of the pixel A.
- the gradation values of the G subpixels of the pixels A and B are 2 and 1, respectively.
- the gradation values of the G subpixels of the pixels A and B are 30 and 39, respectively.
- is larger than the threshold value ⁇
- this fact is described in the ⁇ comparison data, and the gradation value of the B subpixel of the pixel B is equal to that of the pixel A.
- the fact that it is larger than the gradation value of the subpixel is described in the size recognition data.
- the gradation values of the R subpixels of the pixels C and D are both 100. In this case, since the difference
- the magnitude recognition data does not describe the magnitude relation between the gradation values of the G subpixels of the pixels A and B.
- the gradation values of the G subpixels of the pixels C and D are 80 and 85, respectively. In this case, the gradation value difference
- the gradation values of the B subpixels of the pixels C and D are 8, 2 respectively.
- is larger than the threshold value ⁇ , this is described in the ⁇ comparison data, and the gradation value of the B sub-pixel of the pixel C is the B value of the pixel D.
- the gradation value of the B sub-pixel of the pixel C is the B value of the pixel D.
- the error data ⁇ is added to the average values Rave2, Gave2, and Bave2 of the gradation values.
- the error data ⁇ is determined from the coordinates of two pixels in each combination using a basic matrix that is a Bayer matrix. The calculation of the error data ⁇ will be described later separately. In the following description, in the present embodiment, the error data ⁇ determined for the pixels A and B is assumed to be zero.
- rounding processing and bit truncation processing are performed to calculate R representative value # 1, G representative value # 1, B representative value # 1, R representative value # 2, G representative value # 2, and B representative value # 2.
- the rounding process and the bit truncation process are performed according to the compression rate.
- the compression rate is 50%
- the numerical value added in the rounding process and the number of bits rounded down in the bit truncation process are the difference in gradation values
- ⁇ Depending on the magnitude relationship between G B
- the lower 3 after adding the value 4 to the average value Rave1 of the R sub-pixel gradation value A process of truncating the bits is performed, whereby the R representative value # 1 is calculated. Otherwise, the process of adding the value 2 to the average value Rave1 and then truncating the lower 2 bits is performed, thereby calculating the R representative value # 1. As a result, the R representative value # 1 becomes 5 bits or 6 bits. The same applies to the G subpixel and the B subpixel.
- the rounding process and the bit truncation process are not performed for any of the R subpixel, the G subpixel, and the B subpixel of the pixels A and B.
- the average values Rave1, Gave1, and Bave1 of the gradation values of the R subpixel, the G subpixel, and the B subpixel are directly calculated as the R representative value # 1, the G representative value # 1, and the B representative value # 1.
- FIG. 14B is a diagram illustrating a decompression method of compressed image data compressed by (2 ⁇ 2) pixel compression.
- FIG. 14B shows a case where the compression rate is 50%, the correlation between the image data of the pixels A and B is high, and the correlation between the image data of the pixels C and D is high (2 ⁇ 2). Describes decompression of compressed data.
- (2 ⁇ 2) compressed data can be developed in the same manner when the compression rate is 66.7% and when the correlation between pixels is different.
- bit advance processing is performed on R representative value # 1, G representative value # 1, and B representative value # 1.
- the number of bits in the bit advance processing is the difference between the gradation value differences
- the same bit carry processing is performed for the R representative value # 2, the G representative value # 2, and the B representative value # 2.
- the number of bits for the bit carry-over processing of the G representative value # 2 is selected from 1 bit or 2 bits.
- between the gradation values of the G subpixels of the pixels C and D is larger than the threshold value ⁇
- a 2-bit bit carry-over process is performed on the G representative value # 2, otherwise A 1-bit bit advance process is performed.
- a process of raising 2 bits is performed for the R representative value # 2
- a process of raising 2 bits is performed for the G representative value # 2
- 3 bits are performed for the B representative value # 2. Bit advance processing is performed.
- R representative value # 1, G representative value # 1, B representative value # 1, R representative value # 2, G representative value # 2, B After the error data ⁇ is subtracted from each of the representative values # 2, the pixel A, Processing for restoring the gradation values of the R, G, and B subpixels of B and the gradation values of the R, G, and B subpixels of the pixels C and D is performed.
- ⁇ comparison data and size recognition data are used.
- ⁇ comparison data when it is described that the difference
- the value obtained by subtracting the constant value 5 from the R representative value # 1 is restored as the gradation value of the R sub-pixel that is described as being larger in the size recognition data among the pixels A and B. It is restored as the gradation value of the R subpixel which is described as being smaller in the data.
- the gradation value of the R subpixels of the pixels A and B matches the R representative value # 1. Will be restored. Similarly, the gradation values of the G subpixels and B subpixels of the pixels A and B and the gradation values of the R subpixel, G subpixel, and B subpixel of the pixels C and D are restored by the same procedure.
- the gradation value of the R subpixel of the pixel A is restored as a value obtained by subtracting the value 5 from the R representative value # 1
- the gradation value of the R subpixel of the pixel B is R representative value #. It is restored as a value obtained by adding 1 to the value 5.
- the gradation values of the G subpixels of the pixels A and B are restored as values that match the G representative value # 1.
- the gradation value of the B subpixel of the pixel A is restored as a value obtained by subtracting the value 5 from the B representative value # 1
- the gradation value of the B subpixel of the pixel B is changed from the B representative value # 1 to the value 5. It is restored as an added value.
- the gradation values of the R subpixels of the pixels C and D are restored as values that match the B representative value # 2. Further, the gradation value of the G sub-pixel of the pixel C is restored as a value obtained by subtracting the value 5 from the G representative value # 2, and the gradation value of the G sub-pixel of the pixel D is restored from the G representative value # 2 to the value 5 It has been restored as a value added. Further, the gradation value of the B subpixel of the pixel C is restored as a value by adding the value 5 from the G representative value # 2, and the gradation value of the B subpixel of the pixel D is restored from the G representative value # 2 to the value 5 It is restored as a value obtained by subtracting.
- the restoration of the gradation values of the R subpixel, G subpixel, and B subpixel of the pixels A to D is completed. Comparing the image data of the pixels A to D in the right column of FIG. 14B with the image data of the pixels A to D in the left column of FIG. 14A, the original image of the pixels A to D is generally obtained by the above expansion method. It will be understood that the data has been restored.
- FIGS. 15A and 15B are conceptual diagrams showing the format of (4 ⁇ 1) compressed data.
- (4 ⁇ 1) pixel compression is a compression method used when there is a high correlation between the image data of the four pixels of the target block.
- the format of compressed data is shown.
- the basic format is the same regardless of the compression ratio, except that the overall bit number and the bit number distribution are different.
- (4 ⁇ 1) compressed data includes a compression type recognition bit, the following seven data: Ymin, Ydist0 to Ydist2, address data, Cb ′ , Cr ′, and when the compression rate is 66.7%, it further includes 1-bit padding data.
- the compression type recognition bit is data indicating the type of compression method used for compression, and in this embodiment, 4 bits are assigned to the compression type recognition bit.
- Ymin, Ydist0 to Ydist2, address data, Cb ′ and Cr ′ are data obtained by converting the image data of the four pixels of the target block from RGB data to YUV data, and further compressing the YUV data. is there.
- Ymin, Ydist0 to Ydist2 are data obtained from the luminance data among the YUV data of the four pixels of the target block
- Cb ′ and Cr ′ are data obtained from the color difference data.
- Ymin, Ydist0 to Ydist2, and Cb ′ and Cr ′ are representative values of the image data of the four pixels of the target block.
- the compression rate is 50%, as shown in FIG.
- the data Ymin has 10 bits
- Ydist0 to Ydist4 have 4 bits
- the address data has 2 bits
- Cb ′ and Cr ′ have 10 bits. Bits are assigned.
- the data Ymin is 12 bits
- Ydist0 to Ydist2 is 7 bits
- the address data is 2 bits
- Cb ′, Cr ′ Are assigned 12 bits
- padding data is assigned 1 bit.
- Padding data is data for adjusting the number of bits of compressed data.
- luminance data Y and color difference data Cr and Cb are calculated by the following matrix calculation:
- Y k is luminance data of the pixel k
- Cr k and Cb k are color difference data of the pixel k.
- R k , G k , and B k are gradation values of the R subpixel, the G subpixel, and the B subpixel of the pixel k, respectively.
- Ymin, Ydist0 to Ydist2, address data, Cb ′ and Cr ′ are created from the luminance data Y k and color difference data Cr k and Cb k of the pixels A to D.
- Ymin is defined as the minimum one of the luminance data Y A to Y D (minimum luminance data).
- Ydist0 to Ydist2 are generated by performing a 2-bit truncation process on the difference between the remaining luminance data and the minimum luminance data Ymin.
- the address data is generated as data indicating which luminance data of the pixels A to D is the minimum. In the example of FIG.
- “>> 2” is an operator indicating 2-bit truncation processing.
- the address data is described that luminance data Y D is the minimum.
- Cr ′ is generated by performing a 1-bit truncation process on the sum of Cr A to Cr D
- Cb ′ is generated by performing a 1-bit truncation process on the sum of Cb A to Cb D.
- “>> 1” is an operator indicating a 1-bit truncation process. This completes the generation of (4 ⁇ 1) pixel compressed data.
- FIG. 16B is a diagram showing a method of generating (4 ⁇ 1) compressed data by expanding (4 ⁇ 1) compressed data.
- the luminance data of each of the pixels A to D is restored from Ymin and Ydist0 to Ydist2.
- the restored luminance data of the pixels A to D will be referred to as Y A ′ to Y D ′.
- the value of the minimum luminance data Ymin is used as the luminance data of the pixel indicated as minimum by the address data.
- the luminance data of other pixels is restored by adding to the minimum luminance data Ymin.
- the gradation values of the R, G, and B subpixels of the pixels A to D are restored from the luminance data Y A ′ to Y D ′ and the color difference data Cr ′ and Cb ′ by the following matrix calculation:
- “>> 2” is an operator indicating a process of truncating 2 bits.
- the color difference data Cr ′ and Cb ′ are commonly used in the restoration of the gradation values of the R, G, and B subpixels of the pixels A to D.
- the error data ⁇ used for the bit plane reduction processing performed for each pixel performed in (1 ⁇ 4) pixel compression and (2 + 1 ⁇ 2) pixel compression is the basic matrix shown in FIG. And calculated from the coordinates of each pixel.
- the basic matrix is a matrix in which the relationship between the lower 2 bits x1 and x0 of the x coordinate of the pixel and the lower 2 bits y1 and y0 of the y coordinate and the basic value Q of the error data ⁇ is described.
- the basic value Q is a value used as a seed for calculating the error data ⁇ .
- the basic value Q is extracted from the matrix elements of the basic matrix based on the lower 2 bits x1, x0 of the x coordinate of the target pixel and the lower 2 bits y1, y0 of the y coordinate. For example, when the target of the bit plane reduction process is the pixel A and the lower 2 bits of the coordinates of the pixel A are “00”, “15” is extracted as the basic value Q.
- the error data ⁇ used for calculating the representative value of the image data of two pixels having high correlation in the (2 + 1 ⁇ 2) pixel compression and the (2 ⁇ 2) pixel compression is shown in FIG.
- the lower 2nd bit x1 and y1 of the x coordinate and y coordinate of the target two pixels is determined as a pixel used for extraction of the basic value Q according to a combination of two target pixels included in the target block.
- a pixel used for extraction of the basic value Q is described as a Q extraction pixel.
- the relationship between the combination of two target pixels and the Q extraction pixel is as follows: When the two target pixels are pixels A and B: The Q extraction pixel is pixel A When the two target pixels are pixels A and C: The Q extraction pixel is pixel A When the two target pixels are pixels A and D: The Q extraction pixel is pixel A -When the two target pixels are pixels B and C: The Q extraction pixel is pixel B -When the two target pixels are pixels B and D: Q extraction pixel is pixel B -When the two target pixels are pixels C and D: Q extraction pixel is pixel B -When the two target pixels are pixels C and D: Q extraction pixel is pixel B
- the basic value Q corresponding to the Q extraction pixel is extracted from the basic matrix in accordance with the x coordinate of the two target pixels and the lower second bits x1 and y1 of the y coordinate.
- the Q extraction pixel is the pixel A.
- the basic value Q to be finally used is determined as follows according to x1 and y1.
- Q 13.
- the calculation method of the error data ⁇ is not limited to the above.
- another matrix which is a Bayer matrix can be used as the basic matrix.
- the target block is defined as pixels of 1 row and 4 columns.
- the target block may be defined as 4 pixels having an arbitrary arrangement.
- the target block may be defined as a pixel with 2 rows and 2 columns. Even in this case, if the pixels A, B, C, and D are defined as shown in FIG. 18, the same processing as described above can be performed.
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Abstract
Description
図1は、本発明の第1の実施形態の表示装置の構成を示すブロック図である。本実施形態では、本発明の表示装置が、液晶表示装置1に適用されている。以下では、本発明が液晶表示装置1に適用された実施形態が説明されるが、本発明が他の表示装置(例えば、PDP(plasma display panel)表示装置、有機EL(electroluminescence)表示装置等)にも適用可能であることは当業者には明らかであろう。
図4は、本発明の第2の実施形態の表示装置の構成を示すブロック図である。本実施形態では、ドライバ4において、シリアル信号線6によってドライバ4に伝送されるシリアルデータ信号からクロック再生を行うアーキテクチャが採用される。本実施形態では、クロック信号線7は設けられない。シリアルデータ信号からクロック再生を行うアーキテクチャは、タイミング制御回路3とドライバ4とを接続するケーブルの信号線の数を低減させるために有効である。このようなアーキテクチャに対応したシリアルデータ転送方式としては、例えば、LVDS(low voltage differential signaling)があげられる。
図5は、本発明の第3の実施形態の表示装置を示すブロック図である。本実施形態では、本発明の表示装置が、液晶表示装置1を含む画像処理装置50に適用されている。画像処理装置50は、グラフィック処理を行う処理装置51と、メモリ52と、外部入力インターフェース53とを備えている。処理装置51としては、例えばCPU(central processing unit)やDSP(digital signal
processor)が用いられる。処理装置51は、メモリ52をワークエリアとして用いながらグラフィック処理を行う。外部入力インターフェース53は、光ディスクドライブのような外部装置に接続される。本実施形態では、外部入力インターフェース53が圧縮回路53aを備えており、外部入力インターフェース53が外部装置から受け取った画像データに対して圧縮処理を行う。圧縮回路53aの動作は、第1の実施形態及び第2の実施形態の圧縮回路11と同じである。圧縮回路53aには、フレームレートを指定するフレームレート指定データが供給され、フレームレート指定データに応じて選択された圧縮率で画像データに対して圧縮処理を行う。圧縮処理によって生成されたデータは、バス54を介してタイミング制御回路3に送られ、更に、シリアルデータ転送によってドライバ4に送られる。
以下では、上述の実施形態において、圧縮回路11において行われる圧縮処理及び展開回路15において行われる展開処理について説明する。
上述のように、本実施形態では、圧縮処理として複数の画素で構成されるブロック毎に圧縮を行うブロック符号化が採用される。より具体的には、本実施形態では、1ブロックが同一の画素ラインに属する4つの画素で構成され、該4つの画素の画像データ(合計96ビット)がまとめて圧縮される。図6は、各ブロックにおける4つの画素の配置を示しており、以下では、各ブロックに含まれる4つの画素を、それぞれ、画素A、画素B、画素C、画素Dと呼ぶことがある。画素A~Dのそれぞれは、Rサブピクセル、Gサブピクセル、Bサブピクセルを有している。画素AのRサブピクセル、Gサブピクセル、Bサブピクセルは、それぞれ、記号RA、GA、BAによって参照される。画素B~Dについても同様である。本実施形態では、各ブロックの4つの画素のサブピクセルRA、GA、BA、RB、GB、BB、RC、GC、BC、RD、GD、BDは、同一の画素ラインに位置しており、同一のゲート線に接続されている。以下の説明においては、圧縮処理の対象となっているブロックを、対象ブロックと呼ぶことにする。
本実施形態においては、圧縮回路11が、画像データを下記の5つの圧縮方式で圧縮できるように構成されている:
・非圧縮
・(1×4)画素圧縮
・(2+1×2)画素圧縮
・(2×2)画素圧縮
・(4×1)画素圧縮
圧縮率が100%でない場合(即ち、非圧縮以外の圧縮方式が選択される場合)、4つの画素の間の相関に応じて圧縮手法が選択される。より具体的には、圧縮回路11は、対象ブロックの1行4列の4画素の画像データが、下記のいずれの場合に該当するかを判断する:
ケースA:4画素のうちの任意の組み合わせの画素の画像データの間の相関性が低い。
ケースB:2画素の画像データの間に高い相関性があり、かつ、他の2画素の画像データは、先の2画素と相関性が低く、且つ、互いに相関性が低い。
ケースC:4画素の画像データの間に高い相関性がある。
ケースD:2画素の画像データの間に高い相関性があり、かつ、他の2画素の画像データの間に高い相関性がある。
i∈{A,B,C,D}
j∈{A,B,C,D}
i≠j
なるi、jの全ての組み合わせについて下記条件(A)が成立しない場合、圧縮回路11は、ケースAに該当する(即ち、4画素のうちの任意の組み合わせの画素の画像データの間の相関性が低い)と判断する(ステップS01)。
条件(A):
|Ri―Rj|≦Th1,且つ
|Gi―Gj|≦Th1,且つ
|Bi―Bj|≦Th1,
ケースAに該当する場合、圧縮回路11は、(1×4)画素圧縮を行うと決定する。
条件(B1):
|RA―RB|≦Th2,且つ
|GA―GB|≦Th2,且つ
|BA―BB|≦Th2,且つ
|RC―RD|≦Th2,且つ
|GC―GD|≦Th2,且つ
|BC―BD|≦Th2.
条件(B2):
|RA―RC|≦Th2,且つ
|GA―GC|≦Th2,且つ
|BA―BC|≦Th2,且つ
|RB―RD|≦Th2,且つ
|GB―GD|≦Th2,且つ
|BB―BD|≦Th2.
条件(B3):
|RA―RD|≦Th2,且つ
|GA―GD|≦Th2,且つ
|BA―BD|≦Th2,且つ
|RB―RC|≦Th2,且つ
|GB―GC|≦Th2,且つ
|BB―BC|≦Th2.
条件(C):
max(RA,RB,RC,RD)-min(RA,RB,RC,RD)<Th3,且つ
max(GA,GB,GC,GD)-min(GA,GB,GC,GD)<Th3,且つ
max(BA,BB,BC,BD)-min(BA,BB,BC,BD)<Th3.
続いて、(1×4)画素圧縮、(2+1×2)画素圧縮、(2×2)画素圧縮、(3+1)画素圧縮、(4×1)画素圧縮のそれぞれについて、圧縮方式の詳細及び展開方式の詳細について説明する。
図9A、図9Bは、(1×4)圧縮データのフォーマットを示す概念図である。上述のように、(1×4)画素圧縮は、4画素のうちの任意の組み合わせの画素の画像データの間の相関性が低い場合に採用される圧縮方式である。ここで、図9Aは、圧縮率が50%(=1/2)の場合の圧縮データのフォーマットを示しており、図9Bは、圧縮率が66.7%(=2/3)の場合の圧縮データのフォーマットを示している。全体のビット数とビット数の配分とが相違している点を除けば、圧縮率がいずれの場合でも基本的なフォーマットは同じである。
図11A、図11Bは、(2+1×2)圧縮データのフォーマットを示す概念図である。上述のように、(2+1×2)画素圧縮は、2画素の画像データの間に高い相関性があり、かつ、他の2画素の画像データは、先の2画素と相関性が低く、且つ、互いに相関性が低い場合に採用される。ここで、図11Aは、圧縮率が50%(=1/2)の場合の圧縮データのフォーマットを示しており、図11Bは、圧縮率が66.7%(=2/3)の場合の圧縮データのフォーマットを示している。全体のビット数とビット数の配分とが相違している点を除けば、圧縮率がいずれの場合でも基本的なフォーマットは同じである。
・画素A、C
・画素B、D
・画素A、B
・画素C、D
・画素B、C
・画素A、D
形状認識データは、3ビットによって、画像データの間の相関性が高い2画素が、これらの6つの組み合わせのいずれであるかを示している。
Rave=(RA+RB+1)/2,
Gave=(GA+GB+1)/2,
Bave=(BA+BB+1)/2.
図13A、図13Bは、(2×2)圧縮データのフォーマットを示す概念図である。上述のように、(2×2)画素圧縮は、2画素の画像データの間に高い相関性があり、かつ、他の2画素の画像データの間に高い相関性がある場合に使用される圧縮方式である。ここで、図13Aは、圧縮率が50%(=1/2)の場合の圧縮データのフォーマットを示しており、図13Bは、圧縮率が66.7%(=2/3)の場合の圧縮データのフォーマットを示している。全体のビット数とビット数の配分とが相違している点を除けば、圧縮率がいずれの場合でも基本的なフォーマットは同じである。
・画素A、Bの相関性が高く、画素C、Dの相関性が高い
・画素A、Cの相関性が高く、画素B、Dの相関性が高い
・画素A、Dの相関性が高く、画素B、Cの相関性が高い
形状認識データは、2ビットによって、これらの3つの組み合わせのいずれであるかを
示している。
の平均値が算出される。画素A、BのRサブピクセル、Gサブピクセル、Bサブピクセル
の階調値の平均値Rave1、Gave1、Bave1、及び画素C、DのRサブピクセ
ル、Gサブピクセル、Bサブピクセルの階調値の平均値Rave2、Gave2、Bav
e2は、下記式によって算出される:
Rave1=(RA+RB+1)/2,
Gave1=(GA+GB+1)/2,
Bave1=(BA+BB+1)/2,
Rave2=(RA+RB+1)/2,
Gave2=(GA+GB+1)/2,
Bave1=(BA+BB+1)/2.
代表値#2のそれぞれから誤差データαが減算された後、これらの代表値から、画素A、
BのR、G、Bサブピクセルの階調値、及び画素C、DのR、G、Bサブピクセルの階調
値を復元する処理が行われる。
図15A、図15Bは、(4×1)圧縮データのフォーマットを示す概念図である。上述のように、(4×1)画素圧縮は、対象ブロックの4画素の画像データの間に高い相関性がある場合に使用される圧縮方式である。ここで、図15Aは、圧縮率が50%(=1/2)の場合の圧縮データのフォーマットを示しており、図15Bは、圧縮率が66.7%(=2/3)の場合の圧縮データのフォーマットを示している。全体のビット数とビット数の配分とが相違している点を除けば、圧縮率がいずれの場合でも基本的なフォーマットは同じである。
ここで、Ykは、画素kの輝度データであり、Crk、Cbkは、画素kの色差データである。また、上述の通り、Rk、Gk、Bkは、それぞれ、画素kのRサブピクセル、Gサブピクセル、Bサブピクセルの階調値である。
Ymin=YD=4,
Ydist0=(YA-Ymin)>>2=(48-4)>>2=11,
Ydist1=(YB-Ymin)>>2=(28-4)>>2=6,
Ydist2=(YC-Ymin)>>2=(16-4)>>2=3,
ここで、「>>2」は、2ビットの切捨て処理を示す演算子である。アドレスデータには、輝度データYDが最小である旨が記載される。
Cr’=(CrA+CrB+CrC+CrD)>>1
=(2+1-1+1)>>1=1,
Cb’=(CbA+CbB+CbC+CbD)>>1
=(-2-1+1-1)>>1=-1,
ここで、「>>1」は、1ビットの切捨て処理を示す演算子である。以上で、(4×1)画素圧縮データの生成が完了する。
YA’=Ydist0×4+Ymin=44+4=48,
YB’=Ydist1×4+Ymin=24+4=28,
YC’=Ydist2×4+Ymin=12+4=16,
YD’=Ymin=4.
ス演算により、画素A~DのR、G、Bサブピクセルの階調値が復元される:
ここで、「>>2」は、2ビットを切り捨てる処理を示す演算子である。上記の式から理解されるように、画素A~DのR、G、Bサブピクセルの階調値の復元では、色差データCr’、Cb’が共通に使用される。
以下では、(1×4)画素圧縮、(2+1×2)画素圧縮、(2×2)画素圧縮で使用される誤差データαの算出について説明する。
α=Q×2, (ビット切捨て処理のビット数が5)
α=Q, (ビット切捨て処理のビット数が4)
α=Q/2. (ビット切捨て処理のビット数が3)
・対象の2画素が画素A、Bの場合:Q抽出画素は画素A
・対象の2画素が画素A、Cの場合:Q抽出画素は画素A
・対象の2画素が画素A、Dの場合:Q抽出画素は画素A
・対象の2画素が画素B、Cの場合:Q抽出画素は画素B
・対象の2画素が画素B、Dの場合:Q抽出画素は画素B
・対象の2画素が画素C、Dの場合:Q抽出画素は画素B
Q=15, (x1=y1=「0」)
Q=01, (x1=「1」,y1=「0」)
Q=07, (x1=「0」,y1=「1」)
Q=13. (x1=y1=「1」)
α=Q/2, (ビット切捨て処理のビット数が3)
α=Q/4, (ビット切捨て処理のビット数が2)
α=Q/8. (ビット切捨て処理のビット数が1)
Q=13,
α=13/2=6.
2:液晶表示パネル
3:タイミング制御回路
4:ドライバ
5:ゲート線駆動回路
6:シリアル信号線
7:クロック信号線
11:圧縮回路
12:シリアル送信回路
13:PLL回路
14、14A:シリアル受信回路
15:展開回路
16:表示ラッチ部
17:データ線駆動回路
18:PLL回路
21:位相比較器
22:VCO
23、123:分周器
123a:分周比変更回路
31:形状認識部
32:(1×4)画素圧縮部
33:(2+1×2)画素圧縮部
34:(2×2)画素圧縮部
35:(4×1)画素圧縮部
36:圧縮データ選択部
41:形状認識部
42:(1×4)画素展開部
43:(2+1×2)画素展開部
44:(2×2)画素展開部
45:(4×1)画素展開部
50:画像処理装置
51:処理装置
52:メモリ
53:外部入力インターフェース
53a:圧縮回路
54:バス
Claims (9)
- 表示デバイスと、
前記表示デバイスを駆動する表示デバイスドライバと、
画像データに対する圧縮処理により圧縮データを生成する動作に対応した圧縮部と、
前記圧縮部から前記圧縮データを受け取った場合に前記圧縮データを前記表示デバイスドライバにシリアルデータ信号によって送信する送信部
とを具備し、
前記圧縮部は、前記表示デバイスドライバが前記表示デバイスを駆動するフレームレートに応じて選択された圧縮率で前記圧縮処理を行い、
前記表示デバイスドライバは、前記送信部から前記シリアルデータ信号を受け取り、前記シリアルデータ信号によって送信された前記圧縮データを展開して展開データを生成し、前記展開データに応答して前記表示デバイスを駆動し、
前記圧縮率は、前記シリアルデータ信号の前記送信部から前記表示デバイスドライバへの転送速度が、前記フレームレートに関わらず一定になるように設定される
表示装置。 - 請求項1に記載の表示装置であって、
前記圧縮率が、前記画像データのビット数に対する前記圧縮データのビット数の比である場合に、前記圧縮率は、前記圧縮率と前記フレームレートの積が前記フレームレートに関わらず一定になるように設定される
表示装置。 - 請求項1又は2に記載の表示装置であって、
前記圧縮部は、前記画像データを圧縮せずに非圧縮データとして出力する動作に対応しており、
前記送信部は、前記圧縮部から前記非圧縮データを受け取った場合、前記非圧縮データを前記表示デバイスドライバに前記シリアルデータ信号によって送信し、
前記非圧縮データを前記シリアルデータ信号によって前記送信部から前記表示デバイスドライバへ送信する場合の転送速度は、前記圧縮データを前記シリアルデータ信号によって前記送信部から前記表示デバイスドライバへ送信する場合の転送速度と同一である
表示装置。 - 請求項1乃至3のいずれかに記載の表示装置であって、
前記送信部は、
原発クロック信号に同期した第1同期用クロック信号を生成するPLL(phase locked loop)又はDLL(delay locked loop)として構成された第1クロック生成回路と、
前記第1クロック生成回路から受け取った同期用クロック信号に同期して前記シリアルデータ信号を送信するシリアル送信回路
とを備え、
前記第1クロック生成回路は、前記フレームレートの切り替えが発生しても、前記同期用クロック信号の周波数の切り替えを行わないように構成された
表示装置。 - 請求項3又は4に記載の表示装置であって、
前記表示デバイスドライバは、前記シリアルデータ信号を受信する受信部を備え、
前記受信部は、
前記シリアルデータ信号に同期した第2同期用クロック信号を生成するPLL(phase locked loop)又はDLL(delay locked loop)として構成された第2クロック生成回路と、
前記第2クロック生成回路から受け取った第2同期用クロック信号に同期して前記シリアルデータ信号に対してサンプリングして前記圧縮データを得るシリアル受信回路を具備する
表示装置。 - 請求項3乃至5のいずれかに記載の表示装置であって、
前記第1クロック生成回路は、
前記第1同期用クロック信号を受け取り、前記第1同期用クロック信号の周波数と同一又はそれより低い分周クロック信号を出力する分周部と、
前記原発クロック信号と前記分周クロック信号との位相差に応じた出力信号を生成する位相比較回路と、
前記位相比較回路から受け取った前記出力信号に応答して、前記第1同期クロック信号の周波数を制御しながら前記第1同期クロック信号を出力するクロック出力回路
とを備え、
前記分周部は、前記分周クロック信号の周波数と前記第1同期クロック信号の周波数の比が固定であるように構成された
表示装置。 - 表示デバイスを駆動する表示デバイスドライバを制御する表示装置制御回路であって、
画像データに対する圧縮処理により圧縮データを生成する動作に対応した圧縮部と、
前記圧縮部から前記圧縮データを受け取った場合に前記圧縮データを前記表示デバイスドライバにシリアルデータ信号によって送信する送信部
とを具備し、
前記圧縮部は、前記表示デバイスドライバが前記表示デバイスを駆動するフレームレートに応じて選択された圧縮率で前記圧縮処理を行い、
前記表示デバイスドライバは、前記送信部から前記シリアルデータ信号を受け取り、前記シリアルデータ信号によって送信された前記圧縮データを展開して展開データを生成し、前記展開データに応答して前記表示デバイスを駆動し、
前記圧縮率は、前記シリアルデータ信号の前記送信部から前記表示デバイスドライバへの転送速度が、前記フレームレートに関わらず一定になるように設定される
表示装置制御回路。 - 請求項7に記載の表示装置制御回路であって、
前記圧縮率が、前記画像データのビット数に対する前記圧縮データのビット数の比である場合に、前記圧縮率は、前記圧縮率と前記フレームレートの積が前記フレームレートに関わらず一定になるように設定される
表示装置制御回路。 - 請求項7又は8のいずれかに記載の表示装置制御回路であって、
前記送信部は、
原発クロック信号に同期した第1同期用クロック信号を生成するPLL(phase locked loop)又はDLL(delay locked loop)として構成された第1クロック生成回路と、
前記第1クロック生成回路から受け取った同期用クロック信号に同期して前記シリアルデータ信号を送信するシリアル送信回路
とを備え、
前記第1クロック生成回路は、前記フレームレートの切り替えが発生しても、前記同期用クロック信号の周波数の切り替えを行わないように構成された
表示装置制御回路。
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- 2012-02-20 WO PCT/JP2012/053942 patent/WO2012132624A1/ja active Application Filing
- 2012-02-20 CN CN201280016020.7A patent/CN103443843B/zh not_active Expired - Fee Related
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US11132940B2 (en) | 2019-03-28 | 2021-09-28 | Macroblock, Inc. | Display system and driving circuit thereof |
Also Published As
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JPWO2012132624A1 (ja) | 2014-07-24 |
CN103443843A (zh) | 2013-12-11 |
CN103443843B (zh) | 2016-08-17 |
US9959796B2 (en) | 2018-05-01 |
US9691339B2 (en) | 2017-06-27 |
US20140022221A1 (en) | 2014-01-23 |
US20170249881A1 (en) | 2017-08-31 |
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