WO2012126155A1 - 一种半导体器件及其制造方法 - Google Patents
一种半导体器件及其制造方法 Download PDFInfo
- Publication number
- WO2012126155A1 WO2012126155A1 PCT/CN2011/001292 CN2011001292W WO2012126155A1 WO 2012126155 A1 WO2012126155 A1 WO 2012126155A1 CN 2011001292 W CN2011001292 W CN 2011001292W WO 2012126155 A1 WO2012126155 A1 WO 2012126155A1
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- WIPO (PCT)
- Prior art keywords
- layer
- carbon nanotube
- graphene
- silicon
- semiconductor
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 84
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 42
- 239000002041 carbon nanotube Substances 0.000 claims abstract description 37
- 229910021393 carbon nanotube Inorganic materials 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 239000011521 glass Substances 0.000 claims description 6
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- 125000006850 spacer group Chemical group 0.000 claims description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 98
- 239000000203 mixture Substances 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910002804 graphite Inorganic materials 0.000 description 2
- 239000010439 graphite Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000002071 nanotube Substances 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000011852 carbon nanoparticle Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1606—Graphene
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
- H10K10/486—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions the channel region comprising two or more active layers, e.g. forming pn heterojunctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
- H10K85/221—Carbon nanotubes
Definitions
- the present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method of fabricating the same. Background technique
- the present invention provides a method of fabricating a semiconductor device, the method comprising: providing a substrate on which a graphene layer or a carbon nanotube layer is formed; in the graphene layer or carbon After the gate structure is formed on the nanotube layer, a portion of the graphene layer or the carbon nanotube layer is exposed, the gate structure includes a gate stack, a sidewall spacer and a cap layer, and the cap layer is located on the gate stack a side wall surrounding the gate stack and the cap layer; epitaxially growing a semiconductor layer on the exposed graphene layer or carbon nanotube layer; forming a metal contact layer on the semiconductor layer.
- the present invention also provides a semiconductor device, the device comprising: a substrate; a graphene layer or a carbon nanotube layer, the graphene layer or the carbon nanotube layer being formed on the substrate;
- the gate structure is formed on the graphene layer or the carbon nanotube layer, and exposes a portion of the graphene layer or the carbon nanotube layer; a metal contact layer surrounding the gate structure, And located on the exposed graphene layer or carbon nanotube layer.
- a method of fabricating a semiconductor device provided by the present invention by using a graphene layer or carbon A semiconductor layer is formed on the nanotube layer, and then a metal contact layer is formed on the semiconductor layer instead of directly forming a metal contact layer using the graphene layer or the carbon nanotube layer material, thereby facilitating formation of a self-aligned source-drain contact plug.
- FIG. 1 is a flow chart showing an embodiment of a method of fabricating a semiconductor device in accordance with the present invention; a cross-sectional view of an intermediate structure. ⁇ , , ⁇ ⁇
- the embodiments described below with reference to the drawings are intended to be illustrative of the invention and are not to be construed as limiting.
- the following disclosure provides many different embodiments or examples for implementing different structures of the present invention.
- the components and arrangements of the specific examples are described below. Of course, they are merely examples and are not intended to limit the invention.
- the present invention may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not in itself indicate the relationship between the various embodiments and/or arrangements discussed.
- examples of the various specific processes and materials provided by the present invention will be appreciated by those of ordinary skill in the art in the application of other processes and/or other materials.
- the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first and second features. The embodiment, such that the first and second features may not be in direct contact.
- substrate 200 includes one or a combination of a silicon substrate (e.g., a wafer), silicon carbide, bulk silicon, doped or undoped silicon glass. In other embodiments, other basic semiconductors or compound semiconductors such as Ge, GeSi, GaAs, InP or diamond may also be included.
- the substrate 200 can include various doping configurations in accordance with design requirements well known in the art (e.g., p-type or n-type substrates). Additionally, substrate 200 can optionally include an epitaxial layer that can be altered by stress to enhance performance, and can include a silicon-on-insulator (SOI) structure.
- SOI silicon-on-insulator
- a graphene layer or a carbon nanotube layer 202 is formed on the substrate 200, with reference to FIG.
- the graphene layer or carbon nanoparticle including a single layer or a plurality of graphene materials may be formed by CVD, thermal decomposition, micro-mechanical stripping, and their bonding transfer methods or other suitable methods.
- Rice tube layer 202 may be formed by CVD, thermal decomposition, micro-mechanical stripping, and their bonding transfer methods or other suitable methods.
- a gate structure is formed on the graphene layer or the carbon nanotube layer.
- the gate structure includes a gate stack 204 and a sidewall spacer 206 (which may be an insulating material, and may include one or more layers.
- a sidewall spacer 206 which may be an insulating material, and may include one or more layers.
- the structure is a multilayer structure, two adjacent layers The material may be different
- a cap layer which may be an insulating material, the cap material may be the same as the side wall 206 material
- the cap layer being on the gate stack 204, the side wall 206 surrounding the gate stack 204 and the cap Floor.
- the gate stack 204 can carry the cap layer with metal, doped or undoped polysilicon, doped or undoped amorphous silicon, and doped or undoped silicon glass.
- the gate stack 204 may also be a dummy gate stack, which may include a gate dielectric layer (such as silicon oxide or high-k dielectric material) and a gate/pseudo gate (such as metal, doped or undoped polysilicon).
- a gate dielectric layer such as silicon oxide or high-k dielectric material
- a gate/pseudo gate such as metal, doped or undoped polysilicon
- doped or undoped amorphous silicon, and doped or undoped silicon glass may also include only gate/pseudo gates, which can be flexibly selected by those skilled in the art according to the process needs, and only focuses on this document. The effect of material selection of the gate stack 204 on the implementation of the scheme is taught.
- the gate structure is formed on the graphene layer or the carbon nanotube layer, a portion of the graphite germanium layer or the carbon nanotube layer is exposed.
- a semiconductor layer 208 is epitaxially grown on the exposed graphene layer or carbon nanotube layer 202 (the semiconductor layer material may be doped or undoped polysilicon, doped or undoped amorphous silicon, Alternatively, doped or undoped single crystal silicon; in other embodiments, it may be doped or undoped germanium or doped or undoped silicon germanium).
- the semiconductor layer material may be doped or undoped polysilicon, doped or undoped amorphous silicon, Alternatively, doped or undoped single crystal silicon; in other embodiments, it may be doped or undoped germanium or doped or undoped silicon germanium).
- a semiconductor layer 208 may be formed on the exposed graphite germanium layer or carbon nanotube layer 202 by an epitaxial growth process, that is, the semiconductor layer 208 is formed in a self-aligned manner, and further, When the semiconductor layer 208 forms the source and drain regions of the device, the source and drain regions are formed in a self-aligned manner.
- the semiconductor layer material is doped or undoped polysilicon, doped or undoped amorphous silicon, or doped or undoped single crystal silicon.
- a metal contact layer 210 is formed on the semiconductor layer.
- the metal contact layer 210 may be formed by a conventional self-alignment process. Specifically, a metal layer is first formed on the semiconductor layer, such as Ti, Ni, Co, or other metal material; and then, high temperature annealing is performed to The metal layer reacts with the semiconductor layer 208 in contact with it to form a metal contact layer 210, which may react with all of the semiconductor layer 208 (other embodiments), or may only react with the surface layer of the semiconductor layer 208 (this embodiment); Then, remove unreacted The metal layer is self-aligned to form the metal contact layer 210, see FIG.
- the step of forming the metal contact layer 210 on the semiconductor layer 208 includes: first removing the cap layer to expose the gate stack 204. Then, a metal contact layer 210 is formed on the semiconductor layer 208 and the gate stack 204. At this time, after the epitaxial growth of the semiconductor layer 208, the cap layer is removed, which is advantageous for maintaining the topography of the gate stack 204 and also reducing the number of steps required to form the metal contact layer 210 on the gate stack 204, which is advantageous for the number of steps required for forming the metal contact layer 210 on the gate stack 204. Simplify the process.
- the present invention also provides a semiconductor device, the semiconductor device comprising: a substrate; a graphene layer or a carbon nanotube layer formed on the substrate; formed on the graphene layer or the carbon nanotube layer And exposing a portion of the gate structure of the graphene layer or the carbon nanotube layer, the gate structure including a gate stack and sidewall spacers; formed on the graphene layer or the carbon nanotube layer 202 on both sides of the gate structure Metal contact layer.
- the semiconductor device may further include: a semiconductor layer sandwiched between the metal contact layer and the graphene layer or the carbon nanotube layer.
- the graphene layer or the carbon nanotube layer may comprise a single layer or a multilayer structure.
- the structural composition, material, and formation method of each part in each embodiment of the semiconductor device may be the same as those described in the foregoing method for manufacturing the semiconductor device, and are not described herein.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Nanotechnology (AREA)
- Manufacturing & Machinery (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Thin Film Transistor (AREA)
- Carbon And Carbon Compounds (AREA)
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201190000071.1U CN202633239U (zh) | 2011-03-18 | 2011-08-05 | 一种半导体器件 |
US13/376,237 US20130032777A1 (en) | 2011-03-18 | 2011-08-05 | Semiconductor Device and Manufacturing Method thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110066371.6 | 2011-03-18 | ||
CN201110066371.6A CN102683209B (zh) | 2011-03-18 | 2011-03-18 | 一种半导体器件及其制造方法 |
Publications (1)
Publication Number | Publication Date |
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WO2012126155A1 true WO2012126155A1 (zh) | 2012-09-27 |
Family
ID=46814940
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2011/001292 WO2012126155A1 (zh) | 2011-03-18 | 2011-08-05 | 一种半导体器件及其制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20130032777A1 (zh) |
CN (2) | CN102683209B (zh) |
WO (1) | WO2012126155A1 (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130288464A1 (en) * | 2012-04-25 | 2013-10-31 | Hon Hai Precision Industry Co., Ltd. | Method for making eptaxial structure |
US20130285115A1 (en) * | 2012-04-25 | 2013-10-31 | Hon Hai Precision Industry Co., Ltd. | Eptaxial structure |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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CN104282568B (zh) * | 2013-07-06 | 2018-07-13 | 中国科学院微电子研究所 | 一种半导体结构及其制造方法 |
CN104425365A (zh) * | 2013-09-11 | 2015-03-18 | 中国科学院微电子研究所 | 一种自对准接触工艺 |
KR102134819B1 (ko) | 2013-11-29 | 2020-07-21 | 삼성전자주식회사 | 전자 소자 |
CN104393027B (zh) * | 2014-09-29 | 2017-06-27 | 国家纳米科学中心 | 一种全碳石墨烯器件及其制备方法 |
US10217819B2 (en) * | 2015-05-20 | 2019-02-26 | Samsung Electronics Co., Ltd. | Semiconductor device including metal-2 dimensional material-semiconductor contact |
US10559675B2 (en) | 2017-12-21 | 2020-02-11 | International Business Machines Corporation | Stacked silicon nanotubes |
US11081565B2 (en) * | 2019-08-02 | 2021-08-03 | Micron Technology, Inc. | Memory modules and memory packages including graphene layers for thermal management |
CN110571333B (zh) * | 2019-08-13 | 2023-06-30 | 北京元芯碳基集成电路研究院 | 一种无掺杂晶体管器件制作方法 |
CN113097072B (zh) * | 2021-03-02 | 2022-07-22 | 中国电子科技集团公司第五十五研究所 | 一种采用介质牺牲层工艺制备石墨烯场效应晶体管的方法 |
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US7858990B2 (en) * | 2008-08-29 | 2010-12-28 | Advanced Micro Devices, Inc. | Device and process of forming device with pre-patterned trench and graphene-based device structure formed therein |
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2011
- 2011-03-18 CN CN201110066371.6A patent/CN102683209B/zh active Active
- 2011-08-05 WO PCT/CN2011/001292 patent/WO2012126155A1/zh active Application Filing
- 2011-08-05 CN CN201190000071.1U patent/CN202633239U/zh not_active Expired - Fee Related
- 2011-08-05 US US13/376,237 patent/US20130032777A1/en not_active Abandoned
Patent Citations (4)
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CN101065811A (zh) * | 2004-05-25 | 2007-10-31 | 国际商业机器公司 | 制造隧穿纳米管场效应晶体管的方法 |
JP2008004749A (ja) * | 2006-06-22 | 2008-01-10 | Toshiba Corp | 半導体装置 |
CN101378104A (zh) * | 2008-09-19 | 2009-03-04 | 苏州纳维科技有限公司 | 半导体异质衬底及其生长方法 |
CN101710588A (zh) * | 2009-12-08 | 2010-05-19 | 北京大学 | 一种碳基场效应晶体管的顶栅介质及其制备方法 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130288464A1 (en) * | 2012-04-25 | 2013-10-31 | Hon Hai Precision Industry Co., Ltd. | Method for making eptaxial structure |
US20130285115A1 (en) * | 2012-04-25 | 2013-10-31 | Hon Hai Precision Industry Co., Ltd. | Eptaxial structure |
US9099307B2 (en) * | 2012-04-25 | 2015-08-04 | Tsinghua University | Method for making epitaxial structure |
US9231060B2 (en) * | 2012-04-25 | 2016-01-05 | Tsinghua University | Eptaxial structure |
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CN202633239U (zh) | 2012-12-26 |
US20130032777A1 (en) | 2013-02-07 |
CN102683209B (zh) | 2015-01-21 |
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