WO2012126155A1 - 一种半导体器件及其制造方法 - Google Patents

一种半导体器件及其制造方法 Download PDF

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WO2012126155A1
WO2012126155A1 PCT/CN2011/001292 CN2011001292W WO2012126155A1 WO 2012126155 A1 WO2012126155 A1 WO 2012126155A1 CN 2011001292 W CN2011001292 W CN 2011001292W WO 2012126155 A1 WO2012126155 A1 WO 2012126155A1
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layer
carbon nanotube
graphene
silicon
semiconductor
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French (fr)
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尹海洲
骆志炯
朱慧珑
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US13/376,237 priority Critical patent/US20130032777A1/en
Priority to CN201190000071.1U priority patent/CN202633239U/zh
Publication of WO2012126155A1 publication Critical patent/WO2012126155A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/472—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having lower bandgap active layer formed on top of wider bandgap layer, e.g. inverted HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/881—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being a two-dimensional material
    • H10D62/882—Graphene
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
    • H10K10/462—Insulated gate field-effect transistors [IGFETs]
    • H10K10/484—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions
    • H10K10/486—Insulated gate field-effect transistors [IGFETs] characterised by the channel regions the channel region comprising two or more active layers, e.g. forming pn heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
    • H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
    • H10K85/221—Carbon nanotubes

Definitions

  • the present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method of fabricating the same. Background technique
  • the present invention provides a method of fabricating a semiconductor device, the method comprising: providing a substrate on which a graphene layer or a carbon nanotube layer is formed; in the graphene layer or carbon After the gate structure is formed on the nanotube layer, a portion of the graphene layer or the carbon nanotube layer is exposed, the gate structure includes a gate stack, a sidewall spacer and a cap layer, and the cap layer is located on the gate stack a side wall surrounding the gate stack and the cap layer; epitaxially growing a semiconductor layer on the exposed graphene layer or carbon nanotube layer; forming a metal contact layer on the semiconductor layer.
  • the present invention also provides a semiconductor device, the device comprising: a substrate; a graphene layer or a carbon nanotube layer, the graphene layer or the carbon nanotube layer being formed on the substrate;
  • the gate structure is formed on the graphene layer or the carbon nanotube layer, and exposes a portion of the graphene layer or the carbon nanotube layer; a metal contact layer surrounding the gate structure, And located on the exposed graphene layer or carbon nanotube layer.
  • a method of fabricating a semiconductor device provided by the present invention by using a graphene layer or carbon A semiconductor layer is formed on the nanotube layer, and then a metal contact layer is formed on the semiconductor layer instead of directly forming a metal contact layer using the graphene layer or the carbon nanotube layer material, thereby facilitating formation of a self-aligned source-drain contact plug.
  • FIG. 1 is a flow chart showing an embodiment of a method of fabricating a semiconductor device in accordance with the present invention; a cross-sectional view of an intermediate structure. ⁇ , , ⁇ ⁇
  • the embodiments described below with reference to the drawings are intended to be illustrative of the invention and are not to be construed as limiting.
  • the following disclosure provides many different embodiments or examples for implementing different structures of the present invention.
  • the components and arrangements of the specific examples are described below. Of course, they are merely examples and are not intended to limit the invention.
  • the present invention may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not in itself indicate the relationship between the various embodiments and/or arrangements discussed.
  • examples of the various specific processes and materials provided by the present invention will be appreciated by those of ordinary skill in the art in the application of other processes and/or other materials.
  • the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first and second features. The embodiment, such that the first and second features may not be in direct contact.
  • substrate 200 includes one or a combination of a silicon substrate (e.g., a wafer), silicon carbide, bulk silicon, doped or undoped silicon glass. In other embodiments, other basic semiconductors or compound semiconductors such as Ge, GeSi, GaAs, InP or diamond may also be included.
  • the substrate 200 can include various doping configurations in accordance with design requirements well known in the art (e.g., p-type or n-type substrates). Additionally, substrate 200 can optionally include an epitaxial layer that can be altered by stress to enhance performance, and can include a silicon-on-insulator (SOI) structure.
  • SOI silicon-on-insulator
  • a graphene layer or a carbon nanotube layer 202 is formed on the substrate 200, with reference to FIG.
  • the graphene layer or carbon nanoparticle including a single layer or a plurality of graphene materials may be formed by CVD, thermal decomposition, micro-mechanical stripping, and their bonding transfer methods or other suitable methods.
  • Rice tube layer 202 may be formed by CVD, thermal decomposition, micro-mechanical stripping, and their bonding transfer methods or other suitable methods.
  • a gate structure is formed on the graphene layer or the carbon nanotube layer.
  • the gate structure includes a gate stack 204 and a sidewall spacer 206 (which may be an insulating material, and may include one or more layers.
  • a sidewall spacer 206 which may be an insulating material, and may include one or more layers.
  • the structure is a multilayer structure, two adjacent layers The material may be different
  • a cap layer which may be an insulating material, the cap material may be the same as the side wall 206 material
  • the cap layer being on the gate stack 204, the side wall 206 surrounding the gate stack 204 and the cap Floor.
  • the gate stack 204 can carry the cap layer with metal, doped or undoped polysilicon, doped or undoped amorphous silicon, and doped or undoped silicon glass.
  • the gate stack 204 may also be a dummy gate stack, which may include a gate dielectric layer (such as silicon oxide or high-k dielectric material) and a gate/pseudo gate (such as metal, doped or undoped polysilicon).
  • a gate dielectric layer such as silicon oxide or high-k dielectric material
  • a gate/pseudo gate such as metal, doped or undoped polysilicon
  • doped or undoped amorphous silicon, and doped or undoped silicon glass may also include only gate/pseudo gates, which can be flexibly selected by those skilled in the art according to the process needs, and only focuses on this document. The effect of material selection of the gate stack 204 on the implementation of the scheme is taught.
  • the gate structure is formed on the graphene layer or the carbon nanotube layer, a portion of the graphite germanium layer or the carbon nanotube layer is exposed.
  • a semiconductor layer 208 is epitaxially grown on the exposed graphene layer or carbon nanotube layer 202 (the semiconductor layer material may be doped or undoped polysilicon, doped or undoped amorphous silicon, Alternatively, doped or undoped single crystal silicon; in other embodiments, it may be doped or undoped germanium or doped or undoped silicon germanium).
  • the semiconductor layer material may be doped or undoped polysilicon, doped or undoped amorphous silicon, Alternatively, doped or undoped single crystal silicon; in other embodiments, it may be doped or undoped germanium or doped or undoped silicon germanium).
  • a semiconductor layer 208 may be formed on the exposed graphite germanium layer or carbon nanotube layer 202 by an epitaxial growth process, that is, the semiconductor layer 208 is formed in a self-aligned manner, and further, When the semiconductor layer 208 forms the source and drain regions of the device, the source and drain regions are formed in a self-aligned manner.
  • the semiconductor layer material is doped or undoped polysilicon, doped or undoped amorphous silicon, or doped or undoped single crystal silicon.
  • a metal contact layer 210 is formed on the semiconductor layer.
  • the metal contact layer 210 may be formed by a conventional self-alignment process. Specifically, a metal layer is first formed on the semiconductor layer, such as Ti, Ni, Co, or other metal material; and then, high temperature annealing is performed to The metal layer reacts with the semiconductor layer 208 in contact with it to form a metal contact layer 210, which may react with all of the semiconductor layer 208 (other embodiments), or may only react with the surface layer of the semiconductor layer 208 (this embodiment); Then, remove unreacted The metal layer is self-aligned to form the metal contact layer 210, see FIG.
  • the step of forming the metal contact layer 210 on the semiconductor layer 208 includes: first removing the cap layer to expose the gate stack 204. Then, a metal contact layer 210 is formed on the semiconductor layer 208 and the gate stack 204. At this time, after the epitaxial growth of the semiconductor layer 208, the cap layer is removed, which is advantageous for maintaining the topography of the gate stack 204 and also reducing the number of steps required to form the metal contact layer 210 on the gate stack 204, which is advantageous for the number of steps required for forming the metal contact layer 210 on the gate stack 204. Simplify the process.
  • the present invention also provides a semiconductor device, the semiconductor device comprising: a substrate; a graphene layer or a carbon nanotube layer formed on the substrate; formed on the graphene layer or the carbon nanotube layer And exposing a portion of the gate structure of the graphene layer or the carbon nanotube layer, the gate structure including a gate stack and sidewall spacers; formed on the graphene layer or the carbon nanotube layer 202 on both sides of the gate structure Metal contact layer.
  • the semiconductor device may further include: a semiconductor layer sandwiched between the metal contact layer and the graphene layer or the carbon nanotube layer.
  • the graphene layer or the carbon nanotube layer may comprise a single layer or a multilayer structure.
  • the structural composition, material, and formation method of each part in each embodiment of the semiconductor device may be the same as those described in the foregoing method for manufacturing the semiconductor device, and are not described herein.

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  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
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Description

一种半导体器件及其制造方法 优先权要求
本申请要求了 2011年 3月 18日提交的、申请号为 201 1 10066371.6、 发明名称为 "一种半导体器件及其制造方法" 的中国专利申请的优先 权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及半导体制造技术领域， 特别涉及一种半导体器件及其 制造方法。 背景技术
石墨烯自从被发现以来， 已成为世界各国研究小组的研究热点， 它是碳的一种新形态， 由于其具有一系列独一无二的电学和物理学性 质， 成为构建纳米电子器件的理想材料。 但由于石墨烯为单原子层的 结构， 难以对其进行离子注入掺杂而在其上形成器件的自对准的源漏 接触塞。 发明内容
为了解决上述问题， 本发明提供了一种半导体器件的制造方法， 所述方法包括： 提供衬底， 所述衬底上形成有石墨烯层或碳纳米管层； 在所述石墨烯层或碳纳米管层上形成栅极结构后， 暴露部分所述石墨 烯层或碳纳米管层， 所述栅极结构包括栅堆叠、 侧墙和帽层， 所述帽 层位于所述栅堆叠上， 所述侧墙环绕所述栅堆叠和所述帽层； 在暴露 的所述石墨烯层或碳纳米管层上外延生长半导体层； 在所述半导体层 上形成金属接触层。
此外， 本发明还提供了一种半导体器件， 所述器件包括： 衬底； 石墨烯层或碳纳米管层， 所述石墨烯层或碳纳米管层形成于所述衬底 上； 栅极结构， 所述栅极结构形成于所述石墨烯层或碳纳米管层上， 且暴露部分所述石墨烯层或碳纳米管层； 金属接触层， 所述金属接触 层环绕所述栅极结构， 且位于暴露的所述石墨烯层或碳纳米管层上。
采用本发明提供的半导体器件的制造方法， 通过在石墨烯层或碳 纳米管层上形成半导体层， 继而在所述半导体层上形成金属接触层， 以替代直接利用石墨烯层或碳纳米管层材料形成金属接触层， 利于形 成自对准的源漏接触塞。 附图说明
图 1示出了根据本发明的半导体器件的制造方法实施例的流程图； 中间结构的剖示图。 . σ 、 、 ^ ^
具体实施方式
下面通过参考附图描述的实施例是示例性的， 仅用于解释本发明， 而不能解释为对本发明的限制。 下文的公开提供了许多不同的实施例 或例子用来实现本发明的不同结构。 为了简化本发明的公开， 下文中 对特定例子的部件和设置进行描述。 当然， 它们仅仅为示例， 并且目 的不在于限制本发明。 此外， 本发明可以在不同例子中重复参考数字 和 /或字母。 这种重复是为了简化和清楚的目的， 其本身不指示所讨论 各种实施例和 /或设置之间的关系。 此外， 本发明提供的各种特定的工 艺和材料的例子， 本领域普通技术人员可以意识到其他工艺的可应用 于性和 /或其他材料的使用。 另外， 以下描述的第一特征在第二特征之 "上" 的结构可以包括第一和第二特征形成为直接接触的实施例， 也 可以包括另外的特征形成在第一和第二特征之间的实施例， 这样第一 和第二特征可能不是直接接触。
参考图 1， 在步骤 S01， 提供衬底。 结合图 2， 在一个实施例中， 衬底 200 包括硅衬底 （例如晶片） ， 碳化硅、 体硅、 掺杂或未掺杂的 硅玻璃中的一种或其组合。 在其他实施例中， 还可以包括其他基本半 导体或化合物半导体， 例如 Ge、 GeSi、 GaAs、 InP或金刚石等。 根据 现有技术公知的设计要求 （例如 p型衬底或者 n型衬底） ， 衬底 200 可以包括各种掺杂配置。 此外， 衬底 200 可以可选地包括外延层， 可 以被应力改变以增强性能， 以及可以包括绝缘体上硅（SOI ) 结构。
其中所述衬底 200上形成有石墨烯层或碳纳米管层 202,参考图 2。 可以利用 CVD、 热分解法、 微机械剥离法， 以及它们的键合转移法或 其他合适的方法来形成包括单层或多层石墨烯材料的石墨烯层或碳纳 米管层 202。
在步骤 S02,在所述石墨烯层或碳纳米管层上形成栅极结构。在本 发明一个实施例中，参考图 2,所述栅极结构包括栅堆叠 204、侧墙 206 (可为绝缘材料， 可以包括一层或多层结构， 为多层结构时， 相邻两 层材料可不同） 和帽层 （可为绝缘材料， 所述帽层材料可与侧墙 206 材料相同） ， 所述帽层位于栅堆叠 204上， 侧墙 206环绕所述栅堆叠 204和所述帽层。 在一个实施例中， 栅堆叠 204可以以金属、 掺杂或未 掺杂的多晶硅、 掺杂或未掺杂的非晶硅， 以及掺杂或未掺杂的硅玻璃 承载所述帽层。 本文件中， 所述栅堆叠 204也可以为伪栅堆叠， 可包 括栅介质层 （如氧化硅或高 k介电材料） 和栅极 /伪栅（如金属、 掺杂 或未掺杂的多晶硅、 掺杂或未掺杂的非晶硅， 以及掺杂或未掺杂的硅 玻璃） , 也可只包括栅极 /伪栅， 本领域技术人员可根据工艺需要灵活 选择， 本文件中只着重教导所述栅堆叠 204 的材料选择对方案实施的 影响。
在石墨烯层或碳纳米管层上形成栅极结构后， 暴露部分的石墨浠 层或碳纳米管层。
在步骤 S03 ,在暴露的石墨烯层或碳纳米管层 202上外延生长半导 体层 208 (所述半导体层材料可为掺杂或未掺杂的多晶硅、掺杂或未掺 杂的非晶硅， 或者掺杂或未掺杂的单晶硅； 在其他实施例中， 也可以 为掺杂或未掺杂的锗或掺杂或未掺杂的硅锗） 。 参考图 3 所示， 采用 外延生长工艺可在暴露的石墨浠层或碳纳米管层 202上形成半导体层 208 , 即， 以自对准的方式形成所述半导体层 208， 进而， 在利用所述 半导体层 208 形成器件的源漏区时， 即以自对准的方式形成所述源漏 区。
在一个实施例中， 半导体层材料为掺杂或未摻杂的多晶硅、 掺杂 或未掺杂的非晶硅， 或者， 掺杂或未掺杂的单晶硅。
在步骤 S04, 在所述半导体层上形成金属接触层 210。 可以通过传 统的自对准工艺形成金属接触层 210， 具体来说， 首先在半导体层上形 成金属层， 所述金属层材料例如 Ti、 Ni、 Co或其他金属材料； 而后， 进行高温退火， 使金属层与和其接触的半导体层 208发生反应形成金 属接触层 210，所述金属层可以同全部半导体层 208反应（其他实施例）， 也可以仅同半导体层 208表层反应 （本实施例） ； 而后， 去除未反应 的金属层， 从而自对准形成金属接触层 210, 参考图 4。
此外， 当栅堆叠 204 以掺杂或未掺杂的多晶硅或非晶硅承载帽层 时， 在半导体层 208上形成金属接触层 210的步骤包括： 首先去除帽 层， 以暴露栅堆叠 204。 然后， 在半导体层 208和栅堆叠 204上形成金 属接触层 210。此时，在外延生长所述半导体层 208后，去除所述帽层， 既利于保持栅堆叠 204的形貌， 也利于减少在栅堆叠 204上形成金属 接触层 210时所需步骤的数目， 利于简化工艺。
以本发明还提出了一种半导体器件， 所述半导体器件包括： 衬底； 形成于所述衬底上的石墨烯层或碳纳米管层； 形成于所述石墨烯层或 碳纳米管层上且暴露部分所述石墨烯层或碳纳米管层的栅极结构， 所 述栅极结构包括栅堆叠和侧墙； 形成于所述栅极结构两侧的石墨烯层 或碳纳米管层 202上的金属接触层。
在其他实施例中， 所述半导体器件还可以包括： 半导体层， 所述 半导体层夹于所述金属接触层和所述石墨烯层或碳纳米管层之间。
其中所述石墨烯层或碳纳米管层可包括单层或多层结构。 其中， 对半导体器件各实施例中各部分的结构组成、 材料及形成方法等均可 与前述半导体器件的制造方法实施例中描述的相同， 不在赘述。
虽然关于示例实施例及其优点已经详细说明， 应当理解在不脱离 本发明的精神和所附权利要求限定的保护范围的情况下， 可以对这些 实施例进行各种变化、 替换和修改。 对于其他例子， 本领域的普通技 术人员应当容易理解在保持本发明保护范围内的同时， 工艺步骤的次 序可以变化。
此外， 本发明的应用范围不局限于说明书中描述的特定实施例的 工艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开 内容， 作为本领域的普通技术人员将容易地理解， 对于目前已存在或 者以后即将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步 骤， 其中它们执行与本发明描述的对应实施例大体相同的功能或者获 得大体相同的结果， 依照本发明可以对它们进行应用。 因此， 本发明 所附权利要求旨在将这些工艺、 机构、 制造、 物质组成、 手段、 方法 或步骤包含在其保护范围内。

Claims

权 利 要 求
1. 一种半导体器件的制造方法， 包括：
提供衬底， 所述衬底上形成有石墨烯层或碳纳米管层；
在所述石墨烯层或碳纳米管层上形成栅极结构后， 暴露部分所述 石墨烯层或碳纳米管层， 所述栅极结构包括栅堆叠、 侧墙和帽层， 所 述帽层位于所述栅堆叠上， 所述侧墙环绕所述栅堆叠和所述帽层；
在暴露的所述石墨烯层或碳纳米管层上外延生长半导体层； 在所述半导体层上形成金属接触层。
2. 根据权利要求 1所述的方法， 其特征在于： 所述衬底为碳化硅、 体硅、 摻杂或未掺杂的硅玻璃中的一种或其组合。
3. 根据权利要求 1所述的方法， 其特征在于： 所述栅堆叠以金属、 掺杂或未掺杂的多晶硅、 非晶硅或硅玻璃承载所述帽层。
4. 根据权利要求 1所述的方法， 其特征在于， 所述栅堆叠以掺杂 或未掺杂的多晶硅或非晶硅承载所述帽层时， 在所述半导体层上形成 金属接触层的步骤包括：
去除所述帽层， 以暴露所述栅堆叠；
在所述半导体层和所述栅堆叠上形成金属接触层。
5. 根据权利要求 1所述的方法， 其特征在于， 在所述半导体层上 形成金属接触层的步骤包括：
在所述半导体层上形成金属层；
执行退火操作， 使所述金属层和所述半导体层反应生成所述金属 接触层；
去除未反应的所述金属层。
6. 根据权利要求 1所述的方法， 其特征在于： 所述半导体层材料 为掺杂或未掺杂的多晶硅、 非晶硅、 单晶硅、 锗或硅锗。
7. 一种半导体器件， 包括：
衬底；
石墨烯层或碳纳米管层， 所述石墨烯层或碳纳米管层形成于所述 衬底上；
栅极结构， 所述栅极结构形成于所述石墨烯层或碳纳米管层上， 且暴露部分所述石墨烯层或碳纳米管层； 金属接触层， 所述金属接触层环绕所述栅极结构， 且位于暴露的 所述石墨烯层或碳纳米管层上。
8. 根据权利要求 7所述的半导体器件， 其特征在于， 还包括： 半 导体层， 所述半导体层夹于所述金属接触层和所述石墨烯层或碳纳米 管层之间。
9. 根据权利要求 8所述的半导体器件， 其特征在于： 所述半导体 层材料为掺杂或未掺杂的多晶硅、 非晶硅、 单晶硅、 锗或硅锗。
10. 根据权利要求 7 所述的半导体器件， 其特征在于： 所述衬底 为碳化硅、 体硅、 掺杂或未掺杂的硅玻璃中的一种或其组合。
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