WO2012122787A1 - 金属半导体化合物薄膜的制备方法 - Google Patents

金属半导体化合物薄膜的制备方法 Download PDF

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WO2012122787A1
WO2012122787A1 PCT/CN2011/080264 CN2011080264W WO2012122787A1 WO 2012122787 A1 WO2012122787 A1 WO 2012122787A1 CN 2011080264 W CN2011080264 W CN 2011080264W WO 2012122787 A1 WO2012122787 A1 WO 2012122787A1
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metal
semiconductor substrate
semiconductor compound
compound film
semiconductor
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French (fr)
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吴东平
张世理
朱志炜
张卫
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Fudan University
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Fudan University
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/44—Physical vapour deposition [PVD]

Definitions

  • the present invention relates to the field of microelectronic device technology, and in particular, to a method for preparing a metal semiconductor compound film. Background technique
  • a metal semiconductor compound film as a metal electrode is widely used for a source and a drain of a metal oxide semiconductor field effect transistor (MOSFET) to form a gold-semi-contact with a silicon, germanium or silicon-germanium semiconductor.
  • MOSFET metal oxide semiconductor field effect transistor
  • metal-semiconductor compound film The main role of the metal-semiconductor compound film is to provide reliable contact for the single-tube diode from the beginning. Recently, a self-aligned metal-semiconductor compound thin film formation process (salicide) has been used to form a low-resistance source-drain contact and a low-bar resistance gate electrode for the MOSFET. It plays a very important role in the miniaturization of CMOS device size and the improvement of device performance. With advances in semiconductor fabrication process technology, metal semiconductor compound films have evolved from early titanium silicide (TiSi 2 ), cobalt silicide (CoSi 2 ) to the current mainstream nickel silicide (NiSi) or platinum-doped nickel silicide (Ni(Pt)). Si).
  • TiSi 2 titanium silicide
  • CoSi 2 cobalt silicide
  • NiSi nickel silicide
  • Ni(Pt) platinum-doped nickel silicide
  • the thickness of the metal semiconductor compound film is also required to be thinner and thinner.
  • Conventional methods for preparing a thin film of a metal semiconductor compound e.g., a titanium silicide process, a cobalt silicide process, a nickel silicide process, etc. are disadvantageous for forming an ultrathin metal semiconductor compound film.
  • Patent application “Method for forming ultra-thin controllable metal silicide” (Chinese Patent Application No. CN101764058A) discloses a method for preparing a metal silicide by depositing a metal layer on a silicon substrate, metal After the layer diffuses to the bottom of the silicon village, the remaining metal on the bottom surface of the silicon substrate is removed and annealed, thereby forming a metal silicide on the bottom surface of the silicon village. Since the diffusion of metal to the bottom of the silicon substrate has a diffusion saturation, the diffused metal is limited and is constant, so that the thickness of the metal silicide prepared by the method is very thin (usually 3 to 4 nm), and the thickness is controllable.
  • the metal layer is formed by physical vapor deposition (PVD), and when the metal is deposited, the metal particles generated by the bombardment are not ionized, and the silicon is No bias is applied to the bottom.
  • PVD physical vapor deposition
  • the above method also has the following disadvantages: Since the metal diffused to the silicon substrate at a normal temperature is limited, a thicker metal silicide film cannot be prepared; and in some integrated circuits, the desired metal silicide film is required. The thickness is slightly thicker than the thickness of the metal silicide film obtained by the above method.
  • An object of the present invention is to provide a method for producing a thin film of a metal semiconductor compound to obtain an ultrathin metal semiconductor compound film having a suitable thickness.
  • the present invention provides a method for preparing a thin film of a metal semiconductor compound, the method comprising the steps of:
  • PVD Physical Vapor Deposition
  • the semiconductor substrate is annealed to form a metal semiconductor compound film on the surface of the semiconductor substrate.
  • the metal semiconductor compound film has a thickness of 3 to l lnm.
  • the separating the target portion into an ionic state is achieved by applying a first bias voltage to the target.
  • the first bias voltage is any one of a DC bias voltage, an AC bias voltage, and a pulse bias voltage.
  • the bottom bias is any one of a DC bias, an AC bias, or a pulse bias.
  • the semiconductor substrate is silicon or silicon on an insulating layer, and the metal semiconductor compound film is a metal silicide.
  • the semiconductor substrate is a germanium or an insulating layer
  • the metal semiconductor compound film is a metal germanide
  • the metal semiconductor compound film is formed by reacting a metal with the semiconductor substrate.
  • the metal is any one of nickel, cobalt, titanium, and rhodium, or any one of nickel, cobalt, titanium, and rhodium, and is doped with platinum.
  • tungsten and/or molybdenum are also incorporated into the metal.
  • the temperature of the bottom of the substrate when the metal layer is deposited on the semiconductor substrate is 0 to 300 ° C.
  • the annealing temperature is 200 to 900 °C.
  • the method for preparing a metal semiconductor compound film provided by the present invention can adjust the amount of metal ions entering the semiconductor substrate by adjusting the bias of the substrate bottom, thereby making the thickness of the finally formed metal semiconductor compound film adjustable.
  • FIG. 1 is a flow chart showing the steps of a method for preparing a metal semiconductor compound film according to an embodiment of the present invention
  • FIGS. 2A to 2C are cross-sectional views of the device corresponding to each step of the method for preparing a metal semiconductor compound film according to an embodiment of the present invention. detailed description
  • the core idea of the present invention is to provide a method for preparing a thin film of a metal semiconductor compound, which is formed by separating a target portion into an ion state during the process of depositing a metal layer by PVD.
  • Metal ions, and a substrate bias is applied to the semiconductor substrate, so that the metal ions accelerate toward the semiconductor substrate and enter the semiconductor substrate, thereby causing metal ions to diffuse to the surface of the semiconductor substrate Further, the diffusion depth is deeper, and thus the thickness of the finally formed metal semiconductor compound film is also thickened; and the amount of metal ions diffused to the surface of the semiconductor substrate can be adjusted by adjusting the magnitude of the substrate bias, thereby finally forming The thickness of the metal semiconductor compound film is adjustable.
  • FIG. 1 is a flow chart of steps of a method for preparing a metal semiconductor compound film according to an embodiment of the present invention
  • FIGS. 2A to 2C are metal semiconductor compounds according to an embodiment of the present invention.
  • the method for preparing the metal semiconductor compound film provided by the embodiment of the present invention includes the following steps:
  • the diffusion barrier layer 102 may also be selectively covered, and the diffusion barrier layer 102 may be silicon dioxide, silicon nitride or other insulating dielectric layer;
  • a metal layer 103 on the semiconductor substrate 101 by using a PVD method, as shown in FIG. 2A; the metal in the metal layer 103 is diffused toward the semiconductor substrate 101; wherein, the metal layer 103 is deposited on the PVD
  • the target portion is separated into an ionic state to generate metal ions, and a substrate bias is applied to the semiconductor substrate 101;
  • FIG. 2B A cross-sectional view of the device after the metal layer 103 is as shown in FIG. 2B. After the metal is diffused to the surface of the semiconductor substrate 101, a thin metal layer 104 containing a metal is formed on the surface of the semiconductor substrate 101;
  • the metal semiconductor compound film 105 has a thickness of 3 to ll nm.
  • the separating the target portion into an ionic state is achieved by applying a first bias voltage to the target.
  • the first bias voltage is any one of a DC bias voltage, an AC bias voltage, and a pulse bias voltage.
  • the size of the first bias voltage depends on the PVD system used, that is, the PVD system is different, and the magnitude of the first bias voltage also changes accordingly; generally, the first bias voltage The size is 200V ⁇ 1000V, where for the AC bias and the pulse bias, the above size refers to its effective value.
  • the village bottom bias is any one of a DC bias, an AC bias, or a pulse bias.
  • the magnitude of the bottom bias of the village is adjustable.
  • the magnitude of the bottom bias of the village By adjusting the magnitude of the bottom bias of the village, the number of metal ions diffused to the surface of the semiconductor substrate can be adjusted, so that the finally formed metal semiconductor
  • the thickness of the compound film is adjustable.
  • the magnitude of the village bottom bias is 200V-1000V, wherein for the AC bias and the pulse bias, the above size refers to its effective value.
  • the semiconductor substrate 101 is silicon or silicon on an insulating layer
  • the metal semiconductor compound film 105 is a metal silicide.
  • the semiconductor substrate 101 is germanium or an insulating layer
  • the metal semiconductor compound film 105 is a metal germanide.
  • the substrate bias may be any one of a DC bias, an AC bias, or a pulse bias; when the semiconductor substrate 101 When the silicon or insulating layer is on the insulating layer, since the insulating layer is included, the DC bias does not function, and an AC bias or a pulse bias is required.
  • the semiconductor substrate 101 in the present invention is not limited to the above-exemplified types, and other types of semiconductor substrates, such as a tri-five compound semiconductor substrate, are also within the scope of the present invention.
  • the metal semiconductor compound film 105 is formed by reacting a metal with the semiconductor substrate 101, wherein the metal is any one of nickel, cobalt, titanium, and lanthanum, or nickel, cobalt, titanium, or lanthanum. Any of them is doped with platinum; platinum is doped because pure nickel silicide has poor stability under high temperature conditions, or film thickness becomes uneven and agglomerates, or nickel NiSi 2 with high electrical resistivity is formed.
  • platinum is doped because pure nickel silicide has poor stability under high temperature conditions, or film thickness becomes uneven and agglomerates, or nickel NiSi 2 with high electrical resistivity is formed.
  • a certain proportion of platinum may be doped in nickel; Platinum is similarly explained.
  • the metal is further doped with tungsten and/or molybdenum; to further control the growth of nickel silicide or platinum-doped nickel silicide and the diffusion of nickel/platinum, and increase the stability of nickel silicide or platinum-doped nickel silicide; Tungsten and/or molybdenum in the metal is similarly explained.
  • the metal in the present invention is not limited to the specific metal exemplified above, and other metals capable of reacting with the semiconductor material to produce a thin film of the metal semiconductor compound are within the scope of the present invention.
  • the substrate temperature at the time of depositing the metal layer on the semiconductor substrate is 0 to 300 ° C; this is because for the metal nickel, the deposition temperature exceeding 300 ° C causes the excessive nickel diffusion. Nickel reacts directly with silicon to form nickel silicide, which leads to failure of thickness control. At this specific temperature, nickel diffuses through the silicon surface to the silicon substrate. This diffusion has self-saturation characteristics: nickel diffuses to the silicon substrate only Occurs in a thin layer of silicon to form a thin layer of nickel/nickel atomic proportion. The thickness of the thin layer of nickel is related to the temperature of the substrate at the time of deposition. The higher the temperature, the greater the thickness of the thin layer of nickel. At room temperature, the equivalent nickel thickness of the thin layer of nickel is about 2 nanometers.
  • the annealing temperature is 200 to 900 °C.
  • the present invention provides a method for preparing a thin film of a metal semiconductor compound by separating a target portion into an ionic state during the process of depositing a metal layer by PVD, thereby generating metal ions, and in the semiconductor village.
  • Adding a bottom bias to the bottom causing the metal ions to accelerate toward the semiconductor substrate and enter the semiconductor substrate, so that the metal ions diffused to the surface of the semiconductor substrate are more, and the diffusion depth is deeper. Therefore, the thickness of the finally formed metal semiconductor compound film is also thickened; at the same time, by adjusting the magnitude of the substrate bias, the amount of metal ions diffused to the surface of the semiconductor substrate can be adjusted, thereby making the thickness of the finally formed metal semiconductor compound film. Adjustable.

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Description

金属半导体化合物薄膜的制备方法 技术领域
本发明涉及微电子器件技术领域， 尤其涉及一种金属半导体化合物薄膜的 制备方法。 背景技术
作为金属电极的金属半导体化合物薄膜被广泛用于金属氧化物半导体场效 应晶体管（MOSFET )的源漏极和栅极， 形成和硅、 锗或硅-锗半导体的金 -半接 触。
金属半导体化合物薄膜的主要作用从一开始的为筒单的二极管提供可靠的 接触， 到近来利用自对准金属半导体化合物薄膜形成工艺（salicide )为 MOSFET 形成低阻源漏接触和低方块电阻栅电极，在 CMOS器件尺寸的微缩化及提高器件 性能上起着非常重要的作用。 随着半导体制备工艺技术的进步， 金属半导体化 合物薄膜从早期的硅化钛（TiSi2 )、 硅化钴（CoSi2 )发展到现在主流的的硅化镍 ( NiSi )或掺铂硅化镍 ( Ni(Pt)Si )。
并且随着器件尺寸的缩小， 金属半导体化合物薄膜的厚度也要求越来越薄。 传统的制备金属半导体化合物薄膜的方法 （例如硅化钛工艺、 硅化钴工艺、 硅 化镍工艺等） 不利于形成超薄金属半导体化合物薄膜。
专利申请 "形成超薄可控的金属硅化物的方法" （ 申请公布号为 CN101764058A的中国专利申请）公开了一种制备金属硅化物的方法，该方法通 过在硅村底上沉积金属层， 金属层向硅村底扩散后去除硅村底表面剩余的金属， 并进行退火， 从而硅村底表面形成金属硅化物。 由于金属向硅村底扩散存在一 扩散饱和度， 因此扩散的金属是有限的， 并且是一定的， 从而该方法制备的金 属硅化物的厚度非常薄 （通常为 3 ~ 4nm ), 并且该厚度是可控的。
一般情况下，金属层是通过物理气相沉积（PVD, Physical Vapor Deposition ) 形成的， 并且在沉积金属时， 轰击产生的金属粒子不进行离子化处理， 而且硅 于底也不施加偏压。
然而， 上述方法也存在如下缺点： 由于常温下向硅村底扩散的金属是有限 的， 因而不能制备更厚的金属硅化物薄膜； 而在某些集成电路制程下， 所需的 金属硅化物薄膜的厚度比上述方法得到的金属硅化物薄膜的厚度要稍厚。
因此， 有必要提供一种改进的金属半导体化合物薄膜的制备方法。 发明内容
本发明的目的在于提供一种金属半导体化合物薄膜的制备方法， 以得到合 适厚度的超薄金属半导体化合物薄膜。
为解决上述问题， 本发明提出一种金属半导体化合物薄膜的制备方法， 该 方法包括如下步骤：
提供半导体村底；
利用 PVD (物理气相沉积， Physical Vapor Deposition )法在所述半导体村底 上沉积金属层， 所述金属层中的金属向所述半导体村底扩散； 其中， 在 PVD沉 积金属层的过程中， 将靶材部分离化成离子状态， 使其产生金属离子， 并在所 述半导体村底上加村底偏压；
去除所述半导体村底表面剩余的金属层； 以及
对所述半导体村底进行退火， 在所述半导体村底的表面形成金属半导体化 合物薄膜。
可选的， 所述金属半导体化合物薄膜的厚度为 3 ~ l lnm。
可选的， 所述将靶材部分离化成离子状态是通过在所述靶材上加第一偏压 实现的。
可选的， 所述第一偏压为直流偏压、 交流偏压或脉沖偏压中的任一种。 可选的， 所述村底偏压为直流偏压、 交流偏压或脉沖偏压中的任一种。 可选的， 所述半导体村底为硅或绝缘层上硅， 所述金属半导体化合物薄膜 为金属硅化物。
可选的， 所述半导体村底为锗或绝缘层上锗， 所述金属半导体化合物薄膜 为金属锗化物。
可选的， 所述金属半导体化合物薄膜由金属与所述半导体村底反应生成， 其中， 所述金属为镍、 钴、 钛、 镱中的任一种， 或镍、 钴、 钛、 镱中的任一种 并掺入铂。
可选的， 所述金属中还掺入了钨和 /或钼。
可选的， 在所述半导体村底上沉积金属层时的村底温度为 0~300°C。
可选的， 所述退火的温度为 200~900°C。
本发明由于采用上述技术方案， 使之与现有技术相比， 具有以下的优点和 积极效果：
1 )本发明提供的金属半导体化合物薄膜的制备方法， 通过在 PVD沉积金 属层的过程中， 将靶材部分离化成离子状态， 使其产生金属离子， 并在半导体 村底上加村底偏压， 使得所述金属离子加速向所述半导体村底运动， 并进入所 述半导体村底， 从而使得扩散至所述半导体村底表面的金属离子更多， 扩散深 度更深， 因而最终形成的金属半导体化合物薄膜的厚度加厚；
2 )本发明提供的金属半导体化合物薄膜的制备方法， 通过调整村底偏压的 大小可调整进入半导体村底中的金属离子的数量， 从而使得最终形成的金属半 导体化合物薄膜的厚度可调。 附图说明
图 1 为本发明实施例提供的金属半导体化合物薄膜的制备方法的步骤流程 图；
图 2A至图 2C为本发明实施例提供的金属半导体化合物薄膜的制备方法的 各步骤对应的器件截面图。 具体实施方式
以下结合附图和具体实施例对本发明提出的金属半导体化合物薄膜的制备 方法作进一步详细说明。 根据下面说明和权利要求书， 本发明的优点和特征将 更清楚。 需说明的是， 附图均采用非常筒化的形式且均使用非精准的比率， 仅 用于方便、 明晰地辅助说明本发明实施例的目的。
本发明的核心思想在于， 提供一种金属半导体化合物薄膜的制备方法， 该 方法通过在 PVD沉积金属层的过程中， 将靶材部分离化成离子状态， 使其产生 金属离子， 并在半导体村底上加村底偏压， 使得所述金属离子加速向所述半导 体村底运动， 并进入所述半导体村底， 从而使得扩散至所述半导体村底表面的 金属离子更多， 扩散深度更深， 因而最终形成的金属半导体化合物薄膜的厚度 也加厚； 同时通过调整所述村底偏压的大小可调整扩散至半导体村底表面的金 属离子的数量， 从而使得最终形成的金属半导体化合物薄膜的厚度可调。
请参考图 1 , 以及图 2A至图 2C, 其中， 图 1为本发明实施例提供的金属半 导体化合物薄膜的制备方法的步骤流程图， 图 2A至图 2C为本发明实施例提供 的金属半导体化合物薄膜的制备方法的各步骤对应的器件截面图， 如图 1 , 以及 图 2A至图 2C所示， 本发明实施例提供的金属半导体化合物薄膜的制备方法包 括如下步骤：
5101、 提供半导体村底 101; 具体地， 准备半导体村底 101 , 并完成生长前 的各项工艺， 如清洗和去除半导体村底 101 表面的天然氧化层等； 并且， 所述 半导体村底 101 上还可以有选择性地覆盖有扩散阻挡层 102, 所述扩散阻挡层 102可以是二氧化硅、 氮化硅或其它绝缘介质层；
5102、 利用 PVD法在所述半导体村底 101上沉积金属层 103, 如图 2A所 示； 所述金属层 103中的金属向所述半导体村底 101扩散； 其中， 在 PVD沉积 金属层 103 的过程中， 将靶材部分离化成离子状态， 使其产生金属离子， 并在 所述半导体村底 101上加村底偏压；
5103、 去除所述半导体村底 101表面剩余的金属层 103; 具体地， 利用湿法 或干法刻蚀除去所述半导体村底 101表面剩余地金属层 101;去除所述半导体村 底 101表面剩余的金属层 103后的器件截面图如图 2B所示，所述金属扩散至所 述半导体村底 101表面后， 在所述半导体村底 101的表面形成含有金属的半导 体薄层 104; 以及
5104、 对所述半导体村底 101进行退火， 在所述半导体村底 101的表面形 成金属半导体化合物薄膜 105, 如图 2C所示。
进一步地， 所述金属半导体化合物薄膜 105的厚度为 3 ~ llnm。
进一步地， 所述将靶材部分离化成离子状态是通过在所述靶材上加第一偏 压实现的。 当然， 本发明并不以此为限， 任何使得靶材的一部分离化成离子状 态的方式都在本发明的保护范围之内。 进一步地， 所述第一偏压为直流偏压、 交流偏压或脉沖偏压中的任一种。 需要说明的是， 所述第一偏压的大小取决于使用的 PVD系统， 即 PVD系 统不同， 所述第一偏压的大小也相应地有所变化； 一般来说， 所述第一偏压的 大小为 200V~1000V, 其中对于交流偏压和脉沖偏压来说， 上述大小指的是其有 效值。 进一步地， 所述村底偏压为直流偏压、 交流偏压或脉沖偏压中的任一种。
需要说明的是， 所述村底偏压的大小是可调的， 通过调整所述村底偏压的 大小， 可以调整扩散至半导体村底表面的金属离子的数量， 从而使得最终形成 的金属半导体化合物薄膜的厚度可调。 一般来说， 所述村底偏压的大小为 200V-1000V, 其中对于交流偏压和脉沖偏压来说， 上述大小指的是其有效值。
进一步地， 所述半导体村底 101 为硅或绝缘层上硅， 所述金属半导体化合 物薄膜 105为金属硅化物。
进一步地， 所述半导体村底 101 为锗或绝缘层上锗， 所述金属半导体化合 物薄膜 105为金属锗化物。
需要说明地是， 当所述半导体村底 101 为硅或锗时， 所述村底偏压可为直 流偏压、 交流偏压或脉沖偏压中的任一种； 当所述半导体村底 101 为绝缘层上 硅或绝缘层上锗时， 由于包含有绝缘层， 因此直流偏压不起作用， 需加交流偏 压或脉沖偏压。
当然， 本发明中的半导体村底 101 并不以上述举例的种类为限， 其它种类 的半导体村底， 例如三五族化合物半导体村底等也在本发明的保护范围之内。
进一步地， 所述金属半导体化合物薄膜 105 由金属与所述半导体村底 101 反应生成， 其中， 所述金属为镍、 钴、 钛、 镱中的任一种， 或镍、 钴、 钛、 镱 中的任一种并掺入铂； 掺入铂是因为纯的一硅化镍在高温条件下稳定性差， 或 出现薄膜厚度变得不均匀并结块， 或生成电阻率高的二硅化镍 NiSi2, 严重影响 器件的性能， 因此， 为了减慢硅化镍的生长速度以及防止硅化镍薄层遇到高温 时发生结块或形成二硅化镍， 可以在镍中掺入一定比例的铂； 其它金属中掺铂 作类似解释。
进一步地， 所述金属中还掺入了钨和 /或钼； 以进一步控制硅化镍或掺铂硅 化镍的生长和镍 /铂的扩散， 并增加硅化镍或掺铂硅化镍的稳定性； 其它金属中 掺钨和 /或钼作类似解释。 当然， 本发明中的金属并不以上述举例的具体金属为限， 其它能与半导体 材料发生反应， 产生金属半导体化合物薄膜的金属都在本发明的保护范围之内。
进一步地， 在所述半导体村底上沉积金属层时的村底温度为 0~300°C ; 这是 因为对金属镍来说，沉积温度超过 300°C会造成在超量的镍扩散的同时镍会和硅 直接反应形成硅化镍， 导致厚度控制的失败； 在该特定温度下， 镍会经硅表面 向硅村底进行扩散， 这种扩散具有自饱和特性： 镍向硅村底进行扩散仅在硅的 表面薄层中发生， 形成一定硅 /镍原子比例的薄层镍， 该薄层镍的厚度和淀积时 的村底温度有关， 温度越高， 该薄层镍的厚度也越大， 在室温下， 该薄层镍的 等效镍厚度为 2纳米左右。
进一步地， 所述退火的温度为 200~900°C。
综上所述， 本发明提供了一种金属半导体化合物薄膜的制备方法， 该方法 通过在 PVD沉积金属层的过程中， 将靶材部分离化成离子状态， 使其产生金属 离子， 并在半导体村底上加村底偏压， 使得所述金属离子加速向所述半导体村 底运动， 并进入所述半导体村底， 从而使得扩散至所述半导体村底表面的金属 离子更多， 扩散深度更深， 因而最终形成的金属半导体化合物薄膜的厚度也加 厚； 同时通过调整所述村底偏压的大小可调整扩散至半导体村底表面的金属离 子的数量， 从而使得最终形成的金属半导体化合物薄膜的厚度可调。
显然， 本领域的技术人员可以对发明进行各种改动和变型而不脱离本发明 的精神和范围。 这样， 倘若本发明的这些修改和变型属于本发明权利要求及其 等同技术的范围之内， 则本发明也意图包含这些改动和变型在内。

Claims

1、 一种金属半导体化合物薄膜的制备方法， 其特征在于， 包括如下步骤： 提供半导体衬底；
利用 PVD法在所述半导体衬底上沉积金属层， 所述金属层中的金属向所述 半导体衬底扩散； 其中， 在 PVD沉积金属层的过程中， 将靶材部分离化成离子 状态， 使其产生金属离子， 并在所述半导体衬底上加衬底偏压；
去除所述半导体衬底表面剩余的金属层； 以及
对所述半导体衬底进行退火， 在所述半导体衬底的表面形成金属半导体化 合物薄膜。
2、 如权利要求 1所述的金属半导体化合物薄膜的制备方法， 其特征在于， 所述金属半导体化合物薄膜的厚度为 3 ~ llnm。
3、 如权利要求 2所述的金属半导体化合物薄膜的制备方法， 其特征在于， 所述将靶材部分离化成离子状态是通过在所述靶材上加第一偏压实现的。
4、 如权利要求 3所述的金属半导体化合物薄膜的制备方法， 其特征在于， 所述第一偏压为直流偏压、 交流偏压或脉冲偏压中的任一种。
5、 如权利要求 2所述的金属半导体化合物薄膜的制备方法， 其特征在于， 所述衬底偏压为直流偏压、 交流偏压或脉冲偏压中的任一种。
6、 如权利要求 1所述的金属半导体化合物薄膜的制备方法， 其特征在于， 所述半导体衬底为硅或绝缘层上硅， 所述金属半导体化合物薄膜为金属硅化物。
7、 如权利要求 1所述的金属半导体化合物薄膜的制备方法， 其特征在于， 所述半导体衬底为锗或绝缘层上锗， 所述金属半导体化合物薄膜为金属锗化物。
8、 如权利要求 6或 7所述的金属半导体化合物薄膜的制备方法， 其特征在 于， 所述金属半导体化合物薄膜由金属与所述半导体衬底反应生成， 其中， 所 述金属为镍、 钴、 钛、 镱中的任一种， 或镍、 钴、 钛、 镱中的任一种并掺入铂。
9、 如权利要求 9所述的金属半导体化合物薄膜的制备方法， 其特征在于， 所述金属中还掺入了钨和 /或钼。
10、 如权利要求 1所述的金属半导体化合物薄膜的制备方法， 其特征在于， 在所述半导体衬底上沉积金属层时的衬底温度为 0〜300°C。
11、 如权利要求 1所述的金属半导体化合物薄膜的制备方法， 其特征在于， 所述退火的温度为 200〜900°C。
PCT/CN2011/080264 2011-03-17 2011-09-28 金属半导体化合物薄膜的制备方法 Ceased WO2012122787A1 (zh)

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