WO2012093575A1 - Procédé de fabrication de condensateur céramique à semi-conducteur empilé et condensateur céramique à semi-conducteur empilé - Google Patents

Procédé de fabrication de condensateur céramique à semi-conducteur empilé et condensateur céramique à semi-conducteur empilé Download PDF

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WO2012093575A1
WO2012093575A1 PCT/JP2011/079207 JP2011079207W WO2012093575A1 WO 2012093575 A1 WO2012093575 A1 WO 2012093575A1 JP 2011079207 W JP2011079207 W JP 2011079207W WO 2012093575 A1 WO2012093575 A1 WO 2012093575A1
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ceramic capacitor
semiconductor ceramic
compound
multilayer semiconductor
producing
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Japanese (ja)
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光俊 川本
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株式会社 村田製作所
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Priority to JP2012551812A priority Critical patent/JP5418993B2/ja
Priority to CN201180041685.9A priority patent/CN103098157B/zh
Publication of WO2012093575A1 publication Critical patent/WO2012093575A1/fr

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    • H01G4/00—Fixed capacitors; Processes of their manufacture
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    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H01G4/1209—Ceramic dielectrics characterised by the ceramic dielectric material
    • H01G4/1218—Ceramic dielectrics characterised by the ceramic dielectric material based on titanium oxides or titanates
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Definitions

  • the present invention relates to a method for manufacturing a multilayer semiconductor ceramic capacitor and a multilayer semiconductor ceramic, and more specifically, a method for manufacturing a SrTiO 3 -based grain boundary insulating multilayer semiconductor ceramic capacitor, and a manufacturing method using this manufacturing method.
  • the present invention relates to a multilayer semiconductor ceramic capacitor.
  • semiconductor elements such as various ICs and LSIs are increasingly used in order to realize downsizing and multi-functionalization of electronic devices, and accordingly, noise resistance of electronic devices is decreasing.
  • a film capacitor, a multilayer ceramic capacitor, a multilayer semiconductor ceramic capacitor, or the like is provided as a bypass capacitor in the power supply line of the semiconductor element, thereby ensuring noise resistance of electronic equipment.
  • a bypass capacitor 104 is arranged on the power supply line 103 that connects the external terminal 101 and the semiconductor element 102, and a zener diode 105, for example, is connected in parallel with the bypass capacitor 104. It is widely done.
  • the Zener diode 105 serves to protect the bypass capacitor 104 and the semiconductor element 102, thereby ensuring an ESD withstand voltage and protecting the semiconductor element 102.
  • Zener diode 105 is provided in parallel to the bypass capacitor 104 as described above, the number of parts increases, resulting in an increase in cost and an installation space must be secured, resulting in an increase in the size of the device. There is a fear.
  • SrTiO 3 -based grain boundary insulation type multilayer semiconductor ceramic capacitors are known to have varistor characteristics, and a large current flows when a voltage exceeding a certain voltage is applied. Is also attracting attention.
  • this type of multilayer semiconductor ceramic capacitor can bear not only resistance to ESD but also protection of the semiconductor element 102, it replaces the conventional capacitor and Zener diode, as shown in FIG. It can be covered only by the multilayer semiconductor ceramic capacitor 106.
  • the number of parts and the cost can be reduced, the design can be easily standardized, and a capacitor having added value can be provided.
  • the ceramic raw material containing the donor compound is weighed so that the blending molar ratio m of the Sr site and Ti site is in the range of 1.000 ⁇ m ⁇ 1.020, and mixed and pulverized.
  • the heat treated powder is molded to produce a ceramic green sheet, and then the internal electrode layer and the ceramic green sheet
  • a laminated body forming step of alternately laminating a laminate and a primary firing treatment on the laminated body in a reducing atmosphere, and then in a weak reducing atmosphere, an air atmosphere, or Method for manufacturing a stacked semiconductor ceramic capacitor with varistor function including the firing process has been proposed to perform the secondary firing process under reduction atmosphere.
  • the primary firing process is performed at a firing temperature (for example, 1100 to 1300 ° C.) lower than the calcining temperature (1300 to 1450 ° C.), and the subsequent secondary firing process is performed at a firing temperature of 600 to 900 ° C.
  • a firing temperature for example, 1100 to 1300 ° C.
  • the calcining temperature (1300 to 1450 ° C.
  • the subsequent secondary firing process is performed at a firing temperature of 600 to 900 ° C.
  • the present invention has been made in view of such circumstances, SrTiO 3 -based grain capable capacitance ESD absorption performance even at low capacity of about 1nF obtain a favorable laminated semiconductor ceramic capacitor It is an object of the present invention to provide a method for manufacturing a field insulation type multilayer semiconductor ceramic capacitor, and a multilayer semiconductor ceramic capacitor obtained by using this manufacturing method.
  • the present inventor conducted intensive studies on a SrTiO 3 -based intergranular insulation type laminated semiconductor ceramic capacitor.
  • the secondary firing (reoxidation treatment) after the primary firing in the firing step is 450. It has been found that by carrying out at a low temperature of ⁇ 580 ° C., the peak voltage can be suppressed, whereby a multilayer semiconductor ceramic capacitor having good ESD absorption performance can be obtained.
  • the present invention has been made on the basis of these findings, and the method for producing a multilayer semiconductor ceramic capacitor according to the present invention involves weighing a predetermined amount of an Sr compound, a Ti compound, and a donor compound, and mixing and grinding them.
  • the secondary firing process is performed at 450 ° C. to It is characterized by performing at an ambient temperature of 80 ° C..
  • the calcining temperature in the calcining treatment is higher than the firing temperature in the primary calcining treatment.
  • the mixing molar ratio m of Sr sites and Ti sites is in a range of 0.990 ⁇ m ⁇ 1.010. It is preferable to weigh the Sr compound and the Ti compound.
  • the acceptor compound in the heat treatment powder production step, is added so as to be 0.5 mol or less (excluding 0 mol) with respect to 100 mol of Ti element. It is preferable to weigh.
  • a low melting point oxide in a range of 0.1 mol or less with respect to 100 mol of Ti element.
  • the multilayer semiconductor ceramic capacitor according to the present invention is manufactured using the above manufacturing method.
  • the secondary firing process is performed in a temperature atmosphere of 450 ° C. to 580 ° C., the reoxidation process is performed at a low temperature, thereby suppressing the peak voltage. Therefore, even if the capacitance is reduced to about 1 nF, it is possible to obtain a multilayer semiconductor ceramic capacitor having good ESD absorption performance.
  • the multilayer semiconductor ceramic capacitor of the present invention since it is manufactured using the above manufacturing method, the absorption performance against ESD is good even when the capacitance is reduced to about 1 nF. Compared with the case of using together with a Zener diode, an ESD resistance comparable to that of the Zener diode can be obtained. Therefore, the functions of the capacitor and the Zener diode can be handled by one element, the number of parts can be reduced and the cost can be reduced, and the standardization of the design is facilitated. Can be realized.
  • FIG. 1 is a cross-sectional view schematically showing an embodiment of a multilayer semiconductor ceramic capacitor according to the present invention.
  • the multilayer semiconductor ceramic capacitor includes a component body 1 and external electrodes 3a and 3b formed at both ends of the component body 1.
  • the component body 1 is composed of a laminated sintered body in which a plurality of semiconductor ceramic layers 1a to 1g and a plurality of internal electrode layers 2a to 2f are alternately laminated and fired.
  • the internal electrode layers 2a, 2c, and 2e are: The component element body 1 is exposed at one end face and electrically connected to one external electrode 3a, and the internal electrode layers 2b, 2d, and 2f are exposed at the other end face of the component element body 1 and the other It is electrically connected to the external electrode 3b.
  • the semiconductor ceramic layers 1a to 1g are mainly composed of a SrTiO 3 material, the donor element is solid-solved in the crystal particles, the acceptor element is present in the grain boundary layer, and the crystal particles are Capacitance is formed through the grain boundary layer.
  • These semiconductor ceramic layers 1a to 1g are connected in series or in parallel between the opposing surfaces of the internal electrode layers 2a, 2c, and 2e and the internal electrode layers 2b, 2d, and 2f. It has gained.
  • the secondary firing after the primary firing in the firing step is performed in a low temperature atmosphere of 450 to 580 ° C., thereby dramatically improving the ESD absorption performance. It becomes possible.
  • the firing process is usually performed in two stages, a primary firing process and a secondary firing process.
  • the primary firing process is performed in a reducing atmosphere, whereby the ceramic is made semiconductor.
  • the secondary firing process is performed in an air atmosphere, and the semiconductorized ceramic is reoxidized. That is, in this secondary firing treatment, oxygen is diffused into the crystal grain boundary to form an insulating layer (grain boundary insulating layer) at the crystal grain boundary, and a Schottky barrier is formed at the crystal grain boundary.
  • the height of the Schottky barrier formed at the crystal grain boundary is lowered, and as a result, the varistor voltage can be lowered.
  • the varistor voltage decreases in this way, the resistance of the multilayer semiconductor ceramic capacitor during discharge decreases, so that the peak voltage (maximum voltage after being suppressed by the multilayer semiconductor ceramic capacitor with respect to the applied voltage) can be suppressed. This makes it possible to dramatically improve the ESD absorption performance.
  • the firing temperature of the secondary firing treatment must be 580 ° C. or lower.
  • the firing temperature of the secondary firing process is lowered to less than 450 ° C., the crystal grain boundaries cannot be sufficiently oxidized, and it becomes difficult to form a desired grain boundary insulating layer, resulting in an increase in capacitance. May increase excessively.
  • the firing temperature of the secondary firing treatment in the range of 450 to 580 ° C.
  • the manufactured multilayer semiconductor ceramic capacitor can dramatically improve the absorption performance against ESD. .
  • the ESD resistance can be improved to the extent that there is no inferiority. That is, it is possible to obtain good ESD resistance with one element of the multilayer semiconductor ceramic capacitor, and it is possible to protect not only the capacitor function but also the connected semiconductor element.
  • one multilayer semiconductor ceramic capacitor can function as a capacitor and a Zener diode in this way, the number of parts can be reduced and the cost can be reduced, and the design can be easily standardized.
  • a high value multilayer semiconductor ceramic capacitor can be realized.
  • the blending molar ratio m between the Sr site and the Ti site is 0.990 ⁇ m ⁇ 1.010.
  • the blending molar ratio m exceeds 1.010, the precipitation of Sr not dissolved in the crystal particles to the crystal grain boundary increases, the thickness of the grain boundary insulating layer becomes excessively thick, and the capacitance is increased. There is a risk of excessive degradation.
  • the blending molar ratio m is less than 0.990, the average grain size of the crystal grains becomes excessively large, the insulation is significantly lowered, and the ESD withstand voltage is also lowered.
  • the blending molar ratio m is 0.990 ⁇ m ⁇ 1.010.
  • the donor element is solid-solved in the crystal particles in order to convert the ceramic into a semiconductor by performing a firing process in a reducing atmosphere, but the content is not particularly limited.
  • the donor element is less than 0.2 mol with respect to 100 mol of Ti element, there is a risk of causing an excessive decrease in capacitance.
  • the donor element exceeds 1.2 mol with respect to 100 mol of Ti element, the allowable temperature range of the firing temperature may be narrowed.
  • the molar amount of the donor element is 0.2 to 1.2 mol, preferably 0.4 to 1.0 mol, per 100 mol of Ti element.
  • donor element it is not specifically limited, For example, La, Nd, Sm, Dy, Nb, Ta, etc. can be used.
  • the grain boundary insulating layer forms an energy level (grain boundary level) that is electrically activated to form a Schottky barrier.
  • the insulation resistance is improved, and a multilayer semiconductor ceramic capacitor having good insulation can be obtained.
  • the ESD withstand voltage is lowered, which is not preferable.
  • the molar content of the acceptor element is preferably 0.5 mol or less (excluding 0 mol) with respect to 100 mol of Ti element.
  • Mn Mn, Co, Ni, Cr etc.
  • Mn Mn, Co, Ni, Cr etc.
  • a low melting point oxide in the range of 0.1 mole or less to 100 moles of Ti element in the semiconductor ceramic 1, and by adding such a low melting point oxide, sintering is performed. And the segregation of the acceptor element to the crystal grain boundary can be promoted.
  • the content of the low melting point oxide is within the above range because when the content exceeds 0.1 mol with respect to 100 mol of Ti element, the electrostatic capacity is excessively lowered, and the desired electrical properties are reduced. This is because characteristics may not be obtained.
  • the low-melting-point oxide is not particularly limited, SiO 2, B and alkali metal element (K, Li, Na, etc.) glass ceramic containing copper - may be used tungsten salt However, SiO 2 is preferably used.
  • an Sr compound such as SrCO 3 as a ceramic raw material, a donor compound containing a donor element such as La or Sm, and TiO having a specific surface area of 10 m 2 / g or more (average particle size: about 0.1 ⁇ m or less), for example.
  • a fine Ti compound such as 2 and weigh a predetermined amount.
  • a predetermined amount for example, 1 to 3 parts by weight
  • a dispersant is added to the weighed product, and the mixture is put into a ball mill together with a grinding medium such as PSZ (Partially Stabilized Zirconia) balls and pure water. Then, the slurry is sufficiently wet-mixed in the ball mill.
  • a grinding medium such as PSZ (Partially Stabilized Zirconia) balls and pure water.
  • the slurry is evaporated to dryness, and then calcined at a predetermined temperature (for example, 1250 ° C. to 1400 ° C.) for about 2 hours in an air atmosphere to produce a calcined powder in which the donor element is dissolved. .
  • a predetermined temperature for example, 1250 ° C. to 1400 ° C.
  • the acceptor compound is weighed so that the content of the acceptor element such as Mn or Co is 0.5 mol or less with respect to 100 mol of the Ti element, and if necessary, a low melting point oxide such as SiO 2 . Are weighed so that the molar amount of O is 0 to 0.1 mol per 100 mol of Ti element.
  • the calcined powder, pure water and, if necessary, a dispersant are added to the acceptor compound and the low melting point oxide, and the mixture is again put into the ball mill together with the grinding medium, and mixed sufficiently in the ball mill. Thereafter, it is evaporated to dryness, and heat treatment is performed at a predetermined temperature (for example, 500 to 700 ° C.) for about 5 hours in an air atmosphere to produce heat treated powder.
  • an organic solvent such as toluene and alcohol, an organic binder, an antifoaming agent, a surface modifying agent, and the like are appropriately added to the heat-treated powder and mixed in a sufficiently wet manner, thereby obtaining a ceramic slurry.
  • the ceramic slurry is formed using a forming method such as a doctor blade method, a lip coater method, a die coater method, etc., and the thickness after firing becomes a predetermined thickness (for example, about 3 to 4 ⁇ m). A sheet is produced.
  • a forming method such as a doctor blade method, a lip coater method, a die coater method, etc.
  • a transfer using a screen printing method, a gravure printing method, a vacuum deposition method, a sputtering method, or the like is performed on the ceramic green sheet using the conductive paste for internal electrodes, and a predetermined pattern is formed on the surface of the ceramic green sheet.
  • the conductive film is formed.
  • the conductive material contained in the internal electrode conductive paste is not particularly limited, but a base metal material having good conductivity such as Ni or Cu is preferably used.
  • a plurality of ceramic green sheets on which a conductive film is formed are laminated in a predetermined direction, and an outer layer ceramic green sheet on which a conductive film is not formed is laminated. Is made.
  • the binder removal treatment is performed for about 2 hours at a temperature of 300 to 500 ° C. in an air atmosphere.
  • primary firing is performed at a temperature of 1200 to 1250 ° C. for about 2 hours to make the laminate into a semiconductor.
  • the calcination temperature (1250 to 1400 ° C.) in the calcination treatment higher than the calcination temperature (1200 to 1250 ° C.) in the primary calcination treatment, grain growth of crystal grains is promoted in the primary calcination treatment. There is almost nothing, and it can suppress that a crystal grain coarsens.
  • the laminated body is made into a semiconductor in this way, it is subjected to secondary firing at a low temperature of 450 to 580 ° C. for about 1 hour in an air atmosphere to re-oxidize the semiconductor ceramic, whereby the internal electrode 2 is embedded.
  • a component body 1 made of the laminated sintered body is produced.
  • This reoxidation treatment disperses oxygen at the grain boundaries and forms a grain boundary insulation layer.
  • the thickness of the grain boundary insulation layer is small. Therefore, the height of the Schottky barrier is also low, and the varistor voltage, and hence the peak voltage can be reduced.
  • a conductive paste for external electrodes is applied to both ends of the component element body 1, and a baking process is performed to form external electrodes 3a and 3b, whereby a multilayer semiconductor ceramic capacitor is manufactured.
  • the external electrodes 3a and 3b may be formed by printing, vacuum deposition, sputtering, or the like. Moreover, after applying the conductive paste for external electrodes to both end portions of the unfired laminate, the firing treatment may be performed simultaneously with the laminate.
  • the conductive material contained in the conductive paste for external electrodes is not particularly limited, but it is preferable to use a material such as Ga, In, Ni, or Cu. Further, an Ag electrode is provided on these electrodes. It is also possible to form
  • the thickness of the grain boundary insulating layer formed by being diffused to the grain boundaries is thin, and thus the crystal grains
  • the height of the Schottky barrier formed at the boundary is also low, and the varistor voltage can be lowered.
  • the varistor voltage decreases in this way, the resistance of the multilayer semiconductor ceramic capacitor during discharge decreases, and as a result, it becomes possible to suppress the peak voltage, thereby dramatically improving the ESD absorption performance.
  • Can do In other words, the ESD resistance can be improved to the extent that it is inferior to the case where a capacitor and a Zener diode are used in combination, and good ESD resistance can be ensured with one element of the multilayer semiconductor ceramic capacitor.
  • a stacked semiconductor having an ESD withstand voltage of 30 kV or more, a varistor voltage of 75 V or less, a peak voltage of 85 V or less, and excellent ESD absorption characteristics A ceramic capacitor can be obtained.
  • the single-layer semiconductor ceramic capacitor element can function as a capacitor and a Zener diode in this way, the number of parts can be reduced and the cost can be reduced, and the design can be easily standardized.
  • a high value multilayer semiconductor ceramic capacitor can be realized.
  • the present invention is not limited to the above embodiment.
  • the solid solution is produced by the solid phase method, but the production method of the solid solution is not particularly limited.
  • hydrothermal synthesis method, sol-gel method, hydrolysis method, coprecipitation Any method such as a method can be used.
  • this slurry was evaporated to dryness, and then calcined at a temperature of 1400 ° C. for 2 hours in an air atmosphere to obtain a calcined powder in which a donor element was dissolved in crystal particles.
  • a MnCl 2 solution is added to the calcined powder so that the content of Mn element as an acceptor element is 0.3 mol with respect to 100 mol of Ti element, and further SiO 2 content with respect to 100 mol of Ti element Tetraethoxysilane (Si (OC 2 H 5 ) 4 ) was added so that the molar amount was 0.1 mol, and then charged again into the ball mill together with PSZ balls having a diameter of 2 mm and pure water. Wet mixed for hours.
  • the MnCl 2 solution is added to the calcined powder, but a Mn sol solution may be added.
  • an appropriate amount of an organic solvent such as toluene and alcohol and a dispersant were added to the heat-treated powder, and the mixture was again put into a ball mill together with a PSZ ball having a diameter of 2 mm, and mixed in the ball mill for 16 hours in a wet manner. Thereafter, an appropriate amount of polyvinyl vinyl (PVB) as an organic binder and dioctyl phthalate (DOP) as a plasticizer were added, and a wet mixing process was performed for 24 hours, thereby preparing a ceramic slurry.
  • PVB polyvinyl vinyl
  • DOP dioctyl phthalate
  • the ceramic slurry was molded using a lip coater method to produce a ceramic green sheet having a thickness of about 3.2 ⁇ m.
  • screen printing was performed on the ceramic green sheet using an internal electrode conductive paste containing Ni as a main component, and a conductive film having a predetermined pattern was formed on the surface of the ceramic green sheet.
  • the ceramic green sheets for the outer layer without the conductive film are applied up and down, and then the thickness is about 0.6 mm.
  • the thickness is about 0.6 mm.
  • the block body was cut to a predetermined size to obtain a laminated body, and the laminated body was subjected to a binder removal treatment in an air atmosphere at a temperature of 400 ° C. for 2 hours.
  • re-oxidation treatment is performed by performing secondary firing at a temperature of 400 to 800 ° C. for 1 hour in an air atmosphere, thereby dispersing oxygen in the grain boundaries to form a grain boundary insulating layer, Was then polished to prepare a component body.
  • the voltage waveform (absorption waveform) was measured with an oscilloscope in accordance with IEC61000-4-2 (international standard) which is an immunity test standard, and the peak voltage was obtained.
  • FIG. 2 is an electric circuit diagram of an ESD voltage waveform measuring apparatus.
  • a charging capacitor C is connected in parallel with the power source V at a connection point between the discharge resistor R1 and the charging resistor R2. Further, a switch S1 is interposed between the power source V and the discharge resistor R1, a switch S2 is provided on the output side of the charging resistor R2, and the sample 11 is interposed between the output terminals.
  • the electrostatic capacity of the charging capacitor C was 150 pF, the discharge resistance R1 was 330 ⁇ , and a voltage of 8 kV was applied to the charging capacitor C, and a discharge test was performed on each sample 11 of sample numbers 1 to 8. And the voltage waveform was measured with the oscilloscope about each sample 11, and the peak voltage was read from the measurement result of the oscilloscope.
  • Table 1 shows the secondary firing temperature and measurement results of sample numbers 1 to 8.
  • Sample No. 8 had a secondary firing temperature as high as 800 ° C., so that the internal electrode was oxidized, and thus the capacitance could not be measured.
  • Sample Nos. 6 and 7 had a high secondary voltage of 600 to 700 ° C., so the peak voltage was as high as 150 V or higher.
  • Sample Nos. 2 to 5 have a secondary firing temperature of 450 to 580 ° C., which is within the range of the present invention, so that the peak voltage can be lowered to 65 to 85 V, and the ESD absorption characteristics can be improved. I understood.
  • the peak voltage decreases as the secondary firing temperature decreases. That is, when the secondary firing temperature is lowered, the thickness of the grain boundary insulating layer formed by being dispersed at the crystal grain boundary is also thinned. As a result, the height of the Schottky barrier formed at the crystal grain boundary is also low, so that the varistor voltage is reduced. descend.
  • the varistor voltage is lowered, the resistance of the sample 11 (see FIG. 2) is lowered during the discharge test, so that it is considered that the peak voltage is also lowered.

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  • General Life Sciences & Earth Sciences (AREA)
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  • Life Sciences & Earth Sciences (AREA)
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Abstract

L'invention porte sur un procédé de fabrication d'un condensateur céramique à semi-conducteur empilé, de type à couche barrière de SrTiO3, qui comporte les étapes suivantes : la production de poudre calcinée par l'exécution d'un procédé de calcination après pesage d'une quantité donnée de composés de Sr, de Ti et donneur, et de mélange et de broyage de ceux-ci ; la production de poudre traitée thermiquement par le mélange d'un composé accepteur avec la poudre calcinée et le traitement thermique du mélange ; la formation d'une structure empilée afin d'obtenir une feuille crue de céramique par le moulage de la poudre traitée thermiquement et, par la suite, la formation d'une structure empilée en stratifiant de façon alternée une couche d'électrode interne et la feuille crue de céramique ; la calcination consistant à mettre en œuvre un second procédé de calcination dans une atmosphère d'air, après la mise en œuvre d'un premier procédé de calcination sur la structure empilée dans une atmosphère réductrice, le second procédé de calcination étant mis en œuvre dans une atmosphère à une température allant de 450°C à 580°C. Ainsi, un condensateur céramique à semi-conducteur empilé, de type à couche barrière de SrTiO3 est obtenu, celui-ci présentant une bonne efficacité d'absorption pour une décharge électrostatique (DES), même si la capacité électrostatique présente une faible valeur telle que 1 nF.
PCT/JP2011/079207 2011-01-05 2011-12-16 Procédé de fabrication de condensateur céramique à semi-conducteur empilé et condensateur céramique à semi-conducteur empilé WO2012093575A1 (fr)

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CN201180041685.9A CN103098157B (zh) 2011-01-05 2011-12-16 层叠型半导体陶瓷电容器的制造方法、以及层叠型半导体陶瓷电容器

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JP2015026801A (ja) * 2013-07-29 2015-02-05 サムソン エレクトロ−メカニックス カンパニーリミテッド． 積層セラミックキャパシタ、その製造方法及び積層セラミックキャパシタの実装基板

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CN109650878B (zh) * 2019-01-10 2021-08-24 陕西科技大学 一种无铅宽频下巨介电低损耗高绝缘电阻陶瓷材料及其制备方法

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JP2007180297A (ja) * 2005-12-28 2007-07-12 Murata Mfg Co Ltd 半導体セラミック、及び積層型半導体セラミックコンデンサ、並びに半導体セラミックの製造方法
WO2007139061A1 (fr) * 2006-05-31 2007-12-06 Murata Manufacturing Co., Ltd. Céramique semi-conductrice, condensateur en céramique semi-conductrice stratifiée, procédé de fabrication de céramique semi-conductrice, et procédé de fabrication de condensateur en céramique semi-conductrice stratifiée
WO2008004389A1 (fr) * 2006-07-03 2008-01-10 Murata Manufacturing Co., Ltd. Condensateur céramique semi-conducteur superposé doté d'une fonction de varistance et procédé permettant de le fabriquer

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CN1295189C (zh) * 2005-03-30 2007-01-17 天津大学 一种用于制备SrTiO3基压敏电容双功能陶瓷的方法
EP2159196A4 (fr) * 2007-06-27 2014-12-10 Murata Manufacturing Co Poudre céramique semi-conductrice, céramique semi-conductrice, et condensateur semi-conducteur stratifié

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JPH01289205A (ja) * 1988-05-17 1989-11-21 Matsushita Electric Ind Co Ltd 電圧依存性非直線抵抗体素子及びその製造方法
JPH02215112A (ja) * 1989-02-16 1990-08-28 Matsushita Electric Ind Co Ltd セラミックコンデンサ及びその製造方法
JPH03138905A (ja) * 1989-10-24 1991-06-13 Matsushita Electric Ind Co Ltd 電圧依存性非直線抵抗体磁器及びその製造方法
JP2007180297A (ja) * 2005-12-28 2007-07-12 Murata Mfg Co Ltd 半導体セラミック、及び積層型半導体セラミックコンデンサ、並びに半導体セラミックの製造方法
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US9837212B2 (en) 2013-07-29 2017-12-05 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic capacitor, method of manufacturing the same, and board having the same mounted thereon

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