WO2012070821A3 - 플립플롭 회로의 레이아웃 라이브러리 - Google Patents
플립플롭 회로의 레이아웃 라이브러리 Download PDFInfo
- Publication number
- WO2012070821A3 WO2012070821A3 PCT/KR2011/008888 KR2011008888W WO2012070821A3 WO 2012070821 A3 WO2012070821 A3 WO 2012070821A3 KR 2011008888 W KR2011008888 W KR 2011008888W WO 2012070821 A3 WO2012070821 A3 WO 2012070821A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- flip
- flop circuit
- layout
- layout library
- library
- Prior art date
Links
- 230000008878 coupling Effects 0.000 abstract 2
- 238000010168 coupling process Methods 0.000 abstract 2
- 238000005859 coupling reaction Methods 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
- H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
- H03K3/356147—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates
- H03K3/356156—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates with synchronous operation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Architecture (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
동일한 플립플롭 회로가 구현되는 다수의 단위 레이아웃들을 가지는 레이아웃 라이브러리가 제공된다. 레이아웃 라이브러리 내에서 적어도 2개의 단위 레이아웃은 서로 상이한 배치구조를 가진다. 따라서, 2개의 플립플롭 회로들에서 동일한 노드에서 바라보는 커플링 커패시턴스는 서로 상이하게 나타난다. 반도체 설계자는 배선을 통해 원하는 커플링 커패시턴스가 설정된 레이아웃을 선택할 수 있고, 이를 통해 필요한 플립플롭 회로를 채용할 수 있다.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/989,052 US8856704B2 (en) | 2010-11-22 | 2011-11-21 | Layout library of flip-flop circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US41625310P | 2010-11-22 | 2010-11-22 | |
US61/416,253 | 2010-11-22 |
Publications (3)
Publication Number | Publication Date |
---|---|
WO2012070821A2 WO2012070821A2 (ko) | 2012-05-31 |
WO2012070821A3 true WO2012070821A3 (ko) | 2012-07-19 |
WO2012070821A9 WO2012070821A9 (ko) | 2012-08-16 |
Family
ID=46146265
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/KR2011/008888 WO2012070821A2 (ko) | 2010-11-22 | 2011-11-21 | 플립플롭 회로의 레이아웃 라이브러리 |
Country Status (2)
Country | Link |
---|---|
US (1) | US8856704B2 (ko) |
WO (1) | WO2012070821A2 (ko) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9780082B2 (en) | 2015-03-12 | 2017-10-03 | Samsung Electronics Co., Ltd. | Semiconductor device, layout system, and standard cell library |
KR102386907B1 (ko) | 2015-09-10 | 2022-04-14 | 삼성전자주식회사 | 반도체 집적 회로 |
US9514264B1 (en) | 2016-01-05 | 2016-12-06 | Bitfury Group Limited | Layouts of transmission gates and related systems and techniques |
US20170213847A1 (en) * | 2016-01-05 | 2017-07-27 | Bitfury Group Limited | Layouts of transmission gates and related systems and techniques |
US9645604B1 (en) | 2016-01-05 | 2017-05-09 | Bitfury Group Limited | Circuits and techniques for mesochronous processing |
US9660627B1 (en) | 2016-01-05 | 2017-05-23 | Bitfury Group Limited | System and techniques for repeating differential signals |
US10642947B2 (en) * | 2016-09-06 | 2020-05-05 | New York University | System, method and computer-accessible medium providing secure integrated circuit camouflaging for minterm protection |
KR102362016B1 (ko) | 2017-09-19 | 2022-02-10 | 삼성전자주식회사 | 마스터 슬레이브 플립 플롭 |
KR102419646B1 (ko) | 2017-12-22 | 2022-07-11 | 삼성전자주식회사 | 크로스 커플 구조를 구비하는 집적 회로 및 이를 포함하는 반도체 장치 |
KR102367860B1 (ko) * | 2018-01-03 | 2022-02-24 | 삼성전자주식회사 | 반도체 장치 |
KR102518811B1 (ko) | 2018-06-25 | 2023-04-06 | 삼성전자주식회사 | 멀티-하이트 스탠다드 셀을 포함하는 집적 회로 및 그 설계 방법 |
US10930675B2 (en) * | 2018-11-20 | 2021-02-23 | Samsung Electronics Co., Ltd. | Semiconductor device |
KR20210029866A (ko) | 2019-09-06 | 2021-03-17 | 삼성전자주식회사 | 반도체 소자 |
US11509293B2 (en) | 2020-06-12 | 2022-11-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Footprint for multi-bit flip flop |
Citations (3)
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US20020040985A1 (en) * | 2000-10-05 | 2002-04-11 | Aldrich Lawrence L. | Base cell layout permitting rapid layout with minimum clock line capacitance on CMOS standard-cell and gate-array integrated circuits |
JP2005236210A (ja) * | 2004-02-23 | 2005-09-02 | Ricoh Co Ltd | スタンダードセルレイアウト、スタンダードセルライブラリ並びに半導体集積回路及びその設計方法 |
JP2009267094A (ja) * | 2008-04-25 | 2009-11-12 | Panasonic Corp | 標準セルのレイアウト構造、標準セルライブラリ、及び半導体集積回路のレイアウト構造 |
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US4849904A (en) * | 1987-06-19 | 1989-07-18 | International Business Machines Corporation | Macro structural arrangement and method for generating macros for VLSI semiconductor circuit devices |
US5157618A (en) * | 1988-03-10 | 1992-10-20 | Cirrus Logic, Inc. | Programmable tiles |
US5923569A (en) * | 1995-10-17 | 1999-07-13 | Matsushita Electric Industrial Co., Ltd. | Method for designing layout of semiconductor integrated circuit semiconductor integrated circuit obtained by the same method and method for verifying timing thereof |
US5712794A (en) * | 1995-11-03 | 1998-01-27 | Motorola, Inc. | Automated method for adding attributes indentified on a schematic diagram to an integrated circuit layout |
US6571374B1 (en) * | 2000-02-28 | 2003-05-27 | International Business Machines Corporation | Invention to allow multiple layouts for a schematic in hierarchical logical-to-physical checking on chips |
JP4798881B2 (ja) * | 2001-06-18 | 2011-10-19 | 富士通セミコンダクター株式会社 | 半導体集積回路装置 |
JP4318523B2 (ja) * | 2003-10-10 | 2009-08-26 | パナソニック株式会社 | 半導体設計装置 |
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US8631366B2 (en) * | 2009-04-30 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit design using DFM-enhanced architecture |
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FR2967810B1 (fr) * | 2010-11-18 | 2012-12-21 | St Microelectronics Rousset | Procede de fabrication d'un circuit integre protege contre l'ingenierie inverse |
-
2011
- 2011-11-21 US US13/989,052 patent/US8856704B2/en active Active
- 2011-11-21 WO PCT/KR2011/008888 patent/WO2012070821A2/ko active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020040985A1 (en) * | 2000-10-05 | 2002-04-11 | Aldrich Lawrence L. | Base cell layout permitting rapid layout with minimum clock line capacitance on CMOS standard-cell and gate-array integrated circuits |
JP2005236210A (ja) * | 2004-02-23 | 2005-09-02 | Ricoh Co Ltd | スタンダードセルレイアウト、スタンダードセルライブラリ並びに半導体集積回路及びその設計方法 |
JP2009267094A (ja) * | 2008-04-25 | 2009-11-12 | Panasonic Corp | 標準セルのレイアウト構造、標準セルライブラリ、及び半導体集積回路のレイアウト構造 |
Also Published As
Publication number | Publication date |
---|---|
WO2012070821A9 (ko) | 2012-08-16 |
WO2012070821A2 (ko) | 2012-05-31 |
US8856704B2 (en) | 2014-10-07 |
US20130268904A1 (en) | 2013-10-10 |
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