WO2012059003A1 - 芯片封装方法 - Google Patents

芯片封装方法 Download PDF

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Publication number
WO2012059003A1
WO2012059003A1 PCT/CN2011/080874 CN2011080874W WO2012059003A1 WO 2012059003 A1 WO2012059003 A1 WO 2012059003A1 CN 2011080874 W CN2011080874 W CN 2011080874W WO 2012059003 A1 WO2012059003 A1 WO 2012059003A1
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WIPO (PCT)
Prior art keywords
wafer
chip packaging
packaging method
protective layer
ball
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PCT/CN2011/080874
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English (en)
French (fr)
Inventor
石磊
高国华
陶玉娟
舜田直实
目黑弘一
Original Assignee
南通富士通微电子股份有限公司
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Application filed by 南通富士通微电子股份有限公司 filed Critical 南通富士通微电子股份有限公司
Priority to US13/883,231 priority Critical patent/US8883627B2/en
Publication of WO2012059003A1 publication Critical patent/WO2012059003A1/zh

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Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a wafer level chip packaging method. Background technique
  • Wafer Level Chip Size Packaging is a technology that performs a package test on a whole wafer and then cuts a single finished chip.
  • the packaged chip size is exactly the same as the chip.
  • Wafer-level chip-scale packaging technology revolutionizes traditional packaging such as Ceramic Leadless Chip Carriers and Organic Leadless Chip Carriers, and is increasingly light in the market for microelectronics. , small, short, thin and low-cost requirements.
  • the chip size after wafer-level chip-scale packaging technology has been highly miniaturized, and the cost of the chip has been significantly reduced as the chip size has decreased and the wafer size has increased.
  • Wafer-level chip-size packaging technology is a technology that integrates IC design, wafer fabrication, package testing, and integration. It is a hot spot and future development trend in the current packaging field.
  • Chinese Patent Application No. 200610096807.5 discloses a packaging method based on wafer level chip size, which mainly includes the following process steps:
  • the semiconductor wafer 1 is bonded to the first glass substrate 2 of the same size, so that in the initial stage of the package, the device portion of the wafer surface will be covered by the substrate to protect the external environment. Pollution and damage.
  • the semiconductor wafer 1 is thinned relative to the back surface of the first glass substrate 2, and the back surface of the wafer is selectively etched by photolithography and plasma etching to form a plurality of V shapes.
  • the trench serves as a dicing street and exposes a portion of the die pad 11 (i.e., the chip electrode).
  • the V-shaped trench is filled with an insulating medium and pressed against the back surface of the wafer.
  • the second glass substrate 3 is used to support the semiconductor wafer 1, and the electrically insulating solder 4 is used to mechanically buffer the semiconductor wafer 1 in a subsequent mechanical cutting process.
  • a mechanical cutting process is used to semi-cut the position of the original V-shaped groove (without penetrating the separation chip), a new V-shaped groove is formed as a dicing street of the wafer, and the die pad 11 is formed from a V shape. The sides of the grooves are exposed.
  • the outer lead 12 is then formed by an electroplating process, the outer lead 12-end is connected to the die pad n in the V-shaped groove, and the other end is extended to the back surface of the wafer, and the chip pad 11 is The electrical function extends through the outer leads 12 to the back side of the wafer.
  • an insulating protective layer 14 is selectively formed on the back surface of the wafer to expose a portion of the outer leads 12, and solder bumps 15 are formed on the exposed outer leads 12 to cut the wafer along the V-shaped grooves on the back surface thereof.
  • the dicing is performed to form a discrete chip, and then the discrete chip is packaged in the outer casing to finally complete the packaging process of the chip.
  • the existing wafer level chip packaging method has the following problems: when the outer lead 12 is formed by an electroplating process, the metal in the scribe line (for example, in the V-shaped groove described in the above patent) is also easily plated and precipitated, resulting in the connection. A short circuit occurs between them. In addition, after cutting, the side surface of the discrete chip, that is, the side wall of the original V-shaped groove, is exposed to the external environment, and is easily damaged when the outer casing is packaged, thereby causing the external lead to be broken, thereby affecting the yield of the chip.
  • the technical problem to be solved by the present invention is to provide a chip packaging method which can improve packaging efficiency and yield.
  • the chip packaging method provided by the invention comprises the steps of:
  • a step of forming a first protective layer over the scribe line is also included.
  • the width of the first protective layer is greater than the width of the scribe line.
  • the width of the scribe line is a replacement page (Article 26) 30 ⁇ 80 ⁇ , the first protective layer has a width of 50 ⁇ 120 ⁇ .
  • the first protective layer is a thermosetting epoxy resin formed by a screen printing technique.
  • the method of forming the under-ball metal electrode is electroless plating.
  • the electroless plating comprises: first performing a zincate cleaning treatment on the surface of the wafer, and then electrolessly plating nickel, and then electroless plating gold, and the plating thickness is 3 ⁇ m and 0.05 ⁇ m, respectively.
  • the method of forming the under-ball metal electrode is selective vapor deposition.
  • the selective vapor deposition comprises: disposing a mask on a surface of the wafer, the mask exposing a position on the wafer where a metal electrode under the ball is to be formed; and depositing nickel metal and copper metal in sequence by a physical vapor deposition process.
  • the step of forming a second protective layer on the wafer and the region outside the ball-shaped metal electrode by screen printing technology is further included.
  • the second protective layer has a thickness of 5 ⁇ m to 50 ⁇ m.
  • the material of the second protective layer is a thermosetting resin, which is formed by a screen printing technique. In the screen printing, the temperature of the wafer is kept lower than the curing temperature of the thermosetting epoxy resin.
  • the method further comprises the step of removing the thermosetting epoxy resin covering the top surface of the metal electrode under the ball by plasma etching.
  • the step of grinding the surface of the wafer is further included.
  • the grinding is performed by mechanical grinding, specifically comprising: placing the wafer on a fixed worktable; winding a nonwoven fabric having a softness less than the wafer on the grinding disc and adhering to the surface of the wafer; and then infiltrating the non-woven using the polishing liquid Weaving cloth, mechanical grinding.
  • thermosetting resin has a curing temperature of less than 200 °C.
  • thermosetting resin contains a curing filler having a particle diameter smaller than 1/3 of the thickness of the epoxy resin printed.
  • thermosetting resin has a printing thickness of 15 ⁇ m
  • the curing filler has a particle diameter of less than 5 ⁇ m
  • the second protective layer formed after curing has an average thickness of 11 ⁇ m to 12 ⁇ m.
  • the wafer is subjected to a baking treatment or a surface-activated plasma treatment.
  • the encapsulation method of the present invention forms a first protective layer on a dicing street by using a screen printing technique, and specifically, a thermosetting epoxy resin can be selected as a protective layer material, and on the other hand, when a metal electrode under the ball is formed by an electroplating process, the scribe line can be prevented.
  • the metal is electroplated; on the other hand, after dicing, the page can be replaced (Article 26) Protect the sides of discrete chips, especially metal leads, from damage.
  • the process flow of the invention is simple, low in cost, and improves packaging efficiency and package yield.
  • FIG. 1 is a schematic cross-sectional view of a conventional wafer-level chip packaging method
  • FIG. 7 is a basic flow chart of the packaging method of the present invention
  • FIG. 8 is a schematic flow chart of the first embodiment of the present invention
  • FIG. 10 is a top view of FIG.
  • FIG. 12 is a schematic plan view of FIG. 11;
  • FIG. 17 is a schematic flow chart of a second embodiment of the present invention.
  • FIG. 22 and 23 are schematic views of part of the steps shown in Fig. 21.
  • the metal in the dicing street is easily plated out during the fabrication of the metal electrode under the ball to cause a short circuit, and after the dicing of the wafer, the side surface of the discrete chip is exposed to the external environment. damage.
  • the present invention employs a screen printing technique to form a first protective layer on the scribe line to solve the above problems.
  • FIG. 7 The basic flow diagram of the encapsulation method provided in this embodiment is shown in FIG. 7, and includes:
  • the semi-packaged wafer comprises: a semi-replacement page formed with a chip (Article 26) — D—
  • the protective mask may be an organic film such as polyimide, and the metal pad may be a conventional interconnect metal such as copper or aluminum.
  • the first protective layer may be printed on the dicing street by using a screen printing technique.
  • the width of the first protective layer is greater than the width of the scribe line such that after dicing, the top edge of the side of the discrete core is also protected.
  • the first protective layer may be a thermosetting resin such as an epoxy resin, a phenol resin, a urea resin, a melamine-formaldehyde resin, an unsaturated resin, a polyurethane, a polyimide, or the like.
  • the under-ball metal electrode may be formed on the metal pad within the protective mask opening by electroplating or selective vapor deposition.
  • electroless plating can be used to improve the uniformity of electroplating; and with selective vapor deposition, the same metal mask can be repeatedly used to reduce the cost.
  • Common under-ball metal electrode materials include nickel, gold, copper, aluminum, titanium, tungsten, chromium or alloys thereof, combinations, etc., and the materials can be selected according to the actual thickness limit of the metal electrode under the ball to meet the process and cost requirements.
  • a second protective layer may be formed on the wafer by screen printing technology, and the second protective layer may be selected and The first protective layer is the same thermosetting resin material.
  • the specific formation position of the second protective layer can be selected by adjusting the opening area of the screen plate used for screen printing.
  • a portion of the second protective layer covering the top surface of the under-metal electrode due to the fluidity of the thermosetting resin should be generally removed by plasma etching, and the crystal is processed by a grinding process. Round surface. In order to expose the top of the metal electrode under the ball, it is convenient for the subsequent process to make the solder ball.
  • solder ball Form a solder ball on the metal electrode under the ball.
  • the solder may be applied to the top of the metal electrode under the ball and then reflowed at a high temperature to form the solder ball.
  • Common solders include metals such as tin, lead, silver, copper, zinc, or alloys thereof, combinations, and the like.
  • FIG. 8 is a flow chart showing a first embodiment of the present invention
  • FIGS. 9 to 16 are schematic views of respective steps in the above flow, and each step will be described in detail below with reference to FIG.
  • a semi-packaged wafer 10 is provided.
  • the semi-packaged wafer includes: a semiconductor substrate 100 formed with a chip, a dicing street 200 dividing the wafer into a plurality of individual chip units, and the semiconductor lining A protective mask 101 having an opening on the bottom 100, and a metal pad 102 exposing the chip in the opening.
  • the protective mask 101 may be an organic film such as polyimide, and the metal pad 102 may be a conventional interconnect metal such as copper or aluminum.
  • the above semiconductor substrate 100 is not limited to an elemental silicon or silicon-on-insulator substrate, but should also include semiconductor devices, metal interconnections, and other semiconductor structures fabricated thereon.
  • the protective mask 101 covers the surface of the semiconductor structure to protect the chip.
  • the metal pad 102 of the chip serves as an electrode at the input/output end of the chip for extracting the electrical function of the chip.
  • FIG. 10 is a top plan view of the semi-packaged wafer.
  • the wafer is formed with a grid-shaped scribe line 200.
  • the dicing street 200 divides the wafer into a plurality of square regions, and each square region represents an independent region. chip.
  • the cross-sectional shape of the dicing street 200 may be an isosceles trapezoid, and the depth should not be too deep to affect the steel hardness of the wafer. In this embodiment, the opening width of the dicing street 200 is 30 to 80 ⁇ m.
  • 11 is a schematic cross-sectional view of a semi-packaged wafer
  • FIG. 12 is a top plan view of FIG. 11. Referring to FIG. 11 and FIG.
  • the surface of the semi-packaged wafer is subjected to a screen printing process to form a pattern above the dicing street 200.
  • the first protective layer 301 is a thermosetting resin as exemplified above.
  • the first protective layer 301 is preferably a thermosetting epoxy resin for the purpose of cost reduction.
  • the schematic diagram of the screen printing process is as shown in FIG. 13 , including: fixing the wafer 10 in the printing device, the bottom of the screen plate 20, applying a liquid epoxy resin on the screen plate 20; using the doctor blade 30
  • the screen plate 20 and the wafer 10 are pressed so that the liquid epoxy resin is applied to the surface of the wafer 10 through the opening of the screen plate 20; the screen plate 20 is peeled off from the wafer 10, thus the liquid ring
  • the oxyresin is transcribed onto the wafer 10 to form the desired pattern.
  • the opening of the screen plate 20 is aligned with the dicing street 200 on the wafer 10.
  • the liquid epoxy resin After the liquid epoxy resin penetrates into the wafer 10, it will be filled in the dicing street 200, and the wafer 10 is heated to a curing temperature. The liquid epoxy resin is cured to form the first protective layer 301.
  • the width of the first protective layer 301 In addition, in order to make the width of the first protective layer 301 larger than the width of the dicing street 200, it is only necessary to make the opening width of the screen plate 20 larger than the width of the dicing street 200, and the width of the first protective layer 301 in this embodiment. Set to 50 ⁇ 120 ⁇ .
  • the electroless plating is performed, and the first protective layer 301 and the protective mask 101 are used as a plating mask.
  • the under-ball metal electrode 103 In the opening of the protective mask 101, the under-ball metal electrode 103 is formed on the surface of the metal pad 102.
  • the metal pad 102 is subjected to zincate treatment before plating to remove the oxide film on the surface to reduce the contact resistance; then, the electroless nickel plating and the subsequent on the metal pad 102 are sequentially performed.
  • Electrolytic gold plating, the plating thicknesses were 3 ⁇ m and 0.05 ⁇ m, respectively, and finally the under-ball metal electrode 103 protruding from the surface of the protective mask 101 was formed.
  • a solder ball is formed on the top of the under-metal electrode 103 by a solder reflow process.
  • solder paste is applied to the under-ball metal electrode 103, and then subjected to high-temperature reflow, so that the solder paste is converted into the solder ball 104.
  • an underfill process is also performed on the surface of the wafer other than the solder balls 104. As shown in FIG. 16, after the solder ball fabrication process is completed, the wafer 10 is diced along the scribe line 200 to form discrete chips.
  • Fig. 17 is a flow chart showing a second embodiment of the present invention, and Figs. 18 to 20 are schematic views showing part of the steps in the above flow. The steps will be described in detail below with reference to Fig. 17. Referring to FIG.
  • the basic steps of the embodiment include: providing a semi-packaged wafer; printing a first protective layer on the scribe line by screen printing; forming an under-ball metal electrode on the metal pad by electroless plating; Forming a second protective layer on a region other than the metal electrode under the ball; grinding the surface of the wafer and plasma etching; forming a solder ball on the metal electrode under the ball; and dicing the wafer along the scribe line.
  • the difference between this embodiment and the first embodiment is only: after electroless plating to form the under-ball metal electrode, further comprising forming a second protective layer on a region other than the metal electrode under the wafer surface; Carry out the steps of the relevant process.
  • the second protective layer can further protect the wafer 10, and in the subsequent solder ball fabrication process, without underfilling, the process is finished, and if a dark resin (epoxy resin is a typical dark resin) is used, It can also prevent chip circuit failure caused by photoelectric effect caused by external illumination.
  • a second protective layer 302 is formed on the wafer 10 by screen printing technology based on the half-package wafer structure shown in FIG. 14 in the first embodiment.
  • the second protective layer 302 may be made of the same material as the first protective layer 301, such as a thermosetting epoxy resin.
  • the second protective layer 302 is a thin film structure, and the required thickness is only 5 ⁇ m to 50 ⁇ m.
  • it is necessary to maintain the fluidity of the thermosetting epoxy resin during the screen printing that is, to ensure that the temperature of the wafer 10 is lower than the curing temperature of the thermosetting epoxy resin.
  • the specific process of the screen printing may be performed by referring to FIG. 13 to form a first protective layer 301.
  • the pattern of the screen plate 20 may be changed to apply a liquid thermosetting epoxy resin to the wafer 10, the ball.
  • a region other than the lower metal electrode 103 is then heat-cured to form a desired second protective layer 302.
  • the curing temperature of the epoxy resin is less than 200 °C.
  • a curing filler such as a filler containing silica or other solid particles is usually included in the epoxy resin.
  • the filler particle diameter should be smaller than the replacement page of the printed thickness (Article 26) 1/3 to achieve uniformity of film printing and flatness requirements, thereby reducing warpage on the surface of the wafer 10.
  • the printed thickness is controlled by adjusting the emulsion thickness of the screen plate 20.
  • the printing thickness of the liquid epoxy resin is 15 ⁇ m, and the diameter of the filler particles is not more than 5 ⁇ m, and the average thickness of the second protective layer 302 formed by curing the epoxy resin can be controlled. 11 ⁇ 12 ⁇ .
  • the liquid epoxy resin has fluidity, it is inevitably infiltrated into the under-ball metal electrode 103 region. This may cause the following problems:
  • the epoxy resin located on the top surface of the under-ball metal electrode 103 will reduce the contact area of the solder ball with the under-ball metal electrode 103, thereby The combination of the solder ball and the under-metal electrode 103 is hindered, and even the solder ball may fall off during the reliability test after the package and the substrate drop test, which may have an adverse effect. Therefore, after the second protective layer 302 is formed, it is usually necessary to surface-treat the wafer 10 by polishing to remove the residue.
  • the grinding may be mechanical or chemical grinding or the like.
  • the specific grinding process used includes: placing the wafer 10 on a fixed worktable; and making the softness less than the nonwoven of the wafer.
  • the cloth 40 is wound around the polishing disk 50 and abuts against the surface of the wafer 10; then the nonwoven fabric 40 is impregnated with a polishing liquid, and mechanically ground to remove residue material adhering to the surface of the wafer 10.
  • a plasma etching process may be further performed to further remove the epoxy resin covering the top surface of the under-ball metal electrode 103.
  • the basic steps of the embodiment include: providing a semi-packaged wafer, printing a first protective layer on the scribe line by using a screen printing technique; forming a sub-ball metal electrode on the metal pad by selective vapor deposition; a second protective layer is formed in a region other than the metal electrode under the ball; a replacement page is applied to the surface of the wafer (Article 26)
  • the present embodiment differs from the foregoing two embodiments in that the method of forming the under-ball metal layer is different. Specifically, a sub-ball metal electrode is formed at a predetermined position on the wafer 10 by selective vapor deposition instead of electroless plating.
  • a mask 60 is first disposed on the surface of the wafer 10.
  • the mask 60 may be a metal mask and is closely attached.
  • an opening is formed in the mask plate 60, and an opening in the mask plate 60 is aligned with the opening of the surface of the wafer 10 to protect the mask 101.
  • nickel and copper are selected as the under-metal metal electrode material.
  • the wafer 10 and the mask 60 are placed in a deposition chamber, and a nickel metal and a copper metal are sequentially used by a physical vapor deposition process. The deposition, forming the desired under-ball metal electrode 103.
  • the above metal may only be deposited in the opening of the protective mask 101, i.e., the predetermined under-ball metal electrode 103 is formed to achieve selective vapor deposition.
  • the mask sheet 60 described above can be repeatedly used, has superior economical efficiency compared with electroless plating, and has the advantages of high deposition speed inherent in vapor deposition and short process flow. The subsequent process is exactly the same as the pre-existing embodiment, and details are not described herein again.
  • the semi-finished product of the wafer 10 may be first baked or surface-activated before screen printing. Plasma treatment.
  • the present invention has been disclosed in the preferred embodiments as described above, but it is not intended to limit the invention, and the present invention may be utilized by the method and technical contents disclosed above without departing from the spirit and scope of the invention.
  • the technical solutions make possible changes and modifications, and the technical features having the differences in the above three embodiments are mutually replaced. Therefore, any content that does not deviate from the technical solutions of the present invention belongs to the protection scope of the technical solution of the present invention.

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Abstract

本发明提供了一种芯片封装方法，包括步骤：提供半封装晶圆，所述半封装晶圆上具有切割道以及芯片的金属焊垫；在切割道上形成第一保护层；在金属焊垫上形成球下金属电极；在所述球下金属电极上形成焊球；沿所述切割道对晶圆进行划片。本发明所述的第一保护层能够使得切割道内的金属不被电镀析出，且在切割后能够保护分立芯片的侧面，工艺流程简单，提高了封装效率以及成品率。

Description

芯片封装方法 本申请要求于 2010年 11 月 05 日提交中国国家知识产权局、 申请号为 201010534388.5、 发明名称为"芯片封装方法"的中国专利申请的优先权， 其全 部内容通过引用结合在本申请中。 技术领域
本发明涉及半导体技术领域， 尤其涉及一种晶圆级的芯片封装方法。 背景技术
晶圆级芯片尺寸封装（ Wafer Level Chip Size Packaging, WLCSP )技术是 对整片晶圆进行封装测试后再切割得到单个成品芯片的技术，封装后的芯片尺 寸与棵片完全一致。晶圆级芯片尺寸封装技术彻底颠覆了传统封装如陶瓷无引 线芯片载具 ( Ceramic Leadless Chip Carrier ) 、 有机无引线芯片载具（Organic Leadless Chip Carrier ) 的模式， 顺应了市场对微电子产品日益轻、 小、 短、 薄 化和低价化要求。经晶圆级芯片尺寸封装技术封装后的芯片尺寸达到了高度微 型化， 芯片成本随着芯片尺寸的减小和晶圆尺寸的增大而显著降低。 晶圆级芯 片尺寸封装技术是可以将 IC设计、 晶圆制造、 封装测试、 整合为一体的技术， 是当前封装领域的热点和未来发展的趋势。
中国发明专利申请第 200610096807.5号公开了一种基于晶圆级芯片尺寸 的封装方法， 主要包括如下工艺步骤：
首先如图 1所示， 将半导体晶圆 1与同样尺寸的第一玻璃基板 2粘接， 这样 在封装的初始阶段， 所述晶圆表面的器件部分将被基板盖住保护， 减少了外界 的污染和损害。
如图 2所示， 对半导体晶圆 1相对于第一玻璃基板 2的背面进行减薄， 并利 用光刻技术以及等离子刻蚀对所述晶圆背面进行选择性刻蚀， 形成多个 V形沟 槽作为切割道， 并暴露出部分芯片焊垫 11 (即芯片电极） 。
如图 3所示， 用绝缘介质填充所述 V形沟槽， 并在所述晶圆背面压合第二 - 玻璃基板 3以及焊料掩模 4。所述第二玻璃基板 3用于支撑半导体晶圆 1 , 而电热 绝缘焊料 4则用于在后续的机械切割工艺中起机械緩冲保护半导体晶圆 1的作 用。
如图 4所示， 采用机械切割工艺半切割原 V形沟槽所在位置 （不穿透分离 芯片） ， 形成新的 V形沟槽作为晶圆的切割道， 且使得芯片焊垫 11从 V形沟槽 的侧面暴露。
如图 5所示， 然后采用电镀工艺制作外引线 12, 所述外引线 12—端在 V形 沟槽内与芯片焊垫 n连接， 另一端延伸至晶圆背面， 所述芯片焊垫 11的电性功 能通过外引线 12而延伸至晶圆背面。
如图 6所示， 在晶圆背面选择性形成绝缘保护层 14, 露出部分外引线 12, 在露出的外引线 12上制作焊接凸点 15, 将上述晶圆沿其背面的 V形沟槽切割划 片， 形成分立芯片， 然后再对分立芯片进行外壳的封装， 最终完成芯片的封装 工艺。
现有的晶圆级芯片封装方法存在如下问题：在采用电镀工艺制作外引线 12 时， 切割道内 （例如上述专利所述的 V形沟槽内 )的金属也容易电镀析出而导 致各连线之间发生短路。 此外在切割后， 分立芯片的侧面也即原 V形沟槽的侧 壁， 暴露于外界环境中， 在进行外壳封装时容易受到损伤， 导致外引线断路， 进而影响芯片的成品率。 发明内容 本发明解决的技术问题是提供一种芯片封装方法，可以提高封装效率以及 成品率。 本发明提供的芯片封装方法， 包括步骤：
提供半封装晶圆， 所述半封装晶圆上具有切割道以及芯片的金属焊垫； 在所述金属焊垫上形成球下金属电极；
在所述球下金属电极上形成焊球；
沿切割道对晶圆进行划片；
还包括在切割道上方形成第一保护层的步骤。
优选的， 所述第一保护层的宽度大于切割道的宽度。 所述切割道的宽度为 替换页 （细则第 26条) 30~80μηι, 所述第一保护层的宽度为 50~120μηι。
可选的， 所述第一保护层为热固性环氧树脂， 采用丝网印刷技术形成。 可选的， 所述形成球下金属电极的方法为无电解电镀。所述无电解电镀包 括：对晶圆表面先进行锌酸盐清洗处理，再无电解电镀镍，然后无电解电镀金， 电镀厚度分别为 3μηι以及 0.05μηι。
可选的， 所述形成球下金属电极的方法为选择性气相沉积。
所述选择性气相沉积包括： 在晶圆表面设置掩模板， 所述掩模板露出晶圆 上需形成球下金属电极的位置； 采用物理气相沉积工艺，依次沉积镍金属以及 铜金属。
优选的， 在形成球下金属电极后， 还包括采用丝网印刷技术在晶圆上、 球 下金属电极以外区域形成第二保护层的步骤。 所述第二保护层的厚度为 5μηι~50μιη。
可选的， 所述第二保护层的材质为热固性树脂， 采用丝网印刷技术形成。 所述丝网印刷时， 保持晶圆的温度低于所述热固性环氧树脂的固化温度。 所述形成第二保护层后，还包括采用等离子刻蚀去除覆于球下金属电极顶部表 面的热固性环氧树脂的步骤。
可选的， 所述形成第二保护层后， 还包括研磨晶圆表面的步骤。
所述研磨采用机械研磨， 具体包括： 将晶圆放置于固定工作台； 将柔软度 小于晶圆的非织造布缠绕于研磨盘上， 并紧贴晶圆表面； 然后使用研磨液浸润 所述非织造布， 进行机械研磨。
优选的， 所述热固性树脂的固化温度小于 200°C。
所述热固性树脂中包含固化填充剂，所述固化填充剂的颗粒直径小于环氧 树脂印刷厚度的 1/3。
优选的， 所述热固性树脂的印刷厚度为 15μηι, 固化填充剂的颗粒直径小 于 5μηι, 固化后形成的第二保护层平均厚度为 11μηι~12μιη。
优选的，在进行丝网印刷技术时， 先对晶圆进行烘烤处理或者进行表面活 性化的等离子处理。
本发明所述封装方法利用丝网印刷技术在切割道上形成第一保护层，具体 的可以选择热固性环氧树脂作为保护层材料，一方面在采用电镀工艺形成球下 金属电极时， 能够防止切割道内的金属被电镀析出； 另一方面在划片后， 能够 替换页 （细则第 26条) 保护分立芯片的侧面， 尤其是金属引线， 不受到损伤。 本发明工艺流程筒单， 成本低廉， 且提高了封装效率以及封装成品率。 附图说明 通过附图中所示的本发明的优选实施例的更具体说明，本发明的上述及其 他目的、特征和优势将更加清晰。 附图中与现有技术相同的部件使用了相同的 附图标记。 附图并未按比例绘制， 重点在于示出本发明的主旨。 在附图中为清 楚起见， 放大了层和区域的尺寸。 图 1至图 6为现有的一种晶圆级的芯片封装方法各步骤剖面示意图； 图 7为本发明所述封装方法的基本流程图； 图 8为本发明第一实施例的流程示意图；
图 9、 图 11、 图 13、 图 14、 图 15、 图 16为图 8所示部分步骤的示意图； 图 10为图 9的俯视示意图；
图 12为图 11的俯视示意图； 图 17为本发明第二实施例的流程示意图； 图 18至图 20为图 17所示部分步骤的示意图； 图 21为本发明第三实施例的流程示意图；
图 22以及图 23为图 21所示部分步骤的示意图。
具体实施方式 现有的晶圆级芯片封装方法，切割道内的金属容易在球下金属电极制作时 电镀析出而导致短路，且晶圆在划片后， 分立芯片的侧面暴露于外界环境中容 易受到损伤。本发明则采用丝网印刷技术在切割道上形成第一保护层以解决上 述问题。 下面结合附图对本发明进行具体说明。
本实施例提供的封装方法的基本流程示意图如图 7所示， 包括：
S101、 提供半封装晶圆。 具体的， 所述半封装晶圆包括： 形成有芯片的半 替换页 （细则第 26条) — D—
导体衬底、将晶圆划分成若干个独立芯片单元的切割道、位于半导体衬底上起 到绝缘保护作用且具有若干开口的保护掩模、 开口内曝露出芯片的金属焊垫。 所述保护掩模可以是聚酰亚胺等有机膜， 所述金属焊垫可以是铜、铝等常规的 互连金属。
S102、 在切割道上形成第一保护层， 具体的， 可以采用丝网印刷技术在切 割道上印刷所述第一保护层。
优选的， 所述第一保护层的宽度要大于切割道宽度， 使得划片后， 分立芯 片的侧面顶部边缘处也受到保护。 为降低工艺难度， 所述第一保护层可以采用 热固性树脂， 例如环氧树脂、 酚醛树脂、 脲醛树脂、 三聚氰胺 -甲醛树脂、 不饱和树脂、 聚氨酯、 聚酰亚胺等。
S103、 在所述金属焊垫上形成球下金属电极；
可以采用电镀或选择性气相沉积的方式在所述保护掩模开口内、金属焊垫 上形成所述球下金属电极。 其中， 可以采用无电解电镀以提高电镀的均匀性； 而采用选择性气相沉积， 则可以反复利用同一块金属掩模板以降低成本。 常见 的球下金属电极材料包括镍、 金、 铜、 铝、 钛、 钨、 铬或其合金、 组合等， 可 以根据球下金属电极的实际厚度尺寸限制选择相应材料，以满足工艺以及成本 需求。
为了进一步改善对晶圆的保护效果，提高封装的成品率，在形成球下金属 电极后，还可以在晶圆上采用丝网印刷技术形成第二保护层， 所述第二保护层 可以选用与第一层保护层相同的热固性树脂材料。通过调整丝网印刷所采用的 丝网版的开口区域， 可以选择所述第二保护层的具体形成位置。在形成第二层 保护层后， 通常还应当利用等离子刻蚀去除丝网印刷时， 因热固性树脂的流动 性而覆于球下金属电极顶部表面的部分第二保护层，并采用研磨工艺处理晶圆 的表面。 以暴露出球下金属电极顶部， 便于后续工艺进行焊球的制作。
S104、在所述球下金属电极上形成焊球。可以在球下金属电极的顶部先涂 覆焊料， 然后进行高温的回流， 形成所述焊球。 常见的焊料包括锡、 铅、 银、 铜、 锌等金属或其合金、 组合等。
S105、 沿所述切割道对晶圆进行划片， 形成分立的芯片。 通常采用宽度小于切割道的刀片进行机械切割，还可以采用激光切割。切 替换页 （细则第 26条) —o—
割后的分立芯片侧面以及顶部边缘均覆有第一保护层， 能够在后续封装过程 中，保护该处的金属布线避免受到损伤。 最后进行芯片外壳的封装完成本发明 所述芯片封装工艺。 为进一步阐述本发明之优点，以下结合说明书附图提供了本发明的三个具 体实施例。 第一实施例 图 8为本发明第一实施例的流程示意图， 而图 9至图 16为上述流程中各 步骤的示意图， 以下结合图 8对各步骤进行详细说明。 如图 9所示， 提供半封装晶圆 10, 所述半封装晶圆包括： 形成有芯片的 半导体衬底 100、 将晶圆划分成若干个独立芯片单元的切割道 200、 位于所述 半导体衬底 100上具有开口的保护掩模 101、 所述开口内曝露出芯片的金属焊 垫 102。 所述保护掩模 101可以是聚酰亚胺等有机膜， 所述金属焊垫 102可以 是铜、 铝等常规的互连金属。 需要指出的是， 上述半导体衬底 100 并非局限于单质硅或绝缘体上硅衬 底， 还应当包括制作于其上的半导体器件、 金属互连以及其他半导体结构。 所 述保护掩模 101即覆于上述半导体结构的表面，从而起到保护芯片的作用。所 述芯片的金属焊垫 102作为芯片的输入 /输出端的电极， 用于引出芯片的电性 功能。
图 10为上述半封装晶圆的俯视示意图， 可见所述晶圆上形成有格子状的 切割道 200, 上述切割道 200将晶圆划分成若干方片区域， 每个方片区域代表 一块独立的芯片。 所述切割道 200的截面形状可以为等腰梯形， 深度不宜过深 以免影响晶圆的钢型硬度。 本实施例中， 所述切割道 200 的开口宽度为 30~80μηι。 图 11为半封装晶圆的剖面示意图， 图 12为图 11的俯视示意图， 结合图 11以及图 12所示， 将上述半封装晶圆表面进行丝网印刷工艺， 在切割道 200 的上方形成第一保护层 301。 其中， 所述第一保护层 301如前例举的热固性树 月旨，本实施例中， 出于降低成本的考量，第一保护层 301优选热固性环氧树脂。 通过调整丝网印刷所使用的丝网版的开口，可以选择第一保护层 301的形成位 替换页 （细则第 26条) - / - 置。
具体的， 丝网印刷的工艺示意图如图 13所示， 包括： 将晶圆 10固定于印 刷装置中， 丝网版 20的底部， 在丝网版 20上涂抹液态的环氧树脂； 用刮刀 30按压丝网版 20以及晶圆 10, 使得液态的环氧树脂通过丝网版 20的开孔处 涂布至晶圆 10表面； 将丝网版 20从晶圆 10上揭下， 这样液态的环氧树脂便 转录至晶圆 10上， 形成所需图案。 本步骤中， 上述丝网版 20的开孔对准晶圆 10上的切割道 200, 液态环氧 树脂渗入晶圆 10后， 将填充于切割道 200内， 加热所述晶圆 10至固化温度， 使得所述液态的环氧树脂固化以形成第一保护层 301。 此外为了使得第一保护 层 301的宽度大于切割道 200的宽度， 仅需使得丝网版 20的开孔宽度大于切 割道 200 的宽度即可， 本实施例中所述第一保护层 301 的宽度设置为 50~120μηι。 如图 14所示， 采用无电解电镀， 以第一保护层 301以及保护掩模 101作 为电镀掩模，在所述保护掩模 101的开口内，金属焊垫 102表面形成球下金属 电极 103。
具体的， 在本实施例中， 电镀前先对金属焊垫 102进行锌酸盐处理， 去除 其表面的氧化膜， 以降低接触电阻； 然后在金属焊垫 102上依次进行无电解镍 电镀以及无电解金电镀， 电镀厚度分别为 3μηι以及 0.05μηι, 最终形成凸出于 保护掩模 101表面的球下金属电极 103。 如图 15所示， 在球下金属电极 103的顶部， 采用焊料回流工艺制作焊球
104。 本实施例中， 出于降低成本的考量， 采用锡作为焊料材质。 具体包括： 将焊料锡膏涂覆于球下金属电极 103上， 然后进行高温回流，使得所述焊料锡 膏转变成焊球 104。 通常为了保持晶圆其他部分表面的平整性以及加强绝缘保 护， 还会在焊球 104以外的晶圆表面进行底部填充工艺。 如图 16所示，在完成焊球制作工艺后，沿切割道 200对晶圆 10进行划片， 形成分立的芯片。 具体的， 采用宽度小于第一保护层 301 的划片刀对晶圆 10 机械切割， 这样在切割后， 分立芯片的侧面以及边缘顶部覆有连续的第一保护 层 301 , 位于上述位置的金属引线或其他半导体结构均能够得到有效的保护。 替换页 （细则第 26条) ：二实施例 图 17为本发明第二实施例的流程示意图， 而图 18至图 20为上述流程中 部分步骤的示意图， 以下结合图 17对各步骤进行详细说明。 参照图 17 , 本实施例的基本步骤包括： 提供半封装晶圆； 采用丝网印刷 技术在切割道上印刷第一保护层；采用无电解电镀在金属焊垫上形成球下金属 电极； 在晶圆表面、 球下金属电极以外区域形成第二保护层； 对晶圆表面进行 研磨以及等离子刻蚀工艺处理； 在球下金属电极上形成焊球； 沿切割道对晶圆 划片。
与图 8相比， 本实施例与第一实施例相比， 区别仅在于： 在无电解电镀 形成球下金属电极后，还包括在晶圆表面球下金属电极以外区域形成第二保护 层以及进行相关工艺的步骤。 所述第二保护层能够进一步保护晶圆 10, 并在 后续焊球制作工艺中， 不用进行底部填充， 筒化了工艺流程， 同时如果采用深 色树脂 （环氧树脂即典型的深色树脂）， 还可以防止因外界光照引发光电效应 产生的芯片电路故障。 如图 18所示， 以第一实施例中图 14所示的半封装晶圆结构为基础， 采用 丝网印刷技术在晶圆 10上形成第二保护层 302。 具体的， 为降低工艺成本， 所述第二保护层 302 可以选用与第一保护层 301相同的材料， 例如热固性环氧树脂。 但与填充于切割沟道 200内的第一保 护层 301 不同的是， 所述第二保护层 302 为薄膜结构， 所需厚度仅为 5μηι~50μιη。 为了保证第二保护层 302的薄膜均匀性， 需要在丝网印刷的过程 中保持热固性环氧树脂的流动性， 即保证晶圆 10的温度低于热固性环氧树脂 的固化温度。 所述丝网印刷的具体工艺可以参考图 13形成第一保护层 301的图示， 可 选的， 变更丝网版 20的图案， 使得液态的热固性环氧树脂涂布至晶圆 10上、 球下金属电极 103以外的区域， 然后加热固化形成所需的第二保护层 302。 本实施例中， 为降低工艺难度， 所述环氧树脂的固化温度小于 200°C。 为 了改善环氧树脂的固化性能，通常环氧树脂中还包含固化填充剂， 例如含有二 氧化硅或其他固体颗粒的填充剂。 所述填充剂颗粒直径应当小于印刷厚度的 替换页 （细则第 26条) 1/3 , 以实现薄膜印刷的均匀性以及平整度需求，从而减少晶圆 10表面的翘曲。 所述印刷厚度通过调节丝网版 20的乳剂厚度进行控制。 本实施例中， 进行丝 网印刷时， 液态的环氧树脂的印刷厚度为 15μηι, 而填充剂颗粒直径最大不得 超过 5μηι, 环氧树脂固化后形成的第二保护层 302 的平均厚度可以控制在 11μηι~12μιη。
在丝网印刷过程中， 由于液态环氧树脂具有流动性，依然难免会渗入球下 金属电极 103区域。这样会存在如下问题： 当在球下金属电极 103顶部制作焊 球时，所述位于球下金属电极 103顶部表面的环氧树脂将使得焊球与球下金属 电极 103的接触面积减小，从而阻碍焊球与球下金属电极 103的结合， 甚至可 能在封装后的可靠性实验以及衬底跌落实验中导致焊球的脱落， 产生不良影 响。 因此在形成第二保护层 302后，通常需要利用研磨对晶圆 10作表面处理， 去除上述残渣。 所述研磨可以是机械或化学研磨等， 如图 19所示， 本实施例中， 所采用 的具体的研磨工艺包括： 将晶圆 10放置于固定工作台； 将柔软度小于晶圆的 非织造布 40缠绕于研磨盘 50上， 并紧贴晶圆 10表面； 然后使用研磨液浸润 所述非织造布 40, 进行机械研磨， 去除附着于晶圆 10表面的残渣物质。 作为另一个可选方案， 在研磨结束后， 如图 20所示， 还可以进行等离子 刻蚀工艺， 进一步去除上述覆于球下金属电极 103顶部表面的环氧树脂。上述 等离子刻蚀工艺的刻蚀气体包含氧气，能够与固化的环氧树脂发生反应生成气 体而除去。 在进行完上述工艺后，便进入焊球制作以及划片等后续工艺， 与第一实施 例相同， 此处不再赘述。 第三实施例 图 21为本发明第二实施例的流程示意图， 而图 22以及图 23为上述流程 中部分步骤的示意图， 以下结合图 21进行详细说明。 参照图 21 , 本实施例基本步骤包括： 提供半封装晶圆、 采用丝网印刷技 术在切割道上印刷第一保护层；采用选择性气相沉积在金属焊垫上形成球下金 属电极； 在晶圆表面、 球下金属电极以外区域形成第二保护层； 对晶圆表面进 替换页 （细则第 26条) 一丄 ΰ一
行研磨以及等离子刻蚀工艺处理； 在球下金属电极上形成焊球； 沿切割道对晶 圆划片。
与图 8以及图 17相比较， 本实施例与前述两实施例的区别在于： 形成球 下金属层的方法不同。 具体的， 采用选择性气相沉积在晶圆 10上的预定位置 处形成球下金属电极， 代替无电解电镀。
如图 22所示， 以第一实施例中图 11所示的半封装晶圆结构为基础， 首先 在晶圆 10的表面设置掩模板 60, 所述掩模板 60可以是金属掩模板， 紧贴于 晶圆 10上， 且上述掩模板 60上形成有开口， 所述掩模板 60上的开口对准晶 圆 10表面保护掩模 101的开口。 本实施例中， 选用镍以及铜作为球下金属电极材料， 如图 23所示， 将上 述晶圆 10以及掩模板 60放置于沉积腔内， 采用物理气相沉积工艺，依次进行 镍金属以及铜金属的沉积， 形成所需的球下金属电极 103。 由于掩模板 60的 存在， 上述金属仅可能沉积于保护掩模 101的开口内， 也即预定的球下金属电 极 103形成位置， 从而实现选择性气相沉积。 上述掩模板 60可以重复使用， 与无电解电镀相比较， 具有更为优异的经济性，且具有气相沉积所固有的沉积 速度快， 工艺流程短的优点。 后续工艺与前序实施例完全相同， 此处不再赘述。
此外，在上述各实施例中，为了提高丝网印刷工艺中热固性树脂的附着力， 通常在丝网印刷之前， 还可以先对上述晶圆 10的半成品进行烘烤处理， 或者 进行表面活性化的等离子处理。 本发明虽然已以较佳实施例公开如上，但其并不是用来限定本发明，任何 本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法 和技术内容对本发明技术方案做出可能的变动和修改，并对上述三实施例中具 有差异的技术特征互相进行替换， 因此， 凡是未脱离本发明技术方案的内容， 均属于本发明技术方案的保护范围。
替换页 （细则第 26条)

Claims

权 利 要 求
1.一种芯片封装方法， 其特征在于， 包括步骤：
提供半封装晶圆， 所述办封装晶圆上具有切割道以及芯片的金属焊垫； 在切割道上形成第一保护层；
在所述金属焊垫上形成球下金属电极；
在所述球下金属电极上形成焊球；
沿切割道对晶圆进行划片。
2.如权利要求 1所述的芯片封装方法， 其特征在于， 所述第一保护层的宽 度大于切割道的宽度。
3.如权利要求 2所述的芯片封装方法， 其特征在于， 所述切割道的宽度为 30~80μηι, 所述第一保护层的宽度为 50~120μηι。
4.如权利要求 1所述的芯片封装方法， 其特征在于， 所述第一保护层为热 固性环氧树脂、 采用丝网印刷技术形成。
5.如权利要求 1所述的芯片封装方法， 其特征在于， 所述形成球下金属电 极的方法为无电解电镀。
6.如权利要求 5所述的芯片封装方法，其特征在于，所述无电解电镀包括： 对晶圆表面先进行锌酸盐清洗处理； 在晶圆上无电解电镀镍， 然后无电解电镀 金。
7.如权利要求 6所述的芯片封装方法 , 其特征在于， 所述镍的电镀厚度为
3μηι, 金的电镀厚度为 0.05μηι。
8.如权利要求 1所述的芯片封装方法 , 其特征在于， 所述形成球下金属电 极的方法为选择性气相沉积。
9.如权利要求 8所述的芯片封装方法 , 其特征在于， 所述选择性气相沉积 包括：
在晶圆表面设置掩模板，所述掩模板露出晶圆上需形成球下金属电极的位 置； 以所述掩模板为掩模， 采用物理气相沉积工艺， 在晶圆上依次沉积镍金属 以及铜金属。
10. 如权利要求 1所述的芯片封装方法， 其特征在于， 在形成球下金属 电极后，还包括采用在晶圆上、球下金属电极以外区域形成第二保护层的步骤。 替换页 （细则第 26条) 12.
2—
11. 如权利要求 10所述的芯片封装方法， 其特征在于， 所述第二保护层 的厚度为 5μηι~50μιη„
12. 如权利要求 10所述的芯片封装方法， 其特征在于， 所述第二保护层 的材质为热固性环氧树脂， 采用丝网印刷技术形成。
13. 如权利要求 10所述的芯片封装方法， 其特征在于， 所述形成第二保 护层后， 还包括研磨晶圆表面的步骤。
14. 如权利要求 13所述的芯片封装方法， 其特征在于， 所述研磨采用机 械研磨， 具体包括：
将晶圆放置于固定工作台；
将柔软度小于晶圆的非织造布缠绕于研磨盘上， 并紧贴晶圆表面； 使用研磨液浸润所述非织造布， 进行机械研磨。
15. 如权利要求 12所述的芯片封装方法， 其特征在于， 所述形成第二保 护层后，还包括采用等离子刻蚀去除覆于球下金属电极顶部表面的热固性环氧 树脂的步骤。
16. 如权利要求 12所述的芯片封装方法， 其特征在于， 所述丝网印刷时， 保持晶圆的温度低于所述热固性环氧树脂的固化温度。
17. 如权利要求 12所述的芯片封装方法， 其特征在于， 所述热固性树脂 的固化温度小于 200 °C
18. 如权利要求 17所述的芯片封装方法， 其特征在于， 所述热固性树脂 中包含固化填充剂，所述固化填充剂的颗粒直径小于环氧树脂印刷厚度的 1/3
19. 如权利要求 18所述的芯片封装方法， 其特征在于， 所述热固性树脂 的印刷厚度为 15μηι, 固化填充剂的颗粒直径小于 5μηι, 固化后形成的第二保 护层平均厚度为 11μηι~12μιη
20. 如权利要求 4或 12任意所述的芯片封装方法， 其特征在于， 在进行 丝网印刷技术时， 先对晶圆进行烘烤处理或者进行表面活性化的等离子处理。
替换页 （细则第 26条)
PCT/CN2011/080874 2010-11-05 2011-10-18 芯片封装方法 WO2012059003A1 (zh)

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