Classifications

• • C—CHEMISTRY; METALLURGY
  • C03—GLASS; MINERAL OR SLAG WOOL
  • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
  • C03C23/00—Other surface treatment of glass not in the form of fibres or filaments
  • C03C23/0095—Solution impregnating; Solution doping; Molecular stuffing, e.g. of porous glass
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
  • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
• • C—CHEMISTRY; METALLURGY
  • C03—GLASS; MINERAL OR SLAG WOOL
  • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
  • C03C23/00—Other surface treatment of glass not in the form of fibres or filaments
  • C03C23/008—Other surface treatment of glass not in the form of fibres or filaments comprising a lixiviation step
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02002—Preparing wafers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02367—Substrates
  • H01L21/0237—Materials
  • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02439—Materials
  • H01L21/02441—Group 14 semiconducting materials
  • H01L21/0245—Silicon, silicon germanium, germanium
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02494—Structure
  • H01L21/02513—Microstructure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/02521—Materials
  • H01L21/02524—Group 14 semiconducting materials
  • H01L21/02532—Silicon, silicon germanium, germanium
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02656—Special treatments
  • H01L21/02658—Pretreatments
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
  • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
  • H01L21/2251—Diffusion into or out of group IV semiconductors
  • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
  • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
  • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T428/00—Stock material or miscellaneous articles
  • Y10T428/249921—Web or sheet containing structurally defined element or component
  • Y10T428/249953—Composite having voids in a component [e.g., porous, cellular, etc.]
  • Y10T428/249967—Inorganic matrix in void-containing component
  • Y10T428/249969—Of silicon-containing material [e.g., glass, etc.]

Definitions

• the present disclosure relates to dimensional silica-based porous silicon structures and, more particularly, to methods of fabricating the structures.
• a method of fabricating a dimensional silica-based structure comprising a porous silicon layer is provided.
• oxygen is extracted from the atomic elemental composition of a silica glass substrate by reacting a metallic gas with the substrate in a heated inert atmosphere to form a metal-oxygen complex along a surface of the substrate.
• the metal-oxygen complex is removed from the surface of the silica glass substrate to yield a crystalline porous silicon surface portion and one or more additional layers are formed over the crystalline porous silicon surface portion of the silica glass substrate to yield a dimensional silica-based structure comprising the porous silicon layer.
• the substrate is glass-based, but is not necessarily a silica-based glass substrate. Additional embodiments are disclosed and claimed.
• FIG. 1-3 illustrate schematically a method of fabricating a dimensional silica-based porous silicon structure according to one embodiment of the present disclosure
• FIG. 4 illustrates a dimensional silica-based porous silicon structure according to an alternative embodiment of the present disclosure
• FIG. 5 illustrates schematically a silicon-on-insulator structure incorporating a silica- based porous silicon layer according to the present disclosure
• FIG. 6 illustrates schematically a photovoltaic cell incorporating a silica-based porous silicon layer according to the present disclosure.
• Figs. 1-3 of the present disclosure describe the fabrication methodology of the present disclosure with reference to a silica glass substrate and a Mg-based metallo -thermic reduction process, although the scope of the present disclosure extends well beyond specific metallo- thermic reduction processes. More specifically, according to the illustrated fabrication methodology, a dimensional silica-based structure comprising a porous silicon layer can be fabricated by extracting oxygen from the atomic elemental composition of a silica glass substrate 10.
• the silica glass substrate 10 may be a high purity fused silica substrate, an alkaline earth alumina borosilicate glass, or any type of glass comprising silica.
• Oxygen is extracted from the silica glass substrate 10 by reacting a metallic gas Mg with the silica glass substrate 10 in a heated inert atmosphere 20 to form a metal-oxygen complex 30 along a surface of the silica glass substrate 10.
• reaction temperature T which, in the case of many silica glass substrates, will be between
• a suitable reaction temperature T will be approximately 675 °C or slightly less and can be maintained for approximately two hours.
• the silica glass substrate 10 can be characterized by a thermal strain point and the inert atmosphere 20 can be heated to a reaction temperature below the thermal strain point of the silica glass substrate 10.
• the inert atmosphere can be heated to about 660°C. Reduced reaction temperatures are contemplated for low pressure reaction chambers.
• the silica glass substrate 10 may comprise any type of silica-based glass including, but not limited to high purity fused silica, aerogel glasses, alkaline earth alumina borosilicate glasses, which may include oxides of boron, phosphorous, titanium, germanium, zirconium, vanadium, etc., and which may or may not be fabricated to be free of added arsenic, antimony, barium, and halides.
• high purity fused silica is intended to encompass the compositions and purity levels of high purity fused silica commonly recognized in the art.
• the glass may be presented as a fusion drawn sheet of glass that can be a re-drawn, flexible glass sheet for silicon or silicon laminate substrates for roll-to-roll fabrication.
• the substrate is glass-based, but is not necessarily a silica-based glass substrate.
• alternative glass substrates may be provided using non- silica glass formers such as the oxides of boron, phosphorous, titanium, germanium, zirconium, vanadium, and other metallic oxides.
• suitable reduction gases can be utilized without departing from the scope of the present disclosure.
• the metallic reducing gas may comprise Mg, Na, Rb, or combinations thereof. In a simplified, somewhat ideal case, where the metallic gas comprises Mg, the corresponding stoichiometric reaction with the silica glass substrate is as follows:
• reaction byproducts like Mg 2 Si are generated and the reducing step described above can be followed by the byproduct removal steps described herein.
• the stoichiometry of the reduction can be tailored such that the metallic gas is provided in an amount that is not sufficient to generate the byproduct.
• the composition of the glass will be such that the generation of additional reaction byproducts is inevitable, in which case these additional byproducts can be removed by the etching and thermal byproduct removal steps described herein.
• the substrate 10 can be subject to microwave or RF exposure while reacting the metallic gas with the silica glass substrate 10.
• the metallic gas can be derived from any conventional or yet to be developed source including, for example, a metal source subject to microwave, plasma or laser sublimation, an electrical current, or a plasma arc to induce metal gas formation.
• a metal source subject to microwave, plasma or laser sublimation, an electrical current, or a plasma arc to induce metal gas formation.
• the composition of the metal source can be varied while reacting the metallic gas with the silica glass substrate to further enhance reduction.
• Contemplated dosages include, but are not limited to, dosages from approximately 10 kGy to approximately 75 kGy, with acceleration voltages of approximately 125 KV. Higher dosages and acceleration voltages are contemplated and deemed likely to be advantageous.
• the metal-oxygen complex 30 that is formed along the surface of the silica glass substrate 10 is removed from the surface of the silica glass substrate 10 to yield a crystalline porous silicon surface portion forming a porous silicon layer 40.
• the metal-oxygen complex 30 can be removed from the surface of the silica glass substrate 10 by executing a post-reaction acid etching step.
• some additional MgO may be trapped inside the glass and additional etching may be needed for longer periods of time with multiple flushes of the acidic mixture.
• one or more additional layers 50 can be formed over the crystalline porous silicon surface portion of the silica glass substrate 10 to yield a dimensional silica-based structure 100 including the porous silicon layer 40.
• the additional layer 50 comprises a semiconductor or crystalline overlayer and the porous silicon layer 40 is used as a seed layer for the epitaxial growth or deposition of the overlayer. It is contemplated that the eptixially grown or deposited layer may, for example be silicon, germanium, or another semiconductor or crystalline material.
• the method may further comprise the step of recrystallizing the additional layer 50 by annealing the layer 50 at a temperature and duration sufficient to enhance crystallization and increase grain size in the overlayer. It is contemplated that conventional annealing configurations as well as localized laser or torch annealing may be suitable. Typically, the porous silicon layer 40 will increase the degree of crystallization of the epitaxially grown or deposited silicon layer 50.
• the silicon that is epitaxially grown or deposited onto the porous silicon on glass template may have grain sizes from about 10 nm up to tens of microns such as > 20 um.
• monocrystalline silicon also sometimes referred to as single crystal silicon
• Polycrystalline silicon is composed of many smaller silicon grains of varied crystallographic orientation.
• Microcrystalline silicon sometimes also known as nanocrystalline silicon, is a form of porous silicon that is similar to amorphous silicon, in that it has an amorphous phase.
• microcrystalline silicon has small grains of crystalline silicon within the amorphous phase. This is in contrast to polycrystalline silicon which consists solely of crystalline silicon grains, separated by grain boundaries.
• a silica glass substrate 70 that is not high purity fused silica, i.e., a silica glass substrate including dopants, additives, or other impurities.
• alumina boro silicate glass substrates are the subject of widespread use in the industry.
• silica glass substrates include additives such as boron, phosphorous, titanium, germanium, zirconium, vanadium, etc.
• the separation layer 60 may comprise a silicon nitride dielectric layer.
• the porous silicon layer 40 is used as a seed layer for the epitaxial fabrication of the silicon-on-insulator structure including the porous silicon layer 40. It is contemplated that dimensional silica-based structures according to the present disclosure can also be arranged to form a photovoltaic cell 300 (see Fig. 6), a thermoelectric cell, and other similar structures.
• dimensional silica-based structures can be arranged to form a silicon-based optoelectric device, e.g., a light emitting device, a waveguide, a photonic crystal, or a solar cell.
• the structure will be formed over a silica glass substrate including significant amounts of dopants, additives or other impurities, like an alumina borosilicate glass substrate.
• a separation layer similar to that described above with reference to Fig. 4 will be incorporated in the structure.
• dimensional silica-based structures according to the present disclosure can be arranged to form an environmental interface device, which, for the purposes of describing and defining the present invention, is a device that is configured to alter, be altered by, or otherwise interface with an external environmental component such as air, water, an external body, etc.
• an external environmental component such as air, water, an external body, etc.
• the environmental interface device may be a micro -reactor, filter media, or a gas sensor, in which case the porous silicon layer in the active structure of the environmental interface device would comprise a catalytic, zeolite, or other active layer of the device. Additional environmental interface devices are contemplated where the porous silicon layer is configured as a hydrophobic layer, an anti-fingerprint contact layer, or a chemically resistant or strength-enhanced surface layer.
• the silica glass substrate is configured to comprise N-type or P-type dopants and the oxygen extraction and the metal-oxygen complex removal steps are tailored to leave significant amounts of dopants in the crystalline porous silicon surface portion of the silica glass substrate.
• dopants if present in sufficient amounts, can contribute dopants to the additional layers formed over the crystalline porous silicon surface portion of the silica glass substrate.
• typical dopants include but are not limited to Al, P, B, and As.
• N-type or P-type dopants can be introduced into the crystalline porous silicon surface portion of the silica glass substrate by conventional diffusion or ion implantation techniques.
• the silica glass substrate can be provided with a topical film for controlling the thickness, porosity or crystalline character of the resulting crystalline porous silicon surface portion of the silica glass substrate.
• these topical films can be silicates, phosphates, or any glass former including, but not limited to, the oxides of boron, phosphorous, titanium, germanium, zirconium, vanadium, and other metallic oxides.
• a topical film can be formed on the glass through atomic layer deposition (ALD), chemical vapor deposition (CVD) and its variants (such as PECVD, LPCVD, APCVD), molecular beam evaporation (MBE), sputter deposition, etc. It is also possible to form atomic layer deposition (ALD), chemical vapor deposition (CVD) and its variants (such as PECVD, LPCVD, APCVD), molecular beam evaporation (MBE), sputter deposition, etc. It is also, and not by way of limitation, a topical film can be formed on the glass through atomic layer deposition (ALD), chemical vapor deposition (CVD) and its variants (such as PECVD, LPCVD, APCVD), molecular beam evaporation (MBE), sputter deposition, etc. It is also to form atomic layer deposition (ALD), chemical vapor deposition (CVD) and its variants (such as PECVD
• the surface of the silica glass substrate may be provided with grooves, raised features or other texturing to yield specific optical or combined opto-electronic properties, such as optical scattering.
• the starting substrate glass composition may be tailored to enhance thermal processing capabilities, e.g., JADETM glass contains barium and is stable up to 725 °C.
• the glass composition may be chosen to enhance optical transparency, polarizability, or shock resistance.
• dimensional silica-based structures can be densified by coating the crystalline porous silicon surface portion of the silica glass substrate with an additional glass or metal oxide layer and reacting a metallic gas with the crystalline porous surface portion of the glass substrate at the reaction temperature to yield a densified oxygen substrate.
• This process can be repeated a plurality of times with relatively thin, e.g., 10 nm to 300 nm, glass or metal oxide layers, under the various metallo -thermic reaction conditions described herein.
• One or more inert blocking layers can be provided over the silica glass substrate, prior to reacting the metallic gas with the silica glass substrate, to facilitate overlayer patterning.
• a graphite blocking layer could be used in a patterning step.
• fabrication methods according to the present disclosure could incorporate a reducing agent doping step where the silica glass substrate is pre-treated with a gaseous reducing agent to infiltrate the surface of the silica glass substrate with the reducing agent and enhance the reaction of the metallic gas and the silica glass substrate.
• the silica glass substrate may be exposed to pressurized hydrogen and an inert carrier gas in a Parr vessel for quicker and more complete topical reduction.
• Fabrication methods according to the present disclosure could also incorporate a post- reaction acid etching step for the removal of amorphous silicon from the porous silicon, e.g., by HF etching or other conventional or yet-to-be developed acid etching protocols. It is contemplated that the post-reaction acid etching step will, in many cases, yield crystalline porous silicon characterized by X-ray diffraction spectra dominated by a preferential ⁇ 111> crystalline orientation.
• Fabrication methods according to the present disclosure could further incorporate one or more post-reaction thermal treatment steps.
• substrates including porous silicon layers according to the present disclosure can be treated in an inert atmosphere at a post-reaction temperature exceeding the reaction temperature. More specifically, a substrate processed for 2 hours at 675 °C and etched in 1M HCL for 2 hours can be subject to post-reaction thermal treatment in Ar for 6 hours at 725 °C.
• the post-reaction temperature will be above 700°C, e.g., between 725°C and 750°C, and will be maintained for several hours.
• the post-reaction treatment is typically maintained for approximately 6 hours for complete removal of Mg 2 Si.
• post-reaction treatment is typically maintained for more than approximately 18 hours and can be executed intermittently at intermediate 6 hour treatment steps.
• the post reaction thermal treatment can be maintained for a period of time that is sufficient to evaporate the metal-non-oxygen complex as well.
• a "dimensional" substrate or a “dimensional” structure is one where the dimensions of the substrate or structure have a predefined utilitarian shape and size, i.e., a shape and size designed for a particular utility.
• Dimensional substrates and structures may be fully functional structures, intermediate structures, partially functional structures, precursor substrates or structures, or seed substrates or structures for the formation of intermediate, partially or fully functional structures.
• Dimensional substrates and structures can, for example, be distinguished from powders, grains, or other types of coarse or fine particulate matter of undefined, pseudo-random, or otherwise indeterminate shape.
• Dimensional substrates and structures can also be distinguished from nano structures or nanoparticles.
• dimensional substrates and structures include, but are not limited to seed substrates or sheet layers for structure growth, thin film transistors, photovoltaic cells, thermoelectric cells, light emitting devices, waveguides, photonic crystals, solar cells, and other similar structures.
• porous silicon is a form of the chemical element silicon having a distribution of nanoscale sized voids in its micro structure, rendering a relatively large surface to volume ratio, in some cases greater than 500m 2 /g. It is also noted that recitations herein of "at least one" component, element, etc., should not be used to create an inference that the alternative use of the articles "a” or “an” should be limited to a single component, element, etc.

Landscapes

• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Chemical & Material Sciences (AREA)
• Materials Engineering (AREA)
• General Chemical & Material Sciences (AREA)
• Chemical Kinetics & Catalysis (AREA)
• Organic Chemistry (AREA)
• Life Sciences & Earth Sciences (AREA)
• Geochemistry & Mineralogy (AREA)
• Crystallography & Structural Chemistry (AREA)
• Metallurgy (AREA)
• Mechanical Engineering (AREA)
• Recrystallisation Techniques (AREA)
• Surface Treatment Of Glass (AREA)
• Silicon Compounds (AREA)
• Glass Compositions (AREA)
• Laminated Bodies (AREA)
• Photovoltaic Devices (AREA)

Priority Applications (5)

Applications Claiming Priority (4)

Publications (2)

Family

ID=45697815

Family Applications (1)

Country Status (8)

Cited By (2)

Families Citing this family (12)

Family Cites Families (8)

• 2011
  • 2011-05-04 US US13/100,593 patent/US8415555B2/en not_active Expired - Fee Related
  • 2011-08-11 CN CN201180040775.6A patent/CN103069055B/zh not_active Expired - Fee Related
  • 2011-08-11 JP JP2013525950A patent/JP5878535B2/ja not_active Expired - Fee Related
  • 2011-08-11 AU AU2011293715A patent/AU2011293715A1/en not_active Abandoned
  • 2011-08-11 EP EP11820371.0A patent/EP2609234A4/en not_active Withdrawn
  • 2011-08-11 KR KR20137002957A patent/KR20130108531A/ko not_active Ceased
  • 2011-08-11 WO PCT/US2011/047367 patent/WO2012027121A2/en not_active Ceased
  • 2011-08-24 TW TW100130322A patent/TWI560163B/zh not_active IP Right Cessation
• 2013
  • 2013-03-20 US US13/847,740 patent/US20130209781A1/en not_active Abandoned

Non-Patent Citations (3)

Also Published As

Similar Documents

Legal Events