WO2012020565A1 - Substrat semiconducteur, dispositif semiconducteur et procédé de production d'un substrat semiconducteur - Google Patents

Substrat semiconducteur, dispositif semiconducteur et procédé de production d'un substrat semiconducteur Download PDF

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WO2012020565A1
WO2012020565A1 PCT/JP2011/004506 JP2011004506W WO2012020565A1 WO 2012020565 A1 WO2012020565 A1 WO 2012020565A1 JP 2011004506 W JP2011004506 W JP 2011004506W WO 2012020565 A1 WO2012020565 A1 WO 2012020565A1
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layer
crystal layer
atom
crystal
semiconductor substrate
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Japanese (ja)
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洋幸 佐沢
秦　雅彦
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住友化学株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • the present invention relates to a semiconductor substrate, a semiconductor device, and a method for manufacturing a semiconductor substrate.
  • Nitride semiconductors such as GaN and AlGaN have features such as a high breakdown voltage, a high saturation drift velocity, chemical and thermal stability, and a large band gap. For this reason, nitride semiconductors such as GaN and AlGaN are expected to be used for power switching devices, devices capable of operating at high temperatures, blue or green light-emitting devices, etc., taking advantage of these characteristics.
  • a nitride semiconductor When epitaxially growing a nitride semiconductor, it is preferable to use an inexpensive silicon substrate as a base substrate for crystal growth.
  • an inexpensive silicon substrate As a problem that the difference in thermal expansion coefficient between the silicon crystal and the nitride semiconductor crystal is large, and cracks are likely to occur in the epitaxially grown crystal layer.
  • a technique has been proposed in which a nitride semiconductor crystal layer is not partially grown on the entire surface of a silicon substrate but is partially formed.
  • Patent Document 1 discloses a technique for epitaxially growing a group III nitride semiconductor composed of Al x Ga y In 1-xy N (where 0 ⁇ x, y ⁇ 1, 0 ⁇ x + y ⁇ 1) on a Si substrate. Is disclosed. In Patent Document 1, when a group III nitride semiconductor is epitaxially grown on a Si substrate, a mask made of a Si thermal oxide film is formed on the Si substrate, and a group III nitride semiconductor is selectively epitaxially grown on the exposed portion of Si. Is described. Patent Document 1 Japanese Patent Application Laid-Open No. 11-274082
  • the silicon oxide film causes epitaxial growth of a nitride semiconductor crystal. It functions as an inhibition layer to inhibit, and a nitride semiconductor crystal can be epitaxially grown selectively only inside the opening. Since the epitaxially grown nitride semiconductor crystal is formed not only on the entire surface of the silicon substrate but inside the opening, the effect of suppressing the occurrence of cracks in the nitride semiconductor crystal can be expected.
  • atoms constituting the inhibition layer may be taken into the epitaxial growth layer. It is well known that atoms taken into the semiconductor crystal layer function as impurities. For example, when Si or O is taken into a GaN crystal or AlGaN crystal, it becomes an n-type impurity.
  • FIG. 1 is secondary ion mass spectrometry (SIMS) data that was experimentally evaluated to evaluate how much Si and O atoms are incorporated into the GaN layer.
  • FIG. 1 is a SIMS depth profile of a GaN layer that has been selectively epitaxially grown using a silicon oxide film as an inhibition layer.
  • a solid line indicates a depth profile of O atoms
  • a broken line indicates Si atoms
  • a dashed line indicates a Ga atom.
  • the concentration scale on the left side of the vertical axis corresponds to the scale of secondary ion intensity on the right side of the vertical axis for Ga atoms.
  • the vicinity of a depth of 0.5 ⁇ m where the secondary ion intensity of Ga atoms is reduced is the interface between the substrate and the GaN layer.
  • the GaN layer is from the depth of about 0.5 ⁇ m to the surface of the depth of 0 ⁇ m. Although it is not uniform in the depth direction of the GaN layer, O atoms and Si atoms are not less than 1 ⁇ 10 18 cm ⁇ 3 , and depending on the depth, impurity atoms near 1 ⁇ 10 20 cm ⁇ 3 may be incorporated. Recognize.
  • the object of the present invention is to increase the resistance even when a semiconductor crystal contains Si atoms or O atoms in the crystal, such as a nitride semiconductor crystal selectively epitaxially grown using an inhibition layer. It is an object of the present invention to provide a semiconductor crystal that can be used for an electronic device that needs to be controlled.
  • a base substrate and a first crystal layer formed on or above the base substrate are included, and the first crystal layer includes oxygen atoms and Provided is a semiconductor substrate which is a group 3-5 compound semiconductor layer including a first atom which is at least one atom selected from the group consisting of silicon atoms and a second atom which is at least one atom which functions as an acceptor. .
  • the second atom is at least one atom selected from the group consisting of Mg atom, Zn atom, Be atom and C atom.
  • the semiconductor substrate may further include a second crystal layer formed above the first crystal layer and a third crystal layer formed between the first crystal layer and the second crystal layer.
  • the second crystal layer and the third crystal layer are Group 3-5 compound semiconductor layers, the third crystal layer has a second atom, and the total number of second atoms contained in the third crystal layer is equal to the first crystal layer. Less than the total number of second atoms contained in the crystal layer.
  • the second crystal layer may function as an active layer of a semiconductor active element formed using the semiconductor substrate.
  • the third crystal layer may be a depleted crystal layer.
  • the first crystal layer, the second crystal layer, and the third crystal layer may be a group 3-5 nitride semiconductor layer.
  • the semiconductor substrate may further include an inhibition layer formed on or above the base substrate.
  • the inhibition layer has an opening, the inhibition layer inhibits crystal growth, the inhibition layer includes first atoms, and the first crystal layer is formed in the opening.
  • the inhibition layer may be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.
  • a base substrate In a second aspect of the present invention, a base substrate, a first crystal layer formed on or above the base substrate, and an active layer formed on or above the first crystal layer,
  • One crystal layer includes a first atom that is at least one atom selected from the group consisting of an oxygen atom and a silicon atom, and a group 3-5 compound semiconductor that includes at least one atom that functions as an acceptor.
  • a semiconductor device that is a layer is provided.
  • an inhibition layer containing a first atom which is at least one atom selected from the group consisting of an oxygen atom and a silicon atom on or above a base substrate and inhibits crystal growth Forming an opening in the inhibition layer, and forming a first crystal layer of a group 3-5 compound semiconductor by epitaxial growth while introducing a second atom functioning as an acceptor into the opening.
  • the inhibition layer includes a first atom which is at least one atom selected from the group consisting of an oxygen atom and a silicon atom on or above the base substrate and inhibits crystal growth. , Forming an opening in the inhibition layer, forming a first crystal precursor layer of a Group 3-5 compound semiconductor in the opening by epitaxial growth, and at least one atom functioning as an acceptor And forming a first crystal layer by doping the first crystal precursor layer with a second atom that is a semiconductor substrate.
  • the inhibition layer may be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.
  • SIMS secondary ion mass spectrometry
  • An example of a cross section of a semiconductor substrate 100 is shown.
  • An example of a cross section of a semiconductor substrate 200 is shown.
  • An example of a cross section of a semiconductor substrate 300 is shown.
  • An example of a cross section of a field effect transistor 400 is shown.
  • the IV characteristic of a dope transistor is shown.
  • the IV characteristic of an undoped transistor is shown.
  • FIG. 2 shows a cross-sectional example of the semiconductor substrate 100.
  • the semiconductor substrate 100 has a base substrate 102 and a first crystal layer 104.
  • An arbitrary crystal layer may be formed between the base substrate 102 and the first crystal layer 104.
  • the base substrate 102 is a support substrate that supports an epitaxial growth layer formed thereon.
  • the base substrate 102 include a substrate whose surface is silicon, a sapphire substrate, a silicon carbide substrate, a zinc oxide substrate, and a GaAs substrate.
  • the surface is silicon means that at least the surface of the substrate has a region composed of silicon.
  • the base substrate 102 may be composed of silicon as a whole like a Si wafer, or may have a structure having a silicon layer on an insulating layer like a SOI (silicon-on-insulator) wafer. .
  • the base substrate 102 may be a substrate in which a silicon layer is formed on a substrate made of an element different from silicon, such as a sapphire substrate, a glass substrate, a silicon carbide substrate, a zinc oxide substrate, or a GaAs substrate.
  • the silicon of the base substrate 102 may contain impurities.
  • An extremely thin silicon oxide layer or silicon nitride layer such as a natural oxide layer may be formed on the silicon layer on the surface of the base substrate 102.
  • the first crystal layer 104 is formed on or above the base substrate 102. That is, the first crystal layer 104 may be formed in contact with the surface of the base substrate 102 or may be formed with another layer interposed between the first crystal layer 104 and the surface of the base substrate 102.
  • the first crystal layer 104 is a group 3-5 compound semiconductor layer. Examples of the first crystal layer 104 include GaAs, AlGaAs, InGaAs, InGaP, AlN, GaN, and AlGaN.
  • the first crystal layer 104 includes a first atom that is at least one atom selected from the group consisting of O atoms and Si atoms. The concentration of the first atoms in the first crystal layer 104 is 2 ⁇ 10 17 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less.
  • the first crystal layer 104 includes a second atom that is at least one atom that functions as an acceptor.
  • the second atom include at least one atom selected from the group consisting of Mg atom, Zn atom, Be atom, and C atom.
  • the second atom functions as an acceptor that generates holes in the first crystal layer 104.
  • the first crystal layer 104 includes both the first atom serving as a donor and the second atom serving as an acceptor, so that electrons generated by the first atom are compensated by holes generated by the second atom, The resistivity of the first crystal layer 104 can be increased.
  • the current flowing through the first crystal layer 104 is suppressed, and the characteristics of the first crystal layer 104 or the device formed thereon can be improved. For example, in the case of a field effect transistor, pinch-off characteristics or breakdown voltage is improved.
  • the concentration of the second atoms included in the first crystal layer 104 is preferably an excessive concentration sufficient to compensate for the mixed first atoms.
  • the excessive concentration also captures newly generated carriers (electrons) by voltage application during transistor operation, and makes the first crystal layer 104 highly insulating during the transistor operation. Concentration that can be maintained. By using such a concentration, an improvement in the pinch-off property of the transistor and an improvement in the on / off ratio can be expected.
  • the concentration of the second atom can be determined in the range of 1 ⁇ 10 14 cm ⁇ 3 to 1 ⁇ 10 21 cm ⁇ 3 .
  • the concentration of the second atoms included in the first crystal layer 104 is a concentration that is just enough to compensate for the mixed first atoms, a concentration that is slightly insufficient to compensate the first atoms, or the first atoms. However, the concentration may be such that the excess amount is excessively small. In these cases, the first crystal layer 104 has an n-type or p-type conductivity which is insulative or low in conductivity, and even in such a case, an effect can be expected.
  • FIG. 3 shows a cross-sectional example of the semiconductor substrate 200.
  • the semiconductor substrate 200 includes a base substrate 102, a first crystal layer 104, a second crystal layer 202, and a third crystal layer 204.
  • the base substrate 102 and the first crystal layer 104 in the semiconductor substrate 200 are the same as the base substrate 102 and the first crystal layer 104 in the semiconductor substrate 100.
  • the second crystal layer 202 is formed above the first crystal layer 104.
  • the second crystal layer 202 functions as an active layer of the semiconductor active element.
  • the semiconductor active element refers to an element formed using the semiconductor substrate 200. That is, when the semiconductor active element is formed using the semiconductor substrate 200, the second crystal layer 202 has a characteristic that can function as an active layer of the semiconductor active element.
  • the third crystal layer 204 is formed between the first crystal layer 104 and the second crystal layer 202.
  • the second crystal layer 202 and the third crystal layer 204 are group 3-5 compound semiconductor layers. Examples of the second crystal layer 202 include GaAs, AlGaAs, InGaAs, InGaP, AlGaN, or GaN.
  • the second crystal layer 202 may not be a single layer.
  • it may be a heterojunction crystal layer such as GaAs / InGaAs, AlGaN / GaN, GaN / AlGaN / GaN, or InAlN / GaN.
  • the third crystal layer 204 include GaAs, AlGaAs, InGaAs, InGaP, AlN, GaN, and AlGaN.
  • the total number of second atoms contained in the third crystal layer 204 is smaller than the total number of second atoms contained in the first crystal layer 104.
  • the total number of second atoms indicates the sum of the numbers of the second atoms.
  • the third crystal layer 204 is in a depletion state.
  • the “depletion state” means that the same number of free electrons and holes in the third crystal layer 204 exist, so that free electrons and holes recombine and cancel each other, so that carriers are substantially absent. The state that is. For example, there is a case where the number of free electrons and holes generated from the donor and acceptor existing in the third crystal layer 204 is approximately the same.
  • the concentration of the second atoms contained in the first crystal layer 104 is preferably an excessive concentration sufficient to compensate for the mixed first atoms.
  • the concentration of the second atoms contained in the first crystal layer 104 becomes excessive, carriers in the layer formed on the first crystal layer 104 are also captured. Therefore, when the second crystal layer functioning as the active layer is formed over the first crystal layer 104, the second atoms in which carriers that should form channels in the second crystal layer are excessively contained in the first crystal layer 104 are formed. And may adversely affect the modulation characteristics of the transistor.
  • the third crystal layer 204 in which the concentration of the second atom as the compensation impurity is lower than that of the first crystal layer 104 is inserted between the first crystal layer 104 and the second crystal layer 202.
  • the concentration of the first atom tends to show a more constant concentration profile in the upper layer (the surface side of the layer). Therefore, in the third crystal layer 204 above the first crystal layer 104, carrier electrons from the first atoms can be compensated with high accuracy without excessive doping of the second atoms.
  • the third crystal layer 204 can be depleted. it can.
  • the carrier concentration of the third crystal layer 204 is 1 ⁇ 10 17 cm ⁇ 3 or less, preferably 1 ⁇ 10 16 cm ⁇ 3 or less, particularly preferably 1 ⁇ 10 14 cm ⁇ 3 or less.
  • the carrier concentration refers to the carrier concentration when measured by SIMS.
  • the thickness of the third crystal layer 204 is preferably 50 nm or more.
  • the presence of the third crystal layer 204 in the depletion state between the first crystal layer 104 and the second crystal layer 202 causes electrons or holes traveling in the second crystal layer 202 to exist in the first crystal layer 104. Or it will not interact with holes.
  • a field effect transistor is formed using the second crystal layer 202 as an active layer, it is possible to prevent an abnormal operation of the element such as a kink appearing in the current-voltage curve (IV curve) of the field effect transistor.
  • an interface control layer may be formed between the first crystal layer 104 and the base substrate 102 for the purpose of controlling the properties of the interface.
  • Ga and Si may react to deteriorate the crystallinity of GaN.
  • AlN may be disposed as the interface control layer.
  • FIG. 4 shows a cross-sectional example of the semiconductor substrate 300.
  • the semiconductor substrate 300 includes a base substrate 102, a first crystal layer 104, a third crystal layer 204, an inhibition layer 302, a fourth crystal layer 304, and a fifth crystal layer 306.
  • the base substrate 102, the first crystal layer 104, and the third crystal layer 204 of the semiconductor substrate 300 are similar to the base substrate 102, the first crystal layer 104, and the third crystal layer 204 of the semiconductor substrate 100 and the semiconductor substrate 200.
  • the fourth crystal layer 304 is a crystal layer that can be applied to a channel layer of a field effect transistor.
  • the fifth crystal layer 306 is a crystal layer applicable to a Schottky layer of a field effect transistor.
  • the fourth crystal layer 304 and the fifth crystal layer 306 correspond to the second crystal layer 202 in the semiconductor substrate 200 of FIG.
  • the fourth crystal layer 304 is formed on the third crystal layer 204
  • the fifth crystal layer 306 is formed on the fourth crystal layer.
  • the lower portion of the first crystal layer 104 is formed inside the opening, and the upper portion protrudes from the opening.
  • the first crystal layer 104, the third crystal layer 204, the fourth crystal layer 304, and the fifth crystal layer 306 are partially formed on the base substrate 102.
  • “Partially formed” as used herein refers to a state in which crystals are grown not on the entire surface of the base substrate 102 but in a limited range. That is, the inhibition layer 302 is formed on or above the base substrate 102, and the first crystal layer 104, the third crystal layer 204, the fourth crystal layer 304, and the fifth crystal layer 306 are formed in the openings formed in the inhibition layer 302. Is formed.
  • the inhibition layer 302 inhibits crystal growth.
  • the inhibition layer 302 includes the same atoms as the first atoms included in the first crystal layer 104.
  • As the inhibition layer 302, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer can be given.
  • the fourth crystal layer 304 constitutes a channel of the field effect transistor when the field effect transistor is manufactured.
  • Examples of the material of the fourth crystal layer 304 include GaAs, AlGaAs, InGaAs, InGaP, GaN, AlGaN, InGaN, and InAlGaN.
  • the thickness of the fourth crystal layer 304 may be in the range of 100 nm to 10,000 nm.
  • the fifth crystal layer 306 forms a heterointerface with the fourth crystal layer 304, and induces channel charge at the heterointerface when a field effect transistor is manufactured.
  • the fifth crystal layer 306 include materials that can form a heterointerface with the fourth crystal layer 304, such as GaAs, AlGaAs, InGaAs, InGaP, GaN, AlGaN, InAlN, AlN, and InAlGaN.
  • the thickness of the fifth crystal layer 306 can be determined in consideration of the on-resistance, breakdown voltage, etc. of the transistor within a range in which the stress due to the lattice constant difference generated in the heterojunction crystal is kept within the elastic limit of the crystal. Examples of the thickness of the fifth crystal layer 306 include a range of 1 nm to 300 nm.
  • the inhibition layer 302 is formed in contact with the base substrate 102.
  • the inhibition layer 302 for example, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer is formed by vapor deposition, sputtering, thermal CVD, plasma CVD, or the like, and an opening is formed by etching. The opening is formed with a depth reaching the base substrate 102.
  • the inhibition layer 302 can be formed by forming a mask made of Ni or the like on the base substrate 102 and oxidizing, nitriding or oxynitriding the Si surface exposed at the bottom of the mask opening.
  • Nitriding can be performed by introducing a nitrogen source such as ammonia into the surface of the base substrate 102 and performing thermal nitriding or plasma nitriding.
  • the first crystal layer 104, the third crystal layer 204, the fourth crystal layer 304, and the fifth crystal layer 306 are stacked in this order on the base substrate 102 at the bottom of the opening of the inhibition layer 302.
  • These crystal layers are preferably formed by epitaxial growth.
  • Epitaxial growth methods include, for example, metal organic chemical vapor deposition (hereinafter sometimes referred to as MOCVD method), molecular beam epitaxy (hereinafter sometimes referred to as MBE method), and halide vapor phase epitaxy (HVPE method). Is mentioned.
  • MOCVD method metal organic chemical vapor deposition
  • MBE method molecular beam epitaxy
  • HVPE method halide vapor phase epitaxy
  • trimethylgallium (TMG), trimethylaluminum (TMA), trimethylindium (TMI), or the like can be used as a Group 3 element material.
  • Ammonia (NH 3 ) or the like can be used as the nitrogen raw material.
  • High purity hydrogen and high purity nitrogen can be used as a carrier gas for the raw material.
  • the epitaxial growth conditions are, for example, a reactor internal pressure of 0.1 atm, a growth temperature of 1000 ° C., and a growth rate of 0.1 ⁇ m / hr to 3 ⁇ m / hr.
  • the dope source gas may be introduced into the reaction furnace together with the group 3 source and the group 5 source.
  • a dope raw material biscyclopentadienyl magnesium, carbon tetrachloride, diethyl zinc, bismethylcyclopentadienyl beryllium, or the like can be used.
  • the impurity layer is doped into the precursor layer by ion implantation or thermal diffusion.
  • the first crystal layer 104 and the third crystal layer 204 may be formed.
  • FIG. 5 shows a cross-sectional example of the field effect transistor 400.
  • the field effect transistor 400 includes a base substrate 102, a first crystal layer 104, a third crystal layer 204, an inhibition layer 302, a channel layer 402, a Schottky layer 404, an ohmic electrode 406, and a gate electrode 408.
  • the base substrate 102, the first crystal layer 104, the third crystal layer 204, and the inhibition layer 302 of the field effect transistor 400 are the base substrate 102, the first crystal layer 104, and the third substrate 302 of the semiconductor substrate 100, the semiconductor substrate 200, and the semiconductor substrate 300. This is the same as the crystal layer 204 and the inhibition layer 302.
  • the channel layer 402 and the Schottky layer 404 are the same as the fourth crystal layer 304 and the fifth crystal layer 306 in the semiconductor substrate 300, and the fourth crystal layer 304 and the fifth Schottky layer 404 are formed by forming the ohmic electrode 406 and the gate electrode 408.
  • the crystal layers 306 become the channel layer 402 and the Schottky layer 404, respectively.
  • the ohmic electrode 406 connects the field effect transistor 400 and an external circuit.
  • An example of the ohmic electrode 406 is a laminated metal structure of Ti / Au from the Schottky layer 404 side.
  • the gate electrode 408 inputs a signal to the field effect transistor 400.
  • An example of the gate electrode 408 is a Ni / Au laminated metal structure from the Schottky layer 404 side.
  • the field effect transistor 400 is manufactured using the semiconductor substrate 300.
  • two ohmic electrodes 406 are formed so as to be separated from the gate electrode 408 and sandwich the gate electrode 408.
  • the metal constituting the ohmic electrode 406 and the gate electrode 408 is formed by, for example, vapor deposition, sputtering, or CVD. Photolithography can be used to form a desired shape.
  • the ohmic electrode 406 and the gate electrode 408 can be formed by a combination of the photolithography method and the lift-off method.
  • the ohmic electrode 406 is preferably annealed to obtain better ohmic contact. Annealing conditions include a heat treatment at 800 ° C. for 30 seconds in a nitrogen atmosphere.
  • a 2-inch Si substrate having a (111) plane as a main surface was prepared as the base substrate 102.
  • a silicon oxide layer was deposited as an inhibition layer 302 on the entire surface of the Si substrate.
  • the silicon oxide layer was deposited with a thickness of 150 nm by a sputtering method.
  • a photosensitive resin having an opening of 100 ⁇ m square was formed on the silicon oxide layer by photolithography, and the silicon oxide layer and the natural oxide film were wet etched using the photosensitive resin as a mask to expose the Si substrate.
  • the Si substrate After removing the photosensitive resin, the Si substrate is carried into an epitaxial growth furnace, and after the surface pretreatment, a source gas is supplied into the furnace, and the interface control layer, the buffer layer as the first crystal layer 104, the third crystal The depletion crystal layer, the channel layer 402, and the Schottky layer 404 as the layer 204 were formed by epitaxial growth.
  • Table 1 shows the composition, thickness, and Mg atom doping concentration of each layer.
  • a substrate having the same crystal structure as described in Table 1 and not doped with Mg atoms in the buffer layer and the layer corresponding to the depletion crystal layer was produced.
  • a substrate doped with Mg atoms is referred to as a “doped substrate”, and a substrate not doped with Mg atoms is referred to as an “undoped substrate”.
  • Trimethyl gallium (TMG), trimethyl aluminum (TMA), biscyclopentadienyl magnesium and ammonia (NH 3 ) were used as source gases.
  • the pressure in the growth furnace was kept at 30 kPa. Hydrogen was used as a carrier gas for the source gas.
  • the growth of each layer was performed while controlling the supply amount of each raw material and the substrate temperature.
  • the buffer layer and the depleted crystal layer had 5 ⁇ 10 17 cm ⁇ 3 to 1 ⁇ 10 18 cm ⁇ 3 Si atoms and 5 ⁇ 10 17 cm ⁇ . O atoms of 3 to 1 ⁇ 10 18 cm ⁇ 3 were mixed.
  • An ohmic electrode, element isolation, and a gate electrode were formed in this order on a doped substrate and an undoped substrate to produce a field effect transistor.
  • the ohmic electrode was Ti (10 nm) / Al (150 nm) / Ni (20 nm) / Au (300 nm) from the crystal side.
  • the ohmic electrode was formed using vapor deposition, photolithography, and lift-off.
  • the ohmic electrode was annealed in a nitrogen atmosphere at 800 ° C. for 60 seconds after formation.
  • Element isolation was performed by implanting nitrogen ions.
  • the acceleration voltage for implantation was 20 KeV and 100 KeV. Both doses of nitrogen ions were 1 ⁇ 10 14 cm 2 .
  • the gate electrode was Ni (15 nm) / Au (200 nm) from the crystal side.
  • the gate electrode was formed using an evaporation method, photolithography, and a lift-off method.
  • a transistor using a doped substrate is called a doped transistor
  • a transistor using an undoped substrate is called an undoped transistor.
  • FIG. 6 shows the IV characteristics of the doped transistor.
  • FIG. 7 shows the IV characteristics of the undoped transistor.
  • one of the ohmic electrodes (source) was grounded, and the voltage applied to the other ohmic electrode (drain) was changed from 0 V to 10 V, and the current flowing through the drain during that time was evaluated.
  • the IV characteristics were evaluated by changing the gate voltage Vg from 0V to ⁇ 5V in 1V steps.
  • the drain current was modulated only in a limited voltage range within the range of 0V to -5V in which the gate voltage was changed.
  • the drain voltage was not pinched off even when a negative voltage was applied as the gate voltage.
  • the field effect transistor is illustrated as the semiconductor device, but other active devices such as a bipolar transistor and an LED may be used.
  • SYMBOLS 100 Semiconductor substrate, 102 ... Base substrate, 104 ... 1st crystal layer, 200 ... Semiconductor substrate, 202 ... 2nd crystal layer, 204 ... 3rd crystal layer, 300. ..Semiconductor substrate 302 ... Inhibition layer 304 ... Fourth crystal layer 306 ... Fifth crystal layer 400 ... Field effect transistor 402 ... Channel layer 404 ... Schottky Layer, 406 ... Ohmic electrode, 408 ... Gate electrode

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Chemical Vapour Deposition (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention concerne un substrat semiconducteur comportant un substrat de base et une première couche de cristaux formée sur ou au-dessus du substrat de base. La première couche de cristaux est une couche composée de semiconducteurs des groupes 3 à 5 qui contient un premier atome constituant au moins un atome choisi dans le groupe formé d'un atome d'oxygène et d'un atome de silicium, ainsi qu'un deuxième atome constituant au moins un atome faisant fonction d'accepteur. Le substrat semiconducteur peut comporter de plus une couche d'inhibition formée sur ou au-dessus du substrat de base. La couche d'inhibition présente une ouverture et inhibe la croissance des cristaux. La couche d'inhibition contient le premier atome et la première couche de cristaux est formée dans l'ouverture.
PCT/JP2011/004506 2010-08-11 2011-08-09 Substrat semiconducteur, dispositif semiconducteur et procédé de production d'un substrat semiconducteur WO2012020565A1 (fr)

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JP6737800B2 (ja) * 2015-11-02 2020-08-12 日本碍子株式会社 半導体素子用エピタキシャル基板、半導体素子、および、半導体素子用エピタキシャル基板の製造方法
DE112016005025T5 (de) 2015-11-02 2018-08-23 Ngk Insulators, Ltd. Epitaxialsubstrat für halbleiterelemente, halbleiterelement und produktionsverfahren für epitaxialsubstrate für halbleiterelemente
JP6708960B2 (ja) * 2016-06-22 2020-06-10 住友電気工業株式会社 窒化物半導体装置及び窒化物半導体装置の製造方法
JP6566069B2 (ja) * 2018-03-22 2019-08-28 富士通株式会社 化合物半導体装置及びその製造方法

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JP2000311903A (ja) * 1999-04-27 2000-11-07 Kyocera Corp 化合物半導体基板およびその製造方法
JP2002261032A (ja) * 2000-06-19 2002-09-13 Nichia Chem Ind Ltd 窒化物半導体基板及びその製造方法、並びにその窒化物半導体基板を用いた窒化物半導体素子
JP2002299253A (ja) * 2001-03-30 2002-10-11 Toyoda Gosei Co Ltd 半導体基板の製造方法及び半導体素子
JP2010171032A (ja) * 2009-01-20 2010-08-05 New Japan Radio Co Ltd 窒化物半導体装置形成用基板及び窒化物半導体装置

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JP2003257997A (ja) * 2002-02-28 2003-09-12 Sumitomo Electric Ind Ltd 窒化ガリウム系半導体装置を製造する方法
JP4792814B2 (ja) * 2005-05-26 2011-10-12 住友電気工業株式会社 高電子移動度トランジスタ、電界効果トランジスタ、エピタキシャル基板、エピタキシャル基板を作製する方法およびｉｉｉ族窒化物系トランジスタを作製する方法
JP5670427B2 (ja) * 2009-04-08 2015-02-18 エフィシエント パワー コンヴァーション コーポレーション ＧａＮバッファ層におけるドーパント拡散変調

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JP2000311903A (ja) * 1999-04-27 2000-11-07 Kyocera Corp 化合物半導体基板およびその製造方法
JP2002261032A (ja) * 2000-06-19 2002-09-13 Nichia Chem Ind Ltd 窒化物半導体基板及びその製造方法、並びにその窒化物半導体基板を用いた窒化物半導体素子
JP2002299253A (ja) * 2001-03-30 2002-10-11 Toyoda Gosei Co Ltd 半導体基板の製造方法及び半導体素子
JP2010171032A (ja) * 2009-01-20 2010-08-05 New Japan Radio Co Ltd 窒化物半導体装置形成用基板及び窒化物半導体装置

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