TW201214700A - Semiconductor substrate, semiconductor device and method for manufacturing semiconductor substrate - Google Patents

Semiconductor substrate, semiconductor device and method for manufacturing semiconductor substrate Download PDF

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TW201214700A
TW201214700A TW100128650A TW100128650A TW201214700A TW 201214700 A TW201214700 A TW 201214700A TW 100128650 A TW100128650 A TW 100128650A TW 100128650 A TW100128650 A TW 100128650A TW 201214700 A TW201214700 A TW 201214700A
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layer
atom
crystal layer
crystal
semiconductor substrate
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Hiroyuki Sazawa
Masahiko Hata
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Sumitomo Chemical Co
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
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    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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Abstract

Provided is a semiconductor substrate having a base substrate and a first crystalline layer formed on or above the base substrate, wherein the first crystalline layer is a group III-V compound semiconductor layer containing a first atom which is at least one atom selected from a group consisted of oxygen atom and silicon atom and a second atom which is at least one atom serving as acceptor. The semiconductor substrate further has a blocking layer formed on or above the base substrate. The blocking layer has an opening and blocks crystalline growth. The blocking layer contains the first atom. The first crystalline layer is formed in the opening.

Description

201214700 六、發明說明： 【發明所屬之技術領域】 半導體^及+導體基板 本發明係關於半導體基板 的製造方法。201214700 VI. Description of the Invention: [Technical Field of the Invention] Semiconductors and + Conductor Substrate The present invention relates to a method of manufacturing a semiconductor substrate.

【先前技術】 GaN 、A漏等之氮化物半導體’係具有絕緣破壞電壓 高，飽和漂移速度大’化學及熱穩定性佳，且能帶隙 特徵。因此，GaN、A1GaN等之氮化物半導體，乃被視 活用該特徵而應用在功率開關裝置、可在高溫下動作之 置、藍色或綠色的發光裝置等用途中。 义 使氮化物半導體蟲晶成長時，較佳為使用便宜的石夕基 板作為結晶成長的基層基板1而，會㈣結晶與氮化物 半導體結晶之㈣脹魏的騎大，而在Μ成長後的結 晶層容易產生龜裂之問題1問勒解決方法之―，係提 出有-種並非在梦基板的整面上使氮化物半導體結 晶層均 質地成長，而是部分地形成之技術。 例如，專利文獻1係揭示一種使由AlxGaylm-x-yN(惟0 d ’ GSx+y^i)所構叙3族氮化物半導體蟲晶成 長於Si基板上之技術。專利文獻j巾，記載有當使3族氮 化物半導體蟲晶成長於Si基板上時，在Si基板上形成由 Si的熱氧化膜所構成之遮罩，並使3族氮化物半導體選擇 性磊晶成長於Si的露出部之技術内容。 專利文獻1 :日本特開平11-274082號公報 【發明内容】 4 323405 201214700 (發明所欲解決之課題） 如專利文獻i所記载，若在石夕基板上形成氧化石夕膜， 並在該氧化珍膜的任意區域形成可到達發基板之開口，則 可使氧切膜具有作為阻礙氮化物半導體結晶㈣晶成長 之阻礙層的魏’而僅在開口_部使氮化物半導體結晶 選擇性蠢晶成長。蠢晶成長後的氮化物半導體結晶，並非 形成在矽基板的整面，而是僅形成於開口内部故可期待 抑制氮化物半導體結晶龜裂的產生之致果。 然而’以阻礙層作為遮罩而在阻礙層開口的内部使半 導體結晶層選擇㈣晶成長之方法中，會有構成阻礙層之 原子進入於蟲晶成長層内之情形。為人所知者，進入於半 導體結晶層内之原子乃具有作為雜質的功能，例如當^ 、或 〇進入於GaN結晶或AlGaN結晶時，會成為〇型雜質。 第1圖係為了評估Si原子及〇原子以何種程度進入 GaN層而進行實驗之二次離子質譜分析（SIMS)數據。第i 圖係顯示以氧切蘭為阻礙層並__晶成長之㈣ 層的SIMS深度分佈（profile)，實線為〇原子，虛線為& 原子，單點虛線為Ga原子的深度分佈。〇原子及$丨原子 係相當於縱歓側的濃度標度’ Ga原子係相#於縱轴右側 的二次離子強度標度。Ga原子的二欠離子強度降低之深度 〇.5em附近，為基板與GaN層之界面。從深度〇 5#m附 近至深度0 Mm的表面為止為GaN層。雖然在GaN層的深度 方向並非均質，但可得知有lxl〇18cm-3以上的〇原子及si 原子進入，且因深度的不同甚至有接近於lxl〇2Qcm_3的雜質 323405 5 201214700 原子進入。[Prior Art] A nitride semiconductor such as GaN or A-drain has a high dielectric breakdown voltage and a large saturation drift velocity, and has good chemical and thermal stability and band gap characteristics. Therefore, a nitride semiconductor such as GaN or A1GaN is used in applications such as a power switching device, a high-temperature operation, and a blue or green light-emitting device. When the nitride semiconductor crystallite is grown, it is preferable to use a cheap Shih-ray substrate as the base substrate 1 for crystal growth, and (4) crystallize and nitride semiconductor crystal (4) to expand the Wei, and after the growth of the crucible The problem that the crystal layer is liable to cause cracking is a technique in which the nitride semiconductor crystal layer is not uniformly grown on the entire surface of the dream substrate, but is partially formed. For example, Patent Document 1 discloses a technique for forming a Group 3 nitride semiconductor crystallite grown on an Si substrate by AlxGaylm-x-yN (only 0 d ' GSx+y^i). In the case of growing a group III nitride semiconductor crystallite on a Si substrate, a mask formed of a thermal oxide film of Si is formed on the Si substrate, and the group III nitride semiconductor is selectively exposed. The technical content of crystal growth in the exposed portion of Si. [Patent Document 1] Japanese Laid-Open Patent Publication No. Hei 11-274082 (Description of the Invention) 4 323405 201214700 (Problem to be Solved by the Invention) As described in Patent Document i, if an oxide oxide film is formed on a stone substrate, When any region of the oxidized film forms an opening that can reach the hair substrate, the oxygen dicing film can have a barrier layer that hinders the growth of the nitride semiconductor crystal (tetra) crystal, and the nitride semiconductor crystal is selectively stupid only in the opening portion. Crystal growth. The nitride semiconductor crystal after the growth of the stray crystal is not formed on the entire surface of the tantalum substrate, but is formed only inside the opening, so that it is expected to suppress the occurrence of cracking of the nitride semiconductor crystal. However, in the method of selectively (four) crystal growth of the semiconductor crystal layer inside the opening of the barrier layer by using the barrier layer as a mask, atoms constituting the barrier layer may enter the crystal growth layer. As is well known, atoms entering the semiconductor crystal layer have a function as an impurity, for example, when ^ or 〇 enters GaN crystal or AlGaN crystal, it becomes a quinoid impurity. Fig. 1 is a secondary ion mass spectrometry (SIMS) data experimentally conducted to evaluate the extent to which Si atoms and germanium atoms enter the GaN layer. The i-th image shows the SIMS depth profile of the (4) layer with oxygen-cutting as the barrier layer and __ crystal growth, the solid line is the germanium atom, the dotted line is the & atom, and the single-dotted dotted line is the depth distribution of the Ga atom. The ruthenium atom and the ruthenium atom are equivalent to the concentration scale of the mediastinal side, and the secondary ion intensity scale of the Ga atomic phase on the right side of the vertical axis. The depth of the under-ion intensity of the Ga atom is reduced to the vicinity of 〇.5em, which is the interface between the substrate and the GaN layer. The GaN layer is from the surface near the depth 〇 5#m to the surface at a depth of 0 Mm. Although the depth direction of the GaN layer is not homogeneous, it is known that 〇 atoms and si atoms of lxl 〇 18 cm -3 or more enter, and there are even impurities close to lxl 〇 2Qcm_3 due to the difference in depth 323405 5 201214700 atoms enter.

此等雜質原子係明顯對結晶層的導電性產生影響。GaN 結晶中，由於Si原子或〇原子均發揮作為生成n型傳導載 子（自由電子）之施體的作用，故難以提高選擇性磊晶結晶 層的電阻。此外，亦難以將選擇性磊晶結晶層使用在須進 行電阻的精密控制之電子裝置用結晶。本發明之目的係在 於提供一種即使如使用阻礙層來進行選擇性磊晶成長之氮 化物半導體結晶般，於結晶中含有Si原子或〇原子之半導 體結晶，亦可提高電阻並使用在須進行電阻的精密控制之 電子裝置中之半導體結晶。 (用以解決課題之手段） 為了解決上述課題，本發明之第丨型態中，係提供一 =導體基板’其具有：基層基板、以及形成於基層基板 體二:：丄結晶層；第1結晶層係3_5族化合物半導 =1、料含有：獅自崎料及㈣子所組成之群組 至少ί個：原子的第1原子、以及具有作為受體的功能之 主/ 1個原子的第2原子。 =2原子，例如為選自以％原子、如原子、^原子 具有至少1個原子。半導體基板可復 於第…層與第;= ㈣ 2結晶層刀埜Q从 第3、、，0日日層。例如，第 晶層具有第2 為3-5族化合物半導體層，第3結 數，較第】/、帛3結晶層争所含有之第2原子的納 較第1結崎所含有之第2原子的總數更少。= 323405 6 201214700 2結晶層可具有作為使⑽半導體基板所形成之半導體主 動元件的活性層之魏。該第3結晶層可為耗盡狀態的結 晶層。 第1結晶層、第2結晶層及第3結晶層可為3_5族氮 化物半導體層。半導體基板可復具有形成於基層基板上或 上方之阻礙層。阻礙層具有開口，阻礙層阻礙結晶成長， ^礙層含有第1原子’帛1結晶層形成於開π。阻礙層可 為乳化矽層、氮化矽層或氮氧化矽層。 本發明之第2型態中，係提供—種半導體裝置，具有： 基層基板、形成於基層基板上4上方之第丨結晶層、以及 形成於第1結晶層上或上方之活性層；第^結晶層係3—5 族化合物半導體層，其係含有：選擇自以㈣子及梦原子 戶輪成之群組之至少i個原子的第i原子、以及具有作為 受體的功能之至少1個原子的第2原子。 本發明之第3型態中，係提供一種半導體基板的製造 方法’其似有：將含有自叫原子及㈣子所組成 之群組之至少1個原子的第1原子且阻礙結晶成長之阻礙 層’形成於基層上或上方之步驟；於阻礙詹形成開口 之步驟；以及一邊將具有作為受體的功能之第2原子導入 於開口的内部，一邊藉由磊晶成長來形成3_5族化合物半 導體的第1結晶層之步驟。 本發明之第4型態中，係提供—種半導體基板的製造 方法，其係具有：將含有選擇自以氧原子及矽原子所組成 之群組之至少1個原子的第1原子且阻礙結晶成長之阻礙 323405 7 201214700 層，形成於基層基板上或上方之步驟；於阻礙層形成開口 之步驟，藉由磊晶成長將族化合物半導體的第丨結晶 前驅物層形成於開口的内部之步驟；以及以具有作為受體 的功能之至少1個原子的第2原子來摻雜第1結晶前驅物 層，藉此形成第1結晶層之步驟。在半導體基板的製造方 法中，阻礙層可為氧化矽層、氮化矽層或氮氧化矽層。 【實施方式】 第2圖係顯示半導體基板1〇〇的剖面例。半導體基板 100係具有基層基板1〇2及第丨結晶層1〇4。於基層基板 102及第1結晶層1〇4之間亦可形成任意的結晶層。 基層基板102為用以支撐形成於該上方之磊晶成長層 之支撐基板。就基層基板1〇2而言，例如可列舉出表面為 石夕之基板、藍寶石基板、碳化矽基板、氧化鋅基板、GaAs 基板。在此’所謂「表面為矽」係意味著至少基板的表面 具有由矽所構成之區域者。例如，基層基板1〇2可如矽晶 圓I又之基板整體由梦所構成者，或是，S〇i(siiicon-on_ insulator :絕緣層上覆矽）晶圓般之在絕緣層上具有矽層 之構造。基層基板102係可在藍寶石基板、玻璃基板、碳 化石夕基板、氧化辞基板、GaAs基板等之由與矽不同之元素 所構成之基板上形成矽層。基層基板1〇2的矽可包含雜 質。亦可於基層基板102表面的矽層形成自然氧化層等之 極薄的氧化矽層或氮化矽層。 第1結晶層104係形成於基層基板102上或上方。亦 即’第1結晶層104可接觸於基層基板102的表面而形成， 8 323405 201214700 或是與基層基板102的表面之間夾隔著其他層而形成。第 1結晶層104為3-5族化合物半導體層。就第1結晶層104 而言’可列舉出 GaAs、AlGaAs、InGaAs、InGaP、AIN、GaN 或AlGaN。第1結晶層1〇4係含有選擇自以氧原子及矽原 子所組成之群組之至少1個原子的第1原子。第1原子於 第1結晶層104中的濃度，為2xlOncm-3以上ixl〇2icm-3以 下。 第1結晶層104係含有具有作為受體的功能之至少i 個原子的第2原子。就第2原子而言，可列舉選擇自以Mg 原子Zn原、子、Be原、子及C原子所組成之群组之至少i個 原子。第2原子係具有在第i結晶層刚内生成電洞之作 為受體的功能。藉域第丨結晶層1Q4同時含有成為施體 之第1原子與成為受體之第2原子，即可以由第2原子所 生成之電洞來補償由第i原子所生成之電子，而提高第i ^晶層104的電阻率。由於可提高第1結晶層104的電阻 結果可抑制第1结晶層104中所流通之電流，而改盖 幻結晶層綱或形成於第u#晶層⑽上之震置的特性。。 :如為場效電《時’可㈣以（pinGhQff)特性 第1結晶層104中所含有之第2原子的濃度 混入之W原子之過剩的濃度。所謂過： 2度為，除了補償第i原子之外，亦可捕集因電 作時的電壓施加賴產生之載子（電子），而在電 = 時可將第丨結晶層丨〇4保持在高絕緣性之 t 323405 9 201214700 此濃度，可期待電晶體之夾止特性的提升，以及開關比的 提升。一般而言，第2原子的濃度可在lxi〇i4cm-3至1χ1〇2ΐ cm—3的範圍内決定。 第1結晶層104中所含有之第2原子的濃度，可為剛 好補償所混入之第1原子之濃度、些許不足於補償第1原 子之濃度、或是可過度補償第1原子但過剩量僅為些許之 濃度。此時’第1結晶層104係成為絕緣性、或是導電性 低的η型或p型導電型，在此情形下亦可期待該效果。 第3圖係顯不半導體基板2 0 0的剖面例。半導體基板 200係具有基層基板102、第1結晶層104、第2結晶層202 及第3結晶層204。半導體基板200中之基層基板102及 第1結晶層104係與半導體基板100中之基層基板ι〇2及 第1結晶層104相同。 第2結晶層202係形成於第1結晶層1〇4的上方。第 2結晶層202具有作為半導體主動元件的活性層之功能。 該半導體主動元件是指使用半導體基板200所形成之元 件。亦即，當使用半導體基板200來形成半導體主動元件 時，第2結晶層202係具有可作為該半導體主動元件的活 性層的功能之特性。第3結晶層204係形成於第1結晶層 104與第2結晶層202之間。第2結晶層202及第3結晶 層204為3_5族化合物半導體層。就第2結晶層202而言， 可列舉出 GaAs、AlGaAs、InGaAs、InGaP、AlGaN 或 GaN。 第2結晶層202亦可非單一層，例如可為GaAs/InGaAs、 AlGaN/GaN、GaN/AlGaN/GaN、或 InAlN/GaN 等異質接合結 10 323405 201214700 晶層。就第3結晶層204而言’可列舉出GaAs、A1 GaAs、 ' InGaAs、InGaP、AIN、GaN 或 AlGaN 〇 第3結晶層204中所含有之第2原子的總數，較第1 結晶層104中所含有之第2原子的總數更少。當結晶層中 含有複數種類之第2原子時，第2原子的總數是指各第2 原子的數目之和。第3結晶層204係處於耗盡狀態。在此 所謂「耗盡狀態」，是指第3結晶層204内的自由電子與電 洞存在有同等程度的數目，結果使自由電子與電洞重新結 合而抵銷，使載子實質上不存在之狀態。例如可列舉出由 存在於第3結晶層204之施體及受體所生成之自由電子與 電洞幾乎為同樣數目之情形。 如前所述，第1結晶層104中所含有之第2原子的濃 度，較佳為可充分地補償所混入之第1原子之過剩的濃 度。然而，當第1結晶層104中所含有之第2原子的濃度 過剩時，亦會捕集到第1結晶層104上所形成之層的載子。 因此，當將具有作為活性層的功能之第2結晶層形成於第 1結晶層104上時，在第2結晶層上應予形成通道之載子， 會被第1結晶層104中過剩含有之第2原子所捕集，而可 能對電晶體的調變特性產生不良影響。相對於此，半導體 基板200中，係於第1結晶層104與第2結晶層202之間， 插入作為補償雜質之第2原子的濃度較第1結晶層104更 低之第3結晶層204。一般而言，如第1圖的SIMS深度分 佈所示，第1原子的濃度係具有在上層（層的表面側）容易 顯示出更為一定的濃度分佈之傾向。因此，在較第1結晶 11 323405 201214700 層更位於上層侧之第3結晶層2〇4中，即使不過剩地 摻雜第2原子，亦可尚精度地補償來自第1原子的載子電 子。藉由將第2原子的摻雜量’調整為可補償第丨原子並 且可使由第2原子聽生之電、;_農度成祕低之位準， 而可使第3結晶層2G4達到耗盡狀態。第3結晶層2〇4的 载子濃度為IxHTW3以下，較佳為1><1()%_3以下，更佳 為lxlOlW以下。載子濃度是指藉由通進行測定時之 载子濃度。第3結晶層204的厚度較佳為5〇nm以上。 藉由使處於耗盡狀態之第3結晶層2〇4存在於第i锋 晶層104與第2結晶層202之間，可使在第2結晶層^ 中行進之電子或電洞不會與存在於第丨結晶層1〇4之電子 或電洞進行相互作用。結果，當以第2結晶層2〇2作為活 性層來形成場效電晶體時，可防止該場效電晶體的電流一 電壓曲線（IV曲線）產生扭折（kink)等之元件的異常動作。 亦可於第1結晶層104與基層基板1〇2之間，以控制 界面的性狀者為目的’形成界面控制層。例如，當使用s i 作為基層基板102 ’並形成GaN層作為第1結晶層1 時， 會有Ga與Si進行反應而導致GaN結晶性劣化之情形。此 時，亦可配置A1N作為界面控制層。 第4圖係顯示半導體基板3 0 0的剖面例。半導體基才反 3〇〇係具有基層基板102、第1結晶層104、第3結晶層204、 阻礙層302、第4結晶層304及第5結晶層306。半導體基 板300中之基層基板102、第1結晶層104及第3結晶層 204,係與半導體基板100及半導體基板200中之基層基板 323405 12 201214700 102、第1結晶層104及第3結晶層204相同。第4結晶層 304為可適用於場效電晶體的通道層之結晶層。第5結晶 層306為可適用於場效電晶體的簫特基層之結晶層。第4 結晶層304及第5結晶層306，係對應於第3圖之半導體 基板200的第2結晶層202。本例中，第4結晶層304係 形成於第3結晶層204上，第5結晶層306係形成於第4 結晶層上。此外，第4圖中，第1結晶層104的下部係形 成於開口内部，上部則從開口突出而形成。 第1結晶層104、第3結晶層204、第4結晶層304及 第5結晶層306 ’係部分地形成於基層基板1〇2上。在此 所謂部分地形成，並非在基層基板1〇2的整面上，而是顯 示結晶在某有限之範圍内成長之狀況。亦即，係於基層基 板102上或上方形成阻礙層302，並在形成於阻礙層302 之開口的内部，形成第1結晶層1〇4、第3結晶層204、第 4結晶層304及第5結晶層306。 阻礙層302係阻礙結晶成長。阻礙層302含有與第1 結晶層104中所含有的第1原子為同一之原子。阻礙層3〇2 可列舉出氧化矽層、氮化矽層或氮氧化矽層。 第4結晶層304係於製作場效電晶體時構成場效電晶 體的通道層。第4結晶層304的材料，可列舉出GaAs、These impurity atomic systems significantly affect the conductivity of the crystalline layer. In the GaN crystal, since both Si atoms and germanium atoms function as a donor body for generating an n-type conduction carrier (free electrons), it is difficult to increase the resistance of the selective epitaxial crystal layer. Further, it is also difficult to use a selective epitaxial crystal layer for crystallization of an electronic device which requires precise control of resistance. An object of the present invention is to provide a semiconductor crystal containing Si atoms or germanium atoms in a crystal, such as a nitride semiconductor crystal which is selectively epitaxially grown using a barrier layer, which can improve resistance and be used for resistance. The semiconductor crystal in the precision controlled electronic device. (Means for Solving the Problem) In order to solve the above problems, in a third aspect of the present invention, there is provided a conductor substrate having: a base substrate; and a base layer substrate: a germanium crystal layer; The crystal layer is a semi-conducting compound of the group 3-5, and contains at least one group consisting of: the lion and the (4) subunit: the first atom of the atom, and the main function of the acceptor/the first atom 2 atoms. The =2 atom is, for example, selected from the group consisting of % atoms, such as atoms, and ^ atoms having at least one atom. The semiconductor substrate can be re-applied to the first layer and the first layer; = (iv) 2 crystal layer Knife Q from the 3rd, the 0th day. For example, the fourth layer is a 3-5th compound semiconductor layer, and the third number is smaller than the second atom contained in the first atom of the first and/or 结晶3 crystal layers. The total number is smaller. = 323405 6 201214700 The 2 crystal layer may have an active layer as a semiconductor active element formed by the (10) semiconductor substrate. The third crystal layer may be a depleted crystalline layer. The first crystal layer, the second crystal layer, and the third crystal layer may be a Group 3-5 nitride semiconductor layer. The semiconductor substrate may have a barrier layer formed on or above the substrate. The barrier layer has an opening, and the barrier layer inhibits crystal growth. The barrier layer contains a first atom. The ?1 crystal layer is formed at π. The barrier layer may be an emulsified ruthenium layer, a tantalum nitride layer or a ruthenium oxynitride layer. According to a second aspect of the present invention, there is provided a semiconductor device comprising: a base substrate; a second crystal layer formed on the base layer 4; and an active layer formed on or above the first crystal layer; The crystal layer is a Group 3-5 compound semiconductor layer containing: an i-th atom selected from at least i atoms of a group of (4) and a dream atomic group, and at least one function having a function as a receptor The second atom of the atom. According to a third aspect of the present invention, there is provided a method for producing a semiconductor substrate, which is characterized in that it contains a first atom containing at least one atom of a group consisting of a self-called atom and a (four) sub-group and hinders growth of crystal growth. a step of forming a layer 'on or above the base layer; a step of blocking the opening of the layer; and introducing a second atom having a function as a receptor into the opening, and forming a group 3-5 compound semiconductor by epitaxial growth The step of the first crystal layer. According to a fourth aspect of the present invention, there is provided a method of producing a semiconductor substrate comprising: a first atom containing at least one atom selected from the group consisting of an oxygen atom and a germanium atom, and hindering crystallization a step of growing 323405 7 201214700, a step of forming a layer on or above the substrate; a step of forming an opening in the barrier layer, and forming a second crystalline precursor layer of the group compound semiconductor into the interior of the opening by epitaxial growth; And a step of forming a first crystal layer by doping the first crystal precursor layer with a second atom having at least one atom as a function of the acceptor. In the method of fabricating a semiconductor substrate, the barrier layer may be a hafnium oxide layer, a tantalum nitride layer or a hafnium oxynitride layer. [Embodiment] FIG. 2 is a view showing an example of a cross section of a semiconductor substrate 1A. The semiconductor substrate 100 has a base substrate 1〇2 and a second crystal layer 1〇4. An arbitrary crystal layer may be formed between the base layer substrate 102 and the first crystal layer 1〇4. The base substrate 102 is a support substrate for supporting the epitaxial growth layer formed on the upper surface. The base substrate 1 2 includes, for example, a substrate having a surface of a stone, a sapphire substrate, a tantalum carbide substrate, a zinc oxide substrate, and a GaAs substrate. Here, the term "surface is 矽" means that at least the surface of the substrate has a region composed of ruthenium. For example, the base substrate 1〇2 may be composed of a silicon wafer I and a substrate as a whole, or an S〇i (siiicon-on_ insulator) wafer on the insulating layer. The structure of the enamel layer. The base substrate 102 can form a ruthenium layer on a substrate made of an element different from ruthenium, such as a sapphire substrate, a glass substrate, a carbonization substrate, an oxidized substrate, or a GaAs substrate. The crucible of the base substrate 1〇2 may contain impurities. An extremely thin yttria layer or a tantalum nitride layer such as a natural oxide layer may be formed on the ruthenium layer on the surface of the base substrate 102. The first crystal layer 104 is formed on or above the base substrate 102. That is, the first crystal layer 104 can be formed in contact with the surface of the base substrate 102, and 8 323405 201214700 or the surface of the base substrate 102 can be formed with another layer interposed therebetween. The first crystal layer 104 is a group 3-5 compound semiconductor layer. The first crystal layer 104 is exemplified by GaAs, AlGaAs, InGaAs, InGaP, AIN, GaN or AlGaN. The first crystal layer 1〇4 contains a first atom selected from at least one atom of a group consisting of an oxygen atom and a ruthenium atom. The concentration of the first atom in the first crystal layer 104 is 2xlOncm-3 or more and ixl 〇2icm-3 or less. The first crystal layer 104 contains a second atom having at least i atoms which function as an acceptor. The second atom may be selected from at least i atoms selected from the group consisting of a Zn atom, a sub, a Be, a sub and a C atom of a Mg atom. The second atomic system has a function of generating a hole in the ith crystal layer as a receptor. The second crystal layer 1Q4 of the borrowing region contains the first atom to be the donor and the second atom to be the acceptor, that is, the electron generated by the second atom can be compensated for by the hole generated by the second atom. The resistivity of the i ^ crystal layer 104. As a result of increasing the electric resistance of the first crystal layer 104, the current flowing through the first crystal layer 104 can be suppressed, and the characteristics of the crystal layer or the shock formed on the u# crystal layer (10) can be changed. . In the case of the field effect electric power, "hour" can be (4) (pinGhQff) characteristic. The concentration of the second atom contained in the first crystal layer 104 is excessively mixed with the W atom. The so-called: 2 degrees, in addition to compensating the i-th atom, it can also capture the carrier (electron) generated by the voltage application during the electric operation, and the second crystal layer 丨〇4 can be maintained at the electric= At this concentration of high insulation t 323405 9 201214700, it is expected that the clamping characteristics of the transistor are improved and the switching ratio is improved. In general, the concentration of the second atom can be determined within the range of lxi〇i 4 cm -3 to 1 χ 1 〇 2 ΐ cm -3 . The concentration of the second atom contained in the first crystal layer 104 may be such that the concentration of the first atom to be mixed is compensated, the concentration of the first atom is not sufficiently compensated, or the first atom is excessively compensated, but the excess amount is excessively compensated only. For a little concentration. At this time, the first crystal layer 104 is an insulating type or an n-type or p-type conductivity type having low conductivity, and this effect can be expected in this case. Fig. 3 is a cross-sectional view showing a semiconductor substrate 200. The semiconductor substrate 200 has a base layer substrate 102, a first crystal layer 104, a second crystal layer 202, and a third crystal layer 204. The base substrate 102 and the first crystal layer 104 in the semiconductor substrate 200 are the same as the base substrate ι 2 and the first crystal layer 104 in the semiconductor substrate 100. The second crystal layer 202 is formed above the first crystal layer 1〇4. The second crystal layer 202 has a function as an active layer of a semiconductor active device. The semiconductor active device refers to an element formed using the semiconductor substrate 200. That is, when the semiconductor active substrate is formed using the semiconductor substrate 200, the second crystal layer 202 has a function as a function of the active layer of the semiconductor active device. The third crystal layer 204 is formed between the first crystal layer 104 and the second crystal layer 202. The second crystal layer 202 and the third crystal layer 204 are a group 3-5 compound semiconductor layer. The second crystal layer 202 may be GaAs, AlGaAs, InGaAs, InGaP, AlGaN or GaN. The second crystal layer 202 may also be a non-single layer, and may be, for example, a heterojunction 10 323405 201214700 crystal layer such as GaAs/InGaAs, AlGaN/GaN, GaN/AlGaN/GaN, or InAlN/GaN. The third crystal layer 204 can be exemplified by the total number of second atoms contained in the third crystal layer 204 of GaAs, A1 GaAs, 'InGaAs, InGaP, AIN, GaN or AlGaN, compared with the first crystal layer 104. The total number of second atoms contained is less. When the crystal layer contains a plurality of second atoms, the total number of the second atoms means the sum of the numbers of the second atoms. The third crystal layer 204 is in a depleted state. Here, the "depletion state" means that the number of free electrons in the third crystal layer 204 is the same as that of the hole, and as a result, the free electrons and the holes are recombined to offset, so that the carrier does not substantially exist. State. For example, the number of free electrons generated by the donor and the acceptor existing in the third crystal layer 204 is almost the same as the number of holes. As described above, the concentration of the second atom contained in the first crystal layer 104 is preferably such that the excess concentration of the first atom to be mixed is sufficiently compensated. However, when the concentration of the second atom contained in the first crystal layer 104 is excessive, the carrier of the layer formed on the first crystal layer 104 is also trapped. Therefore, when the second crystal layer having the function as the active layer is formed on the first crystal layer 104, the carrier on which the channel is to be formed on the second crystal layer is excessively contained in the first crystal layer 104. The second atom is trapped, which may adversely affect the modulation characteristics of the transistor. On the other hand, in the semiconductor substrate 200, between the first crystal layer 104 and the second crystal layer 202, the third crystal layer 204 having a lower concentration of the second atom as the compensation impurity than the first crystal layer 104 is inserted. In general, as shown by the SIMS depth distribution in Fig. 1, the concentration of the first atom tends to exhibit a more constant concentration distribution in the upper layer (the surface side of the layer). Therefore, in the third crystal layer 2〇4 located on the upper layer side than the first crystal 11 323405 201214700 layer, even if the second atom is not excessively doped, the carrier electrons from the first atom can be accurately compensated. The third crystal layer 2G4 can be achieved by adjusting the doping amount of the second atom to compensate for the second atom and allowing the electricity to be heard by the second atom to be at a lower level. Depleted state. The carrier concentration of the third crystal layer 2〇4 is 1xHTW3 or less, preferably 1><1()%_3 or less, more preferably 1xlOlW or less. The carrier concentration refers to the carrier concentration when measured by passing. The thickness of the third crystal layer 204 is preferably 5 Å or more. By causing the third crystal layer 2〇4 in the depleted state to exist between the i-th front layer 104 and the second crystal layer 202, electrons or holes that travel in the second crystal layer can be prevented from being The electrons or holes existing in the second crystal layer 1〇4 interact. As a result, when the field effect transistor is formed by using the second crystal layer 2〇2 as an active layer, it is possible to prevent the current-voltage curve (IV curve) of the field effect transistor from generating an abnormal action of a component such as a kink. . The interface control layer may be formed between the first crystal layer 104 and the base substrate 1〇2 for the purpose of controlling the properties of the interface. For example, when s i is used as the base layer substrate 102' and a GaN layer is formed as the first crystal layer 1, Ga may react with Si to deteriorate the crystallinity of GaN. At this time, A1N can also be configured as the interface control layer. Fig. 4 is a view showing an example of a cross section of a semiconductor substrate 300. The semiconductor substrate has a base substrate 102, a first crystal layer 104, a third crystal layer 204, a barrier layer 302, a fourth crystal layer 304, and a fifth crystal layer 306. The base layer substrate 102, the first crystal layer 104, and the third crystal layer 204 in the semiconductor substrate 300 are the base substrate 323405 12 201214700 102, the first crystal layer 104, and the third crystal layer 204 in the semiconductor substrate 100 and the semiconductor substrate 200. the same. The fourth crystal layer 304 is a crystal layer which is applicable to the channel layer of the field effect transistor. The fifth crystal layer 306 is a crystal layer which is applicable to the Alken base layer of the field effect transistor. The fourth crystal layer 304 and the fifth crystal layer 306 correspond to the second crystal layer 202 of the semiconductor substrate 200 of Fig. 3 . In this example, the fourth crystal layer 304 is formed on the third crystal layer 204, and the fifth crystal layer 306 is formed on the fourth crystal layer. Further, in Fig. 4, the lower portion of the first crystal layer 104 is formed inside the opening, and the upper portion is formed to protrude from the opening. The first crystal layer 104, the third crystal layer 204, the fourth crystal layer 304, and the fifth crystal layer 306' are partially formed on the base substrate 1'2. Here, the partial formation is not the entire surface of the base substrate 1〇2, but shows that the crystal grows within a certain limited range. That is, the barrier layer 302 is formed on or above the base substrate 102, and the first crystal layer 1〇4, the third crystal layer 204, the fourth crystal layer 304, and the first layer are formed inside the opening formed in the barrier layer 302. 5 crystalline layer 306. The barrier layer 302 inhibits crystal growth. The barrier layer 302 contains the same atom as the first atom contained in the first crystal layer 104. The barrier layer 3〇2 may be a ruthenium oxide layer, a tantalum nitride layer or a ruthenium oxynitride layer. The fourth crystal layer 304 is a channel layer constituting the field effect transistor when the field effect transistor is fabricated. The material of the fourth crystal layer 304 is exemplified by GaAs.

AlGaAs、InGaAs、InGaP、GaN、AlGaN、InGaN、InAlGaN。 第4結晶層304的厚度可位於100nni至i〇〇〇〇nin的範圍内。 第5結晶層306係與第4結晶層304構成異質界面， 於製作場效電晶體時在該異質界面激發通道電荷。就第5 13 323405 201214700 結晶層306而言，可列舉出可與第4結晶層304構成異質 界面之材料，例如 GaAs、AlGaAs、InGaAs、InGaP、GaN、 AlGaN、InAIN、AIN、InAlGaN。第 5 結晶層 306 的厚度係 在結晶的彈性限度内可保持因異質接合結晶所產生之晶格 常數差所導致的應力之範圍内，可考量電晶體的導通電 阻、耐壓等來決定。第5結晶層306的厚度可例示lnm至 300nm的範圍内。 接著，說明半導體基板300的製造方法。首先，接觸 於基層基板102來形成阻礙層302。藉由蒸鍍法、濺鍍法、 熱CVD法、電漿CVD法等來形成例如氧化梦層、氮化梦層 或氮氧化矽層以作為阻礙層302,並藉由蝕刻來形成開口。 開口係形成為到達基層基板1〇2之深度。或者，可在基層 基板102上形成由Ni所構成之遮罩，並藉由使露出於遮罩 開口的底部之Si面予以氧化、氮化或氮氧化來形成阻礙層 302。氧化可應用熱氧化、電漿氧化等。氮化可藉由將氨等 氮源導入於基層基板102的表面並進行熱氮化、電漿氮化 來實施。 接著，於阻礙層302之開口底部的基層基板1〇2上， 依序積層第1結晶層104、第3結晶層204、第4結晶層 304及第5結晶層306。此等結晶層較佳是藉由磊晶成長來 形成。就磊晶成長法而言，可列舉例如有機金屬氣相成長 法（以下亦記載為MOCVD法）、分子束磊晶成長法（以下亦記 载為MBE法）、鹵化物氣相成長法（以下亦記載為hvpe法） 等。在磊晶成長的過程中，於阻礙層302上並未形成結晶 323405 14 201214700 層。因此’第1結晶層104、第3結晶層204、第4結晶層 304及第5結晶層306係僅形成於阻礙層302的開口。 以MOCVD法來形成時，就3族元素的原料而言，可使 用三甲基鎵（TMG)及三甲基銨（TMA)、三甲基銦（TMI)等。氣 原料可使用氨（NH3)等。原料的載體氣體可使用高純度氫 氣、咼純度氮氣。磊晶成長條件，例如為反應爐内壓 0. latm、成長溫度100(rc、成長速度〇. i以‘肚以上 在使前述蟲晶成長之步驟中，使第i結晶層1〇 3結晶層204成長時，係同時擦雜選擇自以％原子第 子、Be原子及G原子肋成之鮮組之至少1個原子作為^ 質原子。亦即，—邊_第2原子-邊藉Μ晶成長2 成結晶層。此時，將_原_難3麟料及5 ^ 一同導入至反應爐内即可。摻雜原料可使用雙環戊^ 鎂、四氯化碳、二乙基鋅、雙曱基環戊二烯鈹等。亦可， 藉由蠢晶絲來形成不含有作為雜f原子㈣2原子 1結晶前驅物層及第3結晶前驅物層後，藉由離子注 熱擴散等將雜質原子掺雜於㈣㈣層，#此來形1 結晶層104及第3結晶層204。 第5圖係顯示場效電晶體_的剖面例。場效電晶體 400係具有基層基板102、第1結晶層1〇4、第3結晶層腿、 阻礙層302、通道層402、蕭特基層404、歐姆電極日概及 閘極電極408。場效電晶體40〇中之基層基板1〇2、第工結 晶層104、第3結晶層204、卩且礙層搬，係與半導體基板 323405 15 201214700 100、半導體基板200及半導體基板300中之基層基板102、 第1結晶層104、第3結晶層204、阻礙層302相同。 通道層402及蕭特基層404係與半導體基板300之第 4結晶層304及第5結晶層306相同，並藉由形成歐姆電 極406及閘極電極408，而使第4結晶層304及第5結晶 層306分別成為通道層402及蕭特基層404。歐姆電極406 係連接場效電晶體400與外部電路。就歐姆電極406而言， 可例示從蕭特基層404側為Ti/Au的積層金屬構造。閘極 電極408係將訊號輸入於場效電晶體400。就閘極電極408 而言，可例示從蕭特基層404侧為Ni/Au的積層金屬構造。 接著說明場效電晶體400的製造方法。場效電晶體400 係使用半導體基板300來製造。於半導體基板3〇〇的第5 結晶層306上’升> 成閘極電極408以及以遠離閘極電極408 並隔著閘極電極408之方式形成2層歐姆電極406。 構成歐姆電極406及閘極電極408之金屬，例如可藉 由蒸鍍法、濺鍍法或CVD法來形成。可使用微影技術來形 成為期望的形狀。亦可藉由微影技術與舉離（lift off)法 之組合來形成歐姆電極406及閘極電極408❶為了獲得更 佳的歐姆接觸性，歐姆電極406較佳為進行退火處理。就 退火條件而言’可列舉出在氮氣環境中在8〇〇t：下進行30 秒的熱處理。 [實施例] 首先準備以（111)面為主面之2吋Si基板作為基層基 板102。於Si基板上的整面，使氧化矽層堆積作為阻礙層 16 323405 201214700 302。氧化矽層係以濺鍍法堆積150ηιη的厚度。於氧化矽層 上’藉由微影技術形成具有1〇〇見方的開口之感光性樹 脂’並以感光性樹脂為遮罩將氧化碎層與自然氧化膜進行 濕式蝕刻，而使Si基板露出。 去除感光性樹脂後’將S i基板送入蠢晶成長爐，進行 表面前處理後，將原料氣體供給至爐内，藉由磊晶成長來 形成界面控制層、作為第1結晶層1〇4的緩衝層、作為第 3結晶層204的耗盡結晶層、通道層402及蕭特基層404。 各層的組成、厚度、Mg原子的摻雜濃度如第1表所示。 [第1表] 結晶層 組成 厚度（nm) % 濃度（cm—3) 蕭特基層 Alo.2Gao.8N 20 通道層 GaN 500 耗盡結晶層 Alo.3Gao.7N 150 2xl019 緩衝層 Alo.3Gao.7N 500 5xl020 界面控制層 Alo. 7Ga〇. 3N 10 為了進行比較，係製作出具有與第i表所記載者相同 之結晶構造，且在對應於缓衝層及耗盡結晶層之層中未掺 雜Mg原子之基板。以下，係將摻雜Mg原子^板^為「捧 雜基板」，未摻雜Mg原子之基板稱為「非摻雜基板」。 使用三曱基鎵（TMG)、三曱基銨（TMA)、雙^戊」二烯鎂 及氨（NH3)作為原料氣體。成長爐内的壓力係保持在 30kPa。原料氣體的載子氣體係使用魏。各層的成長中， 323405 17 201214700 係一邊控制各原料的供給量、基板溫度一邊來進行。 藉由SIMS來分析摻雜基板與非摻雜基板的結晶層，結 果於緩衝層及耗盡結晶層中，混入有5xl〇ncm-^ lxl〇18cm-3 的Si原子及5xl017cm·3至ixi〇i8cm-3的〇原子。 依序將歐姆電極、元件分離、閘極電極形成於摻雜基 板及非摻雜基板，而製作出場效電晶體。歐姆電極係從結 晶側依序構成為 Ti(l〇nm)/Ai(i5〇nm)/Ni(20nm)/Au (300nm)。歐姆電極係使用蒸鍍法、微影技術與舉離法來形 成。歐姆電極係於形成後係在氮氣環境中，在8〇〇1下實 施60秒的退火處理。 το件分離係藉由將氮離子注入來進行。注入的加速電 壓係設為20KeV及100KV。氮離子的摻雜量均設為1χ1〇Η cm2。閘極電極係從結晶側依序構成為Ni(15nm)/Au (200mn)。閘極電極可使用蒸錢法、微影技術與舉離法來形 成。所製作之電晶龍將使轉雜基板者稱為摻雜電晶 體，使用非摻雜基板者稱為非摻雜電晶體。 第6圖係顯示摻雜電晶體的ίν特性。第7圖係顯示非 摻雜電晶體的IV特性。IV純係碰姆電極之—（源極) 作為月景值，使賦予至另一歐姆電極（汲極）之電壓從變 化至10V為止，並評估此間於没極中流通之電流。此外， 係以IV為1階段，在使閘極電壓％從〇ν變化至_5V為止 來評估IV特性。 非摻雜電晶體中，在使閘極電壓變化之ov至_5¥為止 的範圍内’僅在有限的電壓範圍内觀察到汲極電流的調 323405 18 201214700 變。此外，北你 壓，汲極電作/雜電晶體中，即使施加負電壓作為閘極電 ^ 'Sir /ir 1 卜1。 相訝於办 圍（〇v至、，摻雜電晶體中，在所施加之閘極電壓的範 顯示出開〜5V)的全區中，可觀察到汲極電流的調變。此係 雜 极電璧對汲極電流具有良好的控制性。此外，摻 电曰日體中 、 此種非 及極電壓可爽止’而顯示出良好的夹止性。 子摻雜 >雜電晶體與換雜電晶體之性能差’為藉由將啦原 二於緩衝層及耗盡結晶層所得之效果。 薏 Μ述實施形態中，雖例示場效電晶體作為半導體裝 但亦可為雙載子電晶體、LED等之其他主動裝置。 【圖式簡單說明】 第1圖係為了評估Si原子及〇原子以何種程度進入 GaN層而進行實驗之二次離子質譜分析（SIMS)數據。 第2圖係顯示半導體基板1〇〇的剖面例。 第3圖係顯示半導體基板2〇〇的剖面例。 第4圖係顯示半導體基板300的剖面例。 第5圖係顯示場效電晶體4〇〇的剖面例。 第6圖係顯示摻雜電晶體的IV特性。 第7圖係顯示非摻雜電晶體的IV特性。 【主要元件符號說明】 1()〇半導體基板 102基層基板 104第1結晶層 200 半導體基板 19 323405 201214700 202 第2結晶層 204 第3結晶層 300 半導體基板 302 阻礙層 304 第4結晶層 306 第5結晶層 400 場效電晶體 402 通道層 404 蕭特基層 406 歐姆電極 408 閘極電極AlGaAs, InGaAs, InGaP, GaN, AlGaN, InGaN, InAlGaN. The thickness of the fourth crystal layer 304 may be in the range of 100 nni to i〇〇〇〇nin. The fifth crystal layer 306 forms a hetero interface with the fourth crystal layer 304, and the channel charge is excited at the hetero interface when the field effect transistor is fabricated. The 5 13 323405 201214700 crystal layer 306 may be a material which can form a hetero interface with the fourth crystal layer 304, such as GaAs, AlGaAs, InGaAs, InGaP, GaN, AlGaN, InAIN, AIN, and InAlGaN. The thickness of the fifth crystal layer 306 is determined within the range of the stress caused by the difference in lattice constant caused by the heterojunction crystallization within the elastic limit of the crystal, and can be determined by considering the conduction resistance and the withstand voltage of the transistor. The thickness of the fifth crystal layer 306 can be exemplified in the range of 1 nm to 300 nm. Next, a method of manufacturing the semiconductor substrate 300 will be described. First, the barrier layer 302 is formed in contact with the base substrate 102. An oxide layer, a nitride layer, or a hafnium oxynitride layer is formed, for example, by an evaporation method, a sputtering method, a thermal CVD method, a plasma CVD method, or the like as the barrier layer 302, and an opening is formed by etching. The opening is formed to a depth reaching the base substrate 1〇2. Alternatively, a mask made of Ni may be formed on the base substrate 102, and the barrier layer 302 may be formed by oxidizing, nitriding or oxidizing the Si surface exposed at the bottom of the opening of the mask. Oxidation can be applied to thermal oxidation, plasma oxidation, and the like. Nitriding can be carried out by introducing a nitrogen source such as ammonia onto the surface of the base substrate 102, and performing thermal nitridation or plasma nitridation. Next, the first crystal layer 104, the third crystal layer 204, the fourth crystal layer 304, and the fifth crystal layer 306 are sequentially laminated on the base substrate 1A2 at the bottom of the opening of the barrier layer 302. These crystal layers are preferably formed by epitaxial growth. Examples of the epitaxial growth method include an organometallic vapor phase growth method (hereinafter also referred to as MOCVD method), a molecular beam epitaxial growth method (hereinafter also referred to as MBE method), and a halide vapor phase growth method (hereinafter referred to as Also recorded as hvpe method). During the epitaxial growth process, no crystal 323405 14 201214700 layer is formed on the barrier layer 302. Therefore, the first crystal layer 104, the third crystal layer 204, the fourth crystal layer 304, and the fifth crystal layer 306 are formed only in the opening of the barrier layer 302. When formed by the MOCVD method, trimethylgallium (TMG), trimethylammonium (TMA), trimethylindium (TMI), or the like can be used as the raw material of the group 3 element. As the gas raw material, ammonia (NH3) or the like can be used. The carrier gas of the raw material can be a high purity hydrogen gas or a helium purity nitrogen gas. The epitaxial growth conditions are, for example, a reaction furnace internal pressure of 0.1 latm, a growth temperature of 100 (rc, a growth rate of 〇. i in the step of growing the aforementioned crystallites in the above-mentioned step, and the ith crystallization layer 1 〇 3 crystal layer At the time of growth of 204, at least one atom selected from the group consisting of % atomic, Be atom and G atom rib is selected as the atomic atom at the same time. That is, the edge - the second atom - grows by the twin crystal 2 into a crystal layer. At this time, the _ original _ difficult 3 lining material and 5 ^ together can be introduced into the reaction furnace. Doping raw materials can use dicyclopentadienyl magnesium, carbon tetrachloride, diethyl zinc, bismuth Cyclopentadienyl ruthenium, etc. It is also possible to form impurity crystal atoms by ion-injection diffusion or the like after forming a crystal precursor layer and a third crystal precursor layer which are not contained as a hetero atom (a) 2 atom by a stray crystal. It is mixed with the (four) (four) layer, and the first crystal layer 104 and the third crystal layer 204. Fig. 5 is a cross-sectional view showing the field effect transistor _. The field effect transistor 400 has the base substrate 102 and the first crystal layer 1 〇4, third crystal layer leg, barrier layer 302, channel layer 402, Schottky layer 404, ohmic electrode day and gate electrode 408. The base substrate 1 2 in the transistor 40 , the second crystal layer 104 , the third crystal layer 204 , and the interlayer substrate are bonded to the semiconductor substrate 323405 15 201214700 100 , the semiconductor substrate 200 , and the base substrate in the semiconductor substrate 300 . 102. The first crystal layer 104, the third crystal layer 204, and the barrier layer 302 are the same. The channel layer 402 and the Schottky layer 404 are the same as the fourth crystal layer 304 and the fifth crystal layer 306 of the semiconductor substrate 300, and are formed by The ohmic electrode 406 and the gate electrode 408 form the fourth crystal layer 304 and the fifth crystal layer 306 as the channel layer 402 and the Schottky layer 404, respectively. The ohmic electrode 406 is connected to the field effect transistor 400 and an external circuit. 406, a laminated metal structure of Ti/Au from the Schottky layer 404 side can be exemplified. The gate electrode 408 inputs a signal to the field effect transistor 400. As for the gate electrode 408, a Schottky layer can be exemplified. The 404 side is a laminated metal structure of Ni/Au. Next, a method of manufacturing the field effect transistor 400 will be described. The field effect transistor 400 is manufactured using the semiconductor substrate 300. On the fifth crystal layer 306 of the semiconductor substrate 3' > gate electrode 408 And forming a two-layer ohmic electrode 406 away from the gate electrode 408 and interposing the gate electrode 408. The metal constituting the ohmic electrode 406 and the gate electrode 408 can be, for example, by an evaporation method, a sputtering method, or a CVD method. Forming. The lithography technique can be used to form the desired shape. The ohmic electrode 406 and the gate electrode 408 can also be formed by a combination of lithography and lift off, in order to obtain better ohmic contact. The ohmic electrode 406 is preferably annealed. As the annealing conditions, heat treatment at 30 Torr in a nitrogen atmosphere for 30 seconds can be cited. [Examples] First, a 2-inch Si substrate having a (111) plane as a main surface was prepared as the base layer substrate 102. On the entire surface of the Si substrate, a layer of ruthenium oxide is deposited as a barrier layer 16 323405 201214700 302. The ruthenium oxide layer is deposited to a thickness of 150 nm by sputtering. On the yttrium oxide layer, a photosensitive resin having an opening of 1 square is formed by lithography, and the oxidized layer and the natural oxide film are wet-etched with a photosensitive resin as a mask to expose the Si substrate. . After the photosensitive resin is removed, the Si substrate is sent to a doped crystal growth furnace, and after the surface pretreatment, the raw material gas is supplied into the furnace, and the interface control layer is formed by epitaxial growth to form the first crystal layer 1〇4. The buffer layer, the depleted crystal layer as the third crystal layer 204, the channel layer 402, and the Schottky layer 404. The composition, thickness, and doping concentration of Mg atoms of each layer are shown in Table 1. [Table 1] Crystal layer composition thickness (nm) % Concentration (cm-3) Schott base layer Alo.2Gao.8N 20 channel layer GaN 500 depleted crystal layer Alo.3Gao.7N 150 2xl019 Buffer layer Alo.3Gao.7N 500 5xl020 interface control layer Alo. 7Ga〇. 3N 10 For comparison, the same crystal structure as that described in the i-th table is produced, and is undoped in the layer corresponding to the buffer layer and the depleted crystal layer. A substrate of Mg atoms. Hereinafter, the doped Mg atomic plate is referred to as a "doped substrate", and the substrate not doped with Mg atoms is referred to as an "non-doped substrate". Trimethyl sulfide (TMG), trimethyl ammonium (TMA), bis-penta-diene magnesium, and ammonia (NH3) are used as source gases. The pressure in the growth furnace is maintained at 30 kPa. The carrier gas system of the raw material gas uses Wei. In the growth of each layer, 323405 17 201214700 is performed while controlling the supply amount of each raw material and the substrate temperature. The crystal layer of the doped substrate and the undoped substrate is analyzed by SIMS, and as a result, 5×l〇ncm-^lxl〇18cm-3 of Si atoms and 5xl017cm·3 to ixi〇 are mixed in the buffer layer and the depleted crystal layer. I8cm-3 〇 atom. A field effect transistor is fabricated by sequentially forming an ohmic electrode, a device isolation, and a gate electrode on a doped substrate and an undoped substrate. The ohmic electrode was sequentially formed from the crystal side as Ti(l〇nm)/Ai(i5〇nm)/Ni(20 nm)/Au (300 nm). The ohmic electrode is formed by a vapor deposition method, a lithography technique, and a lift-off method. The ohmic electrode was formed in a nitrogen atmosphere after formation, and an annealing treatment was performed for 60 seconds at 8 °C. The separation of το is performed by injecting nitrogen ions. The injected acceleration voltage is set to 20KeV and 100KV. The doping amount of nitrogen ions was set to 1χ1〇Η cm2. The gate electrode is sequentially formed of Ni (15 nm)/Au (200 nm) from the crystal side. The gate electrode can be formed using a steaming method, a lithography technique, and a lift-off method. The fabricated microcrystalline dragon will be referred to as a doped electro-crystal, and the non-doped substrate will be referred to as an undoped transistor. Figure 6 shows the ίν characteristics of the doped transistor. Figure 7 shows the IV characteristics of an undoped transistor. - (Source) of the IV pure electrode is used as the moon value, the voltage applied to the other ohmic electrode (drain) is changed from 10V to 10V, and the current flowing in the pole is evaluated. Further, the IV characteristic was evaluated by changing the gate voltage % from 〇ν to _5V in the first step of IV. In the undoped transistor, within the range of ov to _5 ¥ which changes the gate voltage, the adjustment of the drain current is observed only in a limited voltage range. In addition, North you pressure, bungee electric / hybrid crystal, even if a negative voltage is applied as the gate electric ^ 'Sir /ir 1 Bu 1 . It is surprisingly observed that in the entire region (〇v to, in a doped transistor, the applied gate voltage shows an open ~5V), the modulation of the drain current can be observed. This system has good controllability to the radian current. In addition, in the doped body, the non-polar voltage can be refreshed and exhibits good pinchability. The sub-doping > poor performance of the hybrid crystal and the modified transistor is the effect obtained by disposing the second layer on the buffer layer and depleting the crystal layer. In the embodiment described above, the field effect transistor is exemplified as a semiconductor device, and may be another active device such as a bipolar transistor or an LED. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a secondary ion mass spectrometry (SIMS) data for the purpose of evaluating the extent to which Si atoms and germanium atoms enter the GaN layer. Fig. 2 is a view showing an example of a cross section of a semiconductor substrate 1A. Fig. 3 is a view showing an example of a cross section of a semiconductor substrate 2A. Fig. 4 is a view showing an example of a cross section of the semiconductor substrate 300. Fig. 5 is a cross-sectional view showing a field effect transistor 4A. Figure 6 shows the IV characteristics of a doped transistor. Figure 7 shows the IV characteristics of an undoped transistor. [Description of main component symbols] 1 () 〇 semiconductor substrate 102 base substrate 104 first crystal layer 200 semiconductor substrate 19 323405 201214700 202 second crystal layer 204 third crystal layer 300 semiconductor substrate 302 barrier layer 304 fourth crystal layer 306 fifth Crystal layer 400 field effect transistor 402 channel layer 404 Schottky layer 406 ohm electrode 408 gate electrode

Claims (1)

201214700 七、申請專利範圍： 1. 一種半導體基板，係具有基層基板、以及形成於前述基 層基板上或上方之第1結晶層； 前述第1結晶層係3-5族化合物半導體層，其係含 有·選擇自以氧原子及矽原子所組成之群組之至少1 個原子的第1原子；以及具有作為受體的功能之至少1 個原子的第2原子。 2. 如申請專利範圍第1項所述之半導體基板，其中，前述 第2原子係選擇自以Mg原子、Zn原子、Be原子及c 原子所組成之群組之至少1個原子。 3·如申請專利範圍第1項所述之半導體基板，復具有：形 成於前述第1結晶層的上方之第2結晶層；以及形成於 刖述第1結晶層與前述第2結晶層之間之第3結晶層； m述第2結晶層及前述第3結晶層為3-5族化合物 半導體層； 前述第3結晶層具有前述第2原子； 前述第3結晶層中所含有之前述第2原子的總數， 較削述第1結晶層中所含有之前述第2原子的總數更 少。 ’ 4.如申請專利範圍第3項所述之半導體基板，其中，前述 第2結晶層具有作為半導體主動元件的活性層之功能。 5· ^申請專利範圍第3項所述之半導體基板，其中，前述 第3結晶層處於耗盡狀態。 6·如申請專利範圍第3項所述之半導體基板，其中，前述 323405 1 201214700 第1結晶層、前述第2結晶層及前述第3結晶層為3-5 族氡化物半導體層。 7. 如申請專利範圍第1項所述之半導體基板，復具有形成 於前述基層基板上或上方之阻礙層； 前述阻礙層具有開口； 前述阻礙層係阻礙結晶成長； 前述阻礙層含有前述第1原子； 前述第1結晶層係形成於前述開口。 8. 如申請專利範圍第7項所述之半導體基板，其中，前述 阻礙層為氧化矽層、氮化矽層或氮氧化矽層。 9. 一種半導體裝置，係具有基層基板、形成於前述基層基 板上或上方之第1結晶層、以及形成於前述第1結晶層 上或上方之活性層； 前述第1結晶層係3-5族化合物半導體層，其係含 有：選擇自以氧原子及矽原子所組成之群組之至少1 個原子的第1原子、以及具有作為受體的功能之至少1 個原子的第2原子。 10. —種半導體基板的製造方法，係具有： 將含有選擇自以氧原子及矽原子所組成之群組之 至少1個原子的第1原子且阻礙結晶成長之阻礙層，形 成於基層基板上或上方之步驟； 於前述阻礙層形成開口之步驟，以及 一邊將具有作為受體的功能之至少1個原子的第2 原子導入於前述開口的内部，一邊藉由蠢晶成長來形成 2 323405 201214700 3-5族化合物半導體的第1結晶層之步驟。 11. 一種半導體基板的製造方法，係具有： 將含有選擇自以氧原子及矽原子所組成之群組之 至少1個原子的第1原子且阻礙結晶成長之阻礙層，形 成於基層基板上或上方之步驟， 於前述阻礙層形成開口之步驟， 藉由磊晶成長將3-5族化合物半導體的第1結晶前 驅物層形成於前述開口的内部之步驟，以及 以具有作為受體的功能之至少1個原子的第2原子 來摻雜前述第1結晶前驅物層，藉此形成第1結晶層之 步驟。 12. 如申請專利範圍第10項所述之半導體基板的製造方 法，其中，前述阻礙層為氧化矽層、氮化矽層或氮氧化 石夕層。 3 323405201214700 VII. Patent Application Range: 1. A semiconductor substrate having a base layer substrate and a first crystal layer formed on or above the base layer substrate; wherein the first crystal layer is a Group 3-5 compound semiconductor layer containing - a first atom selected from at least one atom of a group consisting of an oxygen atom and a helium atom; and a second atom having at least one atom functioning as a receptor. 2. The semiconductor substrate according to claim 1, wherein the second atomic system is selected from at least one atom consisting of a group consisting of a Mg atom, a Zn atom, a Be atom, and a c atom. The semiconductor substrate according to claim 1, further comprising: a second crystal layer formed above the first crystal layer; and a first crystal layer and the second crystal layer a third crystal layer; the second crystal layer and the third crystal layer are a group 3-5 compound semiconductor layer; the third crystal layer has the second atom; and the second layer included in the third crystal layer The total number of atoms is smaller than the total number of the aforementioned second atoms contained in the first crystal layer. 4. The semiconductor substrate according to claim 3, wherein the second crystal layer has a function as an active layer of a semiconductor active device. The semiconductor substrate according to claim 3, wherein the third crystal layer is in a depleted state. The semiconductor substrate according to claim 3, wherein the 323405 1 201214700 first crystal layer, the second crystal layer, and the third crystal layer are 3-5 family telluride semiconductor layers. 7. The semiconductor substrate according to claim 1, further comprising a barrier layer formed on or above the base substrate; the barrier layer has an opening; the barrier layer inhibits crystal growth; and the barrier layer includes the first An atom; the first crystal layer is formed in the opening. 8. The semiconductor substrate according to claim 7, wherein the barrier layer is a hafnium oxide layer, a tantalum nitride layer or a hafnium oxynitride layer. A semiconductor device comprising: a base layer substrate; a first crystal layer formed on or above the base layer substrate; and an active layer formed on or above the first crystal layer; The compound semiconductor layer contains a first atom selected from at least one atom of a group consisting of an oxygen atom and a ruthenium atom, and a second atom having at least one atom functioning as a receptor. 10. A method of producing a semiconductor substrate, comprising: forming a barrier layer containing at least one atom of at least one atom selected from the group consisting of an oxygen atom and a ruthenium atom and preventing crystal growth from being formed on a base substrate; Or a step of forming an opening in the barrier layer and introducing a second atom having at least one atom as a function of the acceptor into the opening, and forming by a stupid crystal growth 2 323405 201214700 The step of the first crystal layer of the Group 3-5 compound semiconductor. A method for producing a semiconductor substrate, comprising: forming a barrier layer containing at least one atom selected from a group consisting of an oxygen atom and a ruthenium atom and preventing crystal growth from being formed on a base substrate or In the above step, the step of forming the opening in the barrier layer, the step of forming the first crystal precursor layer of the Group 3-5 compound semiconductor into the inside of the opening by epitaxial growth, and having the function as a receptor The step of forming the first crystal layer by doping the first crystal precursor layer with at least one atom of the second atom. 12. The method of producing a semiconductor substrate according to claim 10, wherein the barrier layer is a hafnium oxide layer, a tantalum nitride layer or a oxynitride layer. 3 323405
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