WO2011125261A1 - 増幅回路及び無線通信装置 - Google Patents
増幅回路及び無線通信装置 Download PDFInfo
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- WO2011125261A1 WO2011125261A1 PCT/JP2010/072379 JP2010072379W WO2011125261A1 WO 2011125261 A1 WO2011125261 A1 WO 2011125261A1 JP 2010072379 W JP2010072379 W JP 2010072379W WO 2011125261 A1 WO2011125261 A1 WO 2011125261A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/04—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in discharge-tube amplifiers
- H03F1/06—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in discharge-tube amplifiers to raise the efficiency of amplifying modulated radio frequency waves; to raise the efficiency of amplifiers acting also as modulators
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
- H03F1/0216—Continuous control
- H03F1/0222—Continuous control by using a signal derived from the input signal
- H03F1/0227—Continuous control by using a signal derived from the input signal using supply converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
- H03F1/3247—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits using feedback acting on predistortion circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/102—A non-specified detector of a signal envelope being used in an amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/15—Indexing scheme relating to amplifiers the supply or bias voltage or current at the drain side of a FET being continuously controlled by a controlling signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/207—A hybrid coupler being used as power measuring circuit at the output of an amplifier circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2201/00—Indexing scheme relating to details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements covered by H03F1/00
- H03F2201/32—Indexing scheme relating to modifications of amplifiers to reduce non-linear distortion
- H03F2201/3233—Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion
Definitions
- the present invention relates to an amplifier circuit used for amplifying signal power mainly in a wireless communication apparatus.
- a high-power amplifier (HPA: High Power Amplifier) is used in a wireless communication apparatus installed in a mobile phone base station.
- HPA High Power Amplifier
- an envelope tracking method also referred to as a power supply modulation method or a bias modulation method
- the power supply voltage of the amplifier dynamically changes in accordance with the envelope of the RF signal. Therefore, when the amplitude of the RF signal is small, the operating power of the amplifier is suppressed, and as a result, the power efficiency is improved.
- an object of the present invention is to provide an amplifier circuit that easily realizes synchronization between an input signal applied to an amplifier used in an envelope tracking method and a power supply voltage. .
- An amplifier circuit includes an amplifier that amplifies power of an input signal, a power supply modulation unit that applies a power supply voltage modulated based on the input signal to the amplifier, and an output that is delayed with respect to the input.
- a timing adjustment unit having a finite number of adjustment values for adjusting the time to be adjusted, and capable of adjusting a time difference between the input signal and the power supply voltage reaching the amplifier by selecting the adjustment value; and the input signal
- a test signal output unit capable of repeatedly transmitting a predetermined test signal at a predetermined cycle, k is an arbitrary natural number, and m is an arbitrary natural number satisfying m ⁇ k.
- m-cycle output power of the amplifier is sequentially measured to find an adjustment value that maximizes the sum or average of m-cycle output power.
- Te in which an adjusting value determining unit that sets the adjustment value to the timing adjuster.
- the amplifier circuit configured as described above, instead of trying to measure the mutual time difference between the input signal reaching the amplifier and the power supply voltage, that is, the timing deviation, the timing deviation and the output power for m cycles of the amplifier.
- the adjustment value that maximizes the sum or average of the output power is searched, and the adjustment value is set in the timing adjustment unit. Thereby, the timing shift is eliminated.
- by repeatedly sending a predetermined test signal it is possible to accurately compare the sum or average of output power for m periods.
- the test signal preferably has the same frequency band as that of the input signal during normal operation other than during testing. In this case, the accuracy of timing adjustment based on the test signal and the ease of adjustment can be appropriately ensured. If the frequency band of the test signal is wider than the frequency band of the input signal in normal operation, the accuracy is improved but the adjustment becomes difficult. Conversely, if the frequency band is narrow, the adjustment is easy but the accuracy is lowered.
- a distortion compensation unit having a function of adding an inverse distortion characteristic to cancel an input / output distortion characteristic in the amplifier to the input signal is provided.
- the output unit may transmit a test signal in a state where the function of the distortion compensation unit is suspended at the time of initial setting as the amplifier circuit.
- timing adjustment is performed to appropriately set an initial value of the adjustment value.
- the distortion compensation unit processes the input / output characteristics of the amplifier. Distortion can be removed. If it is attempted to execute the process (b) without the process (a), it takes a long time to find an appropriate distortion compensation characteristic. However, the initial value of the timing adjustment is obtained by performing the process (a) first. Since it is set appropriately, appropriate distortion compensation can be quickly performed in the process (b).
- the adjustment value determining unit preferably includes a storage unit capable of storing output power for m cycles.
- the output power for exactly m cycles can be acquired no matter where the acquisition starts for the k-cycle signal, and there is no need to acquire it while monitoring (counting) m cycles.
- the test signal includes only a signal that does not repeat the same within one period.
- the same waveform is not repeated within one cycle, it is sufficient that one cycle of the test signal can recognize a signal over the length (time) of one cycle, and the start point and end point of one cycle are recognized.
- the test signal output unit and the adjustment value determination unit do not have to be synchronized. Therefore, the timing adjustment process is easy. Also, a plurality of adjustment value candidates for maximum power do not appear, and it is easy to search for an adjustment value for maximum power.
- the adjustment can be performed with high accuracy.
- the wireless communication device of the present invention is equipped with the amplifier circuit of (1) above.
- Such a wireless communication apparatus can easily realize synchronization between an input signal applied to an amplifier used in an envelope tracking method in an amplifier circuit and a power supply voltage. Therefore, the power efficiency of the wireless communication device can be increased.
- FIG. 8 is an example of a configuration diagram of a wireless communication system having a wireless communication device ST of a wireless base station and wireless communication devices T1, T2, and T3 as terminal devices.
- the wireless communication device ST includes a transmitter S for transmitting a wireless signal, a receiver R for receiving a wireless signal, and a processing unit P for processing a transmission / reception signal.
- the wireless communication devices T1 to T3 basically have the same internal configuration.
- the transmitter S transmits a linear modulation signal and has an amplifier circuit 1 for amplifying the linear modulation signal.
- the receiver R receives a linear modulation signal and has an amplifier circuit 1 for receiving and amplifying the linear modulation signal. Since the basic configuration of the amplifier circuit 1 is the same for both the transmitter S and the receiver R, the amplifier circuit 1 of the transmitter S will be described below as a representative example.
- FIG. 1 is a block circuit diagram showing an amplifier circuit 1 according to an embodiment of the present invention.
- the amplifier (HPA) 100 is supplied with a power supply voltage (hereinafter referred to as a drain voltage) modulated by the power supply modulation section 1A based on an input signal (digital signal).
- the power supply modulation unit 1A includes a detection unit 101 that detects an input signal and extracts an envelope signal, a timing adjustment unit 103 that adjusts a time during which an output is delayed with respect to the input, and a power-voltage for the envelope signal.
- a power-voltage conversion unit 102 that performs conversion and a voltage control unit 104 that finally performs D / A conversion and applies a drain voltage to the amplifier 100 are provided.
- the timing adjustment unit 106 for adjusting the delay time of the output with respect to the input and the distortion characteristic of the amplifier 100 are compensated.
- Distortion compensation unit (DPD: Digital Pre-Distorter) 105 and D / A converter 107 are provided.
- the distortion compensation unit 105 monitors the input / output signal of the amplifier 100 (the output monitoring circuit for distortion compensation is not shown), and grasps the input / output characteristics of the amplifier 100 from the input / output signal. . Then, the distortion compensator 105 cancels the distortion in the amplifier 100 by adding a reverse characteristic of the distorted input / output characteristic to the input signal.
- Each of the two timing adjustment units 103 and 106 is, for example, a digital filter constituting an FIR filter, and can perform a process of delaying a signal by a predetermined time by appropriately adjusting the phase without changing the amplitude.
- the adjustment value d1 of the timing adjustment unit 106 on the gate side can be set to any one of ( ⁇ + 1) from 0 to ⁇ ( ⁇ is an integer). is there.
- the adjustment value d2 of the timing adjustment unit 103 on the drain side can be set to any one of ( ⁇ + 1) from 0 to ⁇ ( ⁇ is an integer).
- the values of ⁇ and ⁇ are represented by (power of 2 ⁇ 1) such as 127 and 255.
- the timing adjustment units 103 and 106 have a finite number of adjustment values for adjusting the delay time of the output with respect to the input, and the gate signal as the input signal reaching the amplifier 100 and the drain voltage The mutual time difference can be adjusted by selecting these adjustment values d1 and d2.
- the timing adjustment unit may basically be provided only on either the gate side or the drain side. However, as an example for realizing more precise adjustment, in the present embodiment, the gate side and the drain of the amplifier 100 are provided. Two timing adjustment units 103 and 106 provided on both sides constitute a timing adjustment unit 1B that synchronizes the gate signal reaching the amplifier 100 and the drain voltage.
- the electric power output from the amplifier 100 is detected by the directional coupler 111 and supplied to the adjustment value determining unit 109 via the A / D converter 112.
- the adjustment value determination unit 109 has a storage unit (memory) 110 therein, and can sequentially store power data output from the amplifier 100.
- the adjustment value determination unit 109 has a function of instructing the two timing adjustment units 103 and 106 which adjustment values d1 and d2 should be selected.
- the test signal output unit 108 can send a predetermined test signal to the electric circuit of the input signal. However, the test signal is sent out as a pseudo input signal at the time of initial setting before normal operation (initial operation before communication).
- the test signal output unit 108 transmits a test signal according to an instruction from the adjustment value determination unit 109. Further, the adjustment value determination unit 109 can instruct the distortion compensation unit 105 whether or not to perform a distortion compensation operation.
- the test signal is repeatedly sent at a predetermined cycle.
- This test signal has the same frequency band as that of the input signal during normal operation other than during testing. Thereby, the precision of the timing adjustment based on the test signal and the ease of the adjustment can be appropriately ensured. If the frequency band of the test signal is wider than the frequency band of the input signal in normal operation, the accuracy is improved but the adjustment becomes difficult. Conversely, if the frequency band is narrow, the adjustment is easy but the accuracy is lowered.
- the test signal includes only signals that do not repeat the same within one cycle, and the same waveform is not repeated within one cycle.
- the period of the test signal only needs to be able to recognize a signal over the length (time) of one period, and it is not necessary to recognize the start point and end point of one period. For this reason, the test signal output unit 108 and the adjustment value determination unit 109 need not be synchronized. Therefore, the timing adjustment process is easy.
- a peak appears at one location within one cycle of the test signal. In this case, since the change of the output signal appears remarkably with respect to the timing shift, the adjustment can be performed with higher accuracy.
- the voltage control unit 104 controls the D / A converter 107, the A / D converter 112, and the directional coupler 111 that handle analog signals in the amplifier 100 and its surroundings. It is a digital circuit element and can be configured by software, for example, by a DSP.
- the digital circuit element indicates the presence of a functional element, and each element does not necessarily have to be separated and independent.
- the amplifier circuit 1 configured as described above, if the timing adjustment has already been completed, distortion (pre-distortion) is added to the input signal by the distortion compensator 105.
- the distortion-added input signal is subjected to a delay process for the adjustment value set in the timing adjustment unit 106, converted to an analog signal, and reaches the amplifier 100 as a gate signal.
- the envelope signal obtained in the detection unit 101 from the input signal is subjected to a delay process of the adjustment value set in the timing adjustment unit 103, and then converted into a voltage signal by the power-voltage conversion unit 102, and the voltage control unit 104 Is converted to an analog drain voltage and reaches the amplifier 100.
- the timing of the gate signal and the arrival of the drain voltage is synchronized by the timing adjustment, and the amplifier 100 can be operated by the envelope tracking method.
- timing adjustment will be described in detail.
- the present embodiment will be described based on the theory that the timing coincides, that is, the output of the amplifier 100 becomes maximum when the gate signal and the drain voltage reaching the amplifier 100 are synchronized with each other. Adjust the timing. First, this theory will be explained.
- Condition 1 refers to FIG. 2, in which output power is G for all u satisfying the relationship of u sat > u 1 > u 2 (where u sat is a saturated region, u 1 and u 2 are non-saturated regions). The relationship of (V, u 1 )> G (V, u 2 ) is satisfied. That is, in the non-saturated region, the output power increases monotonously with the increase in input power.
- condition 3 is that at least one set of V 1 ⁇ V 2 satisfying the relationship of G (V 1 , u) ⁇ G (V 2 , u) exists with reference to FIG. That is, the characteristics of the output power can be made different by setting the drain voltage to a different value.
- Condition 4 is an amplifier circuit that operates in an envelope tracking system.
- the input signal in the amplifier circuit 1 is x [t] using the time t
- the input signal to the amplifier 100 is represented as u (x [t]).
- the drain voltage is represented as V (x [t]).
- V [t] x [t]
- the input power and drain voltage of the amplifier 100 are respectively u [t].
- V (u [t]) V (u [t]
- FIG. 5 is a graph showing the relationship between the input power u and the output power P related to the condition 5.
- the conversion characteristic of the conversion function V is V as a function of u such that the saturation operating point shown in FIG. That is, the conversion function V that satisfies the condition 2 for the amplifier 100 is used.
- the conversion function needs to be monotonous, and uses a conversion function V that satisfies V (u 1 ) ⁇ V (u 2 ) for u 1 > u 2 .
- FIG. 6 is a graph showing the relationship between the input power u and the output power P related to the composite condition. Referring to FIG. 6, when the above conditions 1, 3 and 6 are combined, G (V (u 1 ), u 1 )> G (V (u (u)) for all u satisfying u 1 > u 2. The relationship of 2 ) and u 2 ) is a condition related to monotonicity.
- the test signal to be the input signal u (t) is a periodic signal of period n ⁇ Ts that outputs [x 0 , x 1 ,..., X n-1 ] at every sampling period T S of digital processing. It is.
- the output from time 0 to n ⁇ T S when the difference in timing between u [t] and V (u [t]) is ⁇ t (0 ⁇ ⁇ t ⁇ n ⁇ T S ).
- N 1 , N 2 , and N 3 are the following sets, respectively.
- N 2 set of n satisfying u [n ⁇ T S + ⁇ t] ⁇ u [n ⁇ T S ]
- N 3 Set of n satisfying u [n ⁇ T S + ⁇ t]> u [n ⁇ T S ]
- P Lower ( ⁇ t) can be expressed as follows from Condition 2.
- P even ( ⁇ t), P Lower ( ⁇ t), and P Higher ( ⁇ t) P sum ( ⁇ t) is expressed as follows.
- FIG. 7 is a flowchart illustrating an example of timing adjustment processing. This timing adjustment is performed at the time of initial setting of the amplifier circuit 1, that is, before normal operation.
- the main components of the processing are the adjustment value determining unit 109 and the test signal output unit 108 in FIG.
- the adjustment value determination unit 109 resets the adjustment values d1 and d2 to the timing adjustment units 106 and 103, respectively (step S1). Thereby, for example, both the adjustment values d1 and d2 are set to 0. At this time, the adjustment value determination unit 109 pauses its function so that the distortion compensation unit 105 does not operate. The distortion compensation unit 105 in the idle state outputs the input as it is. Next, the adjustment value determining unit 109 sends one cycle of the test signal from the test signal output unit 108 as [x 0 , x 1 ,..., X n-1 ] and sends it for k cycles (step S2). .
- k is an arbitrary natural number.
- the output power of the amplifier 100 is detected by the directional coupler 111, converted into a digital value by the A / D converter 112, and input to the adjustment value determination unit 109.
- the adjustment value determination unit 109 stores the m-cycle output power (raw waveform) in the storage unit 110
- the adjustment value determination unit 109 calculates the sum (P sum ) of the output power and determines the adjustment value separately from the m-cycle output power.
- the information is stored in the unit 109 (step S3).
- m is an arbitrary natural number that satisfies m ⁇ k.
- the storage unit 110 capable of storing output power for m cycles can acquire output power for exactly m cycles regardless of where the acquisition starts for a k cycle signal. That is, there is an advantage that it is not necessary to acquire (counting) m periods.
- step S3 is executed, and thereafter step S4 ⁇ S5 or step S4 ⁇ S6 is executed.
- the adjustment value determination unit 109 searches the data of the ⁇ total sums P sum for an adjustment value d1 at which the total sum P sum has the maximum power (step S1). S6), d1 is set to that value (step S7).
- the calculation of the output power for each m period may be an average instead of the sum.
- the test signal includes only signals that do not repeat in the same period, and the same waveform is not repeated. Accordingly, a plurality of adjustment value d1 candidates for the maximum power do not appear, and it is easy to search for the adjustment value d1 for the maximum power (the same applies to the adjustment value d2 described later). That is, when the same waveform repeats with a time difference ⁇ within one cycle, for example, when the adjustment value is 0 and when the adjustment value ⁇ , the output power is the same, and there are multiple adjustment value candidates that are the maximum power. May appear. In addition to including only signals that do not repeat the same, it is preferable that a peak appears at one location within one cycle of the test signal. In this case, since the change of the output signal appears remarkably with respect to the timing shift, the adjustment can be performed with higher accuracy.
- the adjustment value determining unit 110 fixes d1 to the above value, and this time, the test signal output unit 108 extracts one period of the test signal [x 0 , x 1 , ..., X n-1 ] are transmitted for k periods (step S8). Further, when the adjustment value determining unit 109 stores the output power (raw waveform) for m cycles in the storage unit 110, the adjustment value determination unit 109 calculates the sum (P sum ) of the output power, and separately from the output power of m cycles, It is stored in the adjustment value determination unit 109 (step S9).
- step S8 a sufficient time (time until the signal reaches the storage unit 110 via the D / A converter 107, the amplifier 107, and the A / D converter 112 after the test signal is transmitted by executing step S8). ) Elapses, step S9 is executed, and thereafter step S10 ⁇ S11 or step S10 ⁇ S12 is executed.
- the adjustment value determination unit 109 searches the adjustment value d2 at which the total sum P sum has the maximum power from the ⁇ total sum P sum data (step S1). S12), d2 is set to that value (step S13).
- the calculation of the output power for each m period may be an average instead of the sum.
- the number of adjustment values relatively obtained by the two adjustment values d1 and d2, that is, the number of combinations is ⁇ ⁇ ⁇ , which is the number of times the test signal is sent in units of m cycles. is there.
- adjustment values d1 and d2 that maximize the sum (or average) of the output power of the amplifier 100 with respect to m cycles of the test signal are searched and set in the timing adjustment units 106 and 103, respectively. Is done.
- the time difference between the input signal reaching the amplifier 100 and the power supply voltage, that is, the timing shift is not measured, but the timing shift and the m period of the amplifier 100 are not measured. Focusing on the relationship with the output power of the minute, an adjustment value that maximizes the total (or average) of the output power is searched, and the adjustment value is set in the timing adjustment unit 1B. Thereby, the timing shift is eliminated.
- the radio communication apparatus (ST, T1 to T3 / FIG. 8) using the above-described amplifier circuit 1 is provided with an input signal and a power supply voltage applied to the amplifier 100 used in the envelope tracking system in the amplifier circuit 1. Can be easily realized, so that the power efficiency of the wireless communication apparatus can be improved.
- the amplifier circuit 1 can start normal operation. After normal operation starts, DPD processing by the distortion compensation unit 105 is performed together with envelope tracking. Thus, the amplifier circuit 1 (a) performs the timing adjustment first before operating the distortion compensation unit 105 to appropriately set the initial value of the adjustment value, and (b) DPD of the distortion compensation unit 105 during normal operation.
- the distortion in the input / output characteristics of the amplifier 100 can be removed by the processing. If it is attempted to execute the process (b) without the process (a), it takes a long time to find an appropriate distortion compensation characteristic. However, the initial value of the timing adjustment is obtained by performing the process (a) first. Since it is set appropriately, distortion compensation can be performed quickly in the process (b).
- the normal operation can be paused at any time after the start of the normal operation to adjust the timing.
- the adjustment values d1 and d2 have been described as being selected in ascending order from 0 to the maximum value. However, this is only an example, and may be in descending order. It is also possible to select to increase or decrease sequentially.
- timing adjustment units 103 and 106 are provided is not limited to the position shown in FIG.
- the timing adjustment unit 103 may be provided between the power-voltage conversion unit 102 and the voltage control unit 104
- the timing adjustment unit 106 is provided between the distortion compensation unit 105 and the D / A converter 107. May be.
- the embodiment disclosed this time should be considered as illustrative in all points and not restrictive.
- the scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.
- the amplifier circuit of the present invention or the wireless communication device using the same, it is possible to easily realize synchronization between the input signal applied to the amplifier used in the envelope tracking method and the power supply voltage.
Abstract
Description
この場合、テスト信号に基づくタイミング調整の精度、及び、調整の容易さを、それぞれ適切に確保することができる。仮にテスト信号の周波数帯域が通常運用における入力信号の周波数帯域より広いと、精度が向上するが調整が困難になり、逆に、狭いと、調整は容易になるが精度が低下する。
この場合、(a)歪補償部を動作させる前に、まずタイミング調整を行って調整値の初期値を適切に設定し、(b)通常運用時には歪補償部の処理によって増幅器の入出力特性における歪を除去することができる。(a)の処理無く(b)の処理を実行しようとすると、適切な歪補償の特性を見つけることに長い時間を要するが、(a)の処理を先に行うことによりタイミング調整の初期値が適切に設定されているので、(b)の処理では適切な歪補償を迅速に行うことができる。
この場合、k周期の信号に対してどこから取得を開始しても、ちょうどm周期分の出力電力を取得することができ、m周期分を監視しながら(数えながら)取得する必要が無い。
この場合、1周期内で同じ波形が繰り返されることもないので、テスト信号の1周期とは、1周期分の長さ(時間)にわたる信号を認識できればよく、1周期の始点・終点を認識する必要はない。そのため、テスト信号出力部と調整値決定部とで同期をとらなくてもよい、ということになる。従って、タイミング調整の処理が容易である。
また、最大電力となる調整値の候補が複数現れることが無く、最大電力となる調整値の探索が容易である。
なお、同じ繰り返しにならない信号のみを含むことに加えて、テスト信号の1周期内に、ピークが1箇所で出現する場合には、タイミングのずれに対して出力信号の変化が顕著に現れるため、さらに精度良く調整を行うことができる。
このような無線通信装置は、増幅回路においてエンベロープ・トラッキング方式で使用される増幅器に対して付与される入力信号と電源電圧との同期を容易に実現することができる。従って、無線通信装置の電力効率を高めることができる。
以下、本発明の一実施形態について、図面を参照して説明する。
図8は、無線基地局の無線通信装置STと、端末装置としての無線通信装置T1,T2,T3とを有する無線通信システムの構成図の一例である。無線通信装置STは、無線信号を送信するための送信機S、無線信号を受信するための受信機R、及び、送受信信号の処理を行う処理部Pを備えている。無線通信装置T1~T3も基本的に同様の内部構成を備えている。
図1は、本発明の一実施形態に係る増幅回路1を示すブロック回路図である。増幅器(HPA)100には、電源変調部1Aにより、入力信号(デジタル信号)に基づいて変調された電源電圧(以下、ドレイン電圧という。)が付与される。この電源変調部1Aは、入力信号を検波してエンベロープ信号を取り出す検波部101と、入力に対して出力が遅延する時間を調整するためのタイミング調整部103と、エンベロープ信号に対して電力‐電圧変換を行う電力‐電圧変換部102と、最終的にD/A変換を行って増幅器100にドレイン電圧を付与する電圧制御部104とを備えている。
なお、タイミング調整部は基本的には、ゲート側・ドレイン側のいずれか一方のみに設けてもよいが、より精密な調整を実現する一例として、本実施形態では、増幅器100のゲート側及びドレイン側の双方に設けた2つのタイミング調整部103,106によって、増幅器100に到達するゲート信号とドレイン電圧との同期をとるタイミング調整部1Bが構成されている。
上記テスト信号はデジタル信号であり、[x0,x1,・・・,xn-1]と表わされる。例えば(n-1)は8191(=213-1)である。
次に、タイミング調整について詳細に説明する。結論から先に述べると、本実施形態においては、タイミングの一致すなわち、増幅器100に到達するゲート信号とドレイン電圧とが互いに同期しているとき、増幅器100の出力が最大になる、という理論に基づいてタイミング調整を行う。まず、この理論から説明する。
[条件1]
条件1は、図2を参照して、usat>u1>u2(usatは飽和領域、u1,u2は非飽和領域)の関係を満たす全てのuについて、出力電力が、G(V,u1)>G(V,u2)の関係を満たすことである。すなわち、非飽和領域では入力電力の増加に応じて出力電力が単調に増加すること、である。
次に、条件2は、図3を参照して、u>usatを満たす全てのuについて、出力電力が、G(V,u)=G(V,usat)の関係を満たすことである。すなわち、飽和領域では出力電力が一定であること、である。
[条件3]
さらに、条件3は、図4を参照して、G(V1,u)≧G(V2,u)の関係を満たすV1≧V2が少なくとも1組存在することである。すなわち、ドレイン電圧を異なる値に設定することにより出力電力の特性を異なるものにできること、である。
条件4は、エンベロープ・トラッキング方式で動作する増幅回路であること、である。この場合、時間tを用いて、増幅回路1における入力信号をx[t]とすると、増幅器100への入力信号はu(x[t])と表される。また、ドレイン電圧はV(x[t])と表される。ここで、簡略化のため、u[t]=x[t]のとき、V[t]=V(u[t])で考えると、増幅器100の入力電力及びドレイン電圧はそれぞれ、u[t]及びV(u[t])と表すことができる。
[条件5]
変換関数Vの変換特性は、増幅器100の特性において図5に示す飽和動作点が存在するような、uの関数としてのVである、ということである。すなわち、増幅器100についての条件2を満たすような変換関数Vを用いるという意味である。
[条件6]
変換関数は、単調性が必要であり、u1>u2に対してV(u1)≧V(u2)となる変換関数Vを用いることである。
N1:u[n・TS+Δt]=u[n・TS]を満たすnの集合
N2:u[n・TS+Δt]<u[n・TS]を満たすnの集合
N3:u[n・TS+Δt]>u[n・TS]を満たすnの集合
次に、図1の増幅回路1におけるタイミング調整の実施例について説明する。図7は、タイミング調整の処理の一例を示すフローチャートである。このタイミング調整は、増幅回路1の初期設定時、すなわち通常運用の前に行われる。処理の主体となるのは、主として図1における調整値決定部109及びテスト信号出力部108である。
なお、時間的には、ステップS2の実行によりテスト信号が送出されてから十分な時間(信号がD/Aコンバータ107、増幅器107、A/Dコンバータ112を経て記憶部110に到達するまでの時間)が経過した後、ステップS3が実行され、その後、ステップS4→S5、又は、ステップS4→S6が実行される。
なお、各m周期分の出力電力の演算は、総和ではなく平均を求めるものであってもよい。
なお、時間的には、ステップS8の実行によりテスト信号が送出されてから十分な時間(信号がD/Aコンバータ107、増幅器107、A/Dコンバータ112を経て記憶部110に到達するまでの時間)が経過した後、ステップS9が実行され、その後、ステップS10→S11、又は、ステップS10→S12が実行される。
なお、各m周期分の出力電力の演算は、総和ではなく平均を求めるものであってもよい。
さらに、上記の増幅回路1を使用した無線通信装置(ST,T1~T3/図8)は、増幅回路1においてエンベロープ・トラッキング方式で使用される増幅器100に対して付与される入力信号と電源電圧との同期を容易に実現することができるので、無線通信装置としての電力効率を高めることができる。
なお、上記のタイミング調整は、通常運用前の初期設定時に行うものとしたが、通常運用の開始後も、随時、通常運用を休止させて、タイミング調整を行うことは可能である。
また、上記タイミング調整の実施例では、調整値d1,d2を0から最大値まで昇順に選択していくものとして説明したが、これは一例であり、降順でもよいし、さらには、特定の値から順次増加又は減少するように選択することも可能である。
なお、今回開示された実施の形態はすべての点で例示であって制限的なものではないと考えられるべきである。本発明の範囲は特許請求の範囲によって示され、特許請求の範囲と均等の意味及び範囲内での全ての変更が含まれることが意図される。
Claims (6)
- 入力信号の電力を増幅する増幅器と、
前記入力信号に基づいて変調された電源電圧を、前記増幅器に付与する電源変調部と、
入力に対して出力が遅延する時間を調整するための有限個数の調整値を有し、前記増幅器に到達する前記入力信号及び電源電圧の相互の時間差を、当該調整値の選択により調整可能なタイミング調整部と、
前記入力信号として所定のテスト信号を所定周期で繰り返し送出可能なテスト信号出力部と、
kは任意の自然数、mはm≦kを満たす任意の自然数とした場合において、前記テスト信号のk周期ごとに前記タイミング調整部における前記調整値を異なる値に変更させながら、前記増幅器のm周期の出力電力を順次測定し、m周期の出力電力の総和又は平均が最大になる調整値を探索して、当該調整値を前記タイミング調整部に設定する調整値決定部と
を備えたことを特徴とする増幅回路。 - 前記テスト信号は、テスト時以外の通常運用時の入力信号が有する周波数帯域と同じ周波数帯域を有する請求項1記載の増幅回路。
- 前記増幅器における入出力の歪特性を打ち消す逆歪特性を入力信号に付加する機能を有する歪補償部が設けられており、
前記テスト信号出力部は、当該増幅回路としての初期設定時に前記歪補償部の機能を休止させた状態で、前記テスト信号の送出を行う請求項1又は2に記載の増幅回路。 - 前記調整値決定部は、前記m周期分の出力電力を記憶可能な記憶部を含む請求項1~3のいずれか1項に記載の増幅回路。
- 前記テスト信号は1周期内に、同じ繰り返しにならない信号のみを含む請求項1~4のいずれか1項に記載の増幅回路。
- 増幅回路を搭載した無線通信装置であって、当該増幅回路は、
入力信号の電力を増幅する増幅器と、
前記入力信号に基づいて変調された電源電圧を、前記増幅器に付与する電源変調部と、
入力に対して出力が遅延する時間を調整するための有限個数の調整値を有し、前記増幅器に到達する前記入力信号及び電源電圧の相互の時間差を、当該調整値の選択により調整可能なタイミング調整部と、
前記入力信号として所定のテスト信号を所定周期で繰り返し送出可能なテスト信号出力部と、
kは任意の自然数、mはm≦kを満たす任意の自然数とした場合において、前記テスト信号のk周期ごとに前記タイミング調整部における前記調整値を異なる値に変更させながら、前記増幅器のm周期の出力電力を順次測定し、m周期の出力電力の総和又は平均が最大になる調整値を探索して、当該調整値を前記タイミング調整部に設定する調整値決定部と
を備えたことを特徴とする無線通信装置。
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