WO2011092783A1 - チャネル推定値補間回路及び方法 - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J11/00—Orthogonal multiplex systems, e.g. using WALSH codes
- H04J11/0023—Interference mitigation or co-ordination
- H04J11/0063—Interference mitigation or co-ordination of multipath interference, e.g. Rake receivers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0202—Channel estimation
- H04L25/022—Channel estimation of frequency response
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0202—Channel estimation
- H04L25/0224—Channel estimation using sounding signals
- H04L25/0228—Channel estimation using sounding signals with direct estimation from sounding signals
- H04L25/023—Channel estimation using sounding signals with direct estimation from sounding signals with extension to other symbols
- H04L25/0232—Channel estimation using sounding signals with direct estimation from sounding signals with extension to other symbols by interpolation between sounding signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
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- the present invention relates to a channel estimation value interpolation circuit and method, and more particularly, to a circuit and method for generating a virtual waveform of a channel estimation value outside a bandwidth when interpolating a channel estimation value in an OFDM (Orthogonal Frequency Frequency Division) Multiplexing method.
- OFDM Orthogonal Frequency Frequency Division
- a channel estimation value is generated from a reference signal, and equalization processing is performed using the channel estimation value, thereby canceling distortion generated in the radio transmission path. Reduce transmission errors.
- the wireless baseband standard of the OFDM system has been widely used because of its high transmission efficiency.
- reference signals used for channel estimation are often discretely arranged in the frequency direction. In this case, the channel estimation value can be obtained only discretely.
- FFT Fast Fourier Transform
- the subcarrier signal used in the OFDM system does not exist in the entire band where the FFT operation is performed.
- the reference signal used for channel estimation does not exist in the entire band where the FFT operation is performed, but actually exists only in a certain bandwidth in the entire band. For this reason, as shown in step S4 of FIG. 7, it is necessary to generate a virtual waveform of the channel estimation value outside the bandwidth by extrapolation or the like.
- Patent Document 1 As a technique for dealing with this problem, for example, in Patent Document 1, only a path position is extracted from a delay profile generated by inverse FFT operation, FFT operation is performed on the extraction result, and the operation result is discontinuous. A method for generating a virtual waveform by adjusting the position of a point is described.
- Patent Document 2 proposes a method for generating a virtual waveform by generating two tangents from a subcarrier signal within a bandwidth toward the outside of the bandwidth and multiplying the tangent by a window function. ing.
- an object of the present invention is to generate a virtual waveform of a channel estimation value outside the bandwidth more accurately while suppressing an increase in circuit scale when interpolating the channel estimation value in the OFDM method.
- a channel estimation value interpolation circuit includes an arithmetic unit that alternately performs an FFT operation and an inverse FFT operation, and a subcarrier within a predetermined bandwidth.
- a first buffer for storing a first channel estimation value estimated from a reference signal disposed in the second signal, a second buffer for storing a calculation result obtained by the calculator, the calculator, and the And a conversion circuit connected to the first and second buffers.
- the conversion circuit includes: (A) a straight line between channel estimation values corresponding to reference signals arranged at both ends of the bandwidth among the first channel estimation values stored in the first buffer.
- a process of extracting a channel estimation value corresponding to a subcarrier outside the band from the value is performed.
- the channel estimation value interpolation method includes (A) a first channel estimation estimated from a reference signal stored in advance and discretely arranged on subcarriers within a predetermined bandwidth.
- the channel estimation values corresponding to the reference signals arranged on both ends of the bandwidth are linearly interpolated to estimate the second channel estimation value corresponding to the subcarrier outside the bandwidth.
- the present invention it is possible to more accurately generate a virtual waveform of a channel estimation value outside the bandwidth while suppressing an increase in circuit scale when interpolating the channel estimation value in the OFDM scheme. Specifically, the error between the virtual waveform and the actual waveform can be reduced as compared with the case where only the conventional linear interpolation is used. This is because error components included in the virtual waveform are reduced. Further, as compared with Patent Documents 1 and 2 described above, an increase in circuit scale can be prevented. The reason is that the scale of the circuit that needs to be added when generating the virtual waveform is very small.
- FIG. 1 to 3 FIGS. 4A to 4I, FIGS. 5 and 6.
- FIG. 1 to 3 the same components are denoted by the same reference numerals, and redundant description is omitted as necessary for the sake of clarity.
- a channel estimation value interpolation circuit 10 includes an FFT / inverse FFT calculator 101, a channel estimation value buffer 102, an intermediate processing data buffer 103, a channel estimation value / delay profile.
- a conversion circuit 104 As shown in FIG. 1, a channel estimation value interpolation circuit 10 according to the present embodiment includes an FFT / inverse FFT calculator 101, a channel estimation value buffer 102, an intermediate processing data buffer 103, a channel estimation value / delay profile.
- the FFT / inverse FFT calculator 101 performs an FFT calculation or an inverse FFT calculation on the data output from the channel estimation value / delay profile conversion circuit 104.
- the channel estimation value buffer 102 stores the channel estimation value input from the preceding channel estimation circuit (not shown).
- the intermediate processing data buffer 103 stores the channel estimation value or delay profile at the intermediate processing stage obtained as the result of the FFT operation or the inverse FFT operation in the FFT / inverse FFT operation unit 101.
- the channel estimation value / delay profile conversion circuit 104 generally reads the channel estimation value stored in the channel estimation value buffer 102 and the channel estimation value and delay profile at the intermediate processing stage stored in the intermediate processing data buffer 103.
- a process, a process for processing the read channel estimation value and the delay profile, and a process for controlling the FFT / inverse FFT calculator 101 to mutually convert the channel estimation value and the delay profile are performed.
- FIG. 2 FIG. 3, and FIGS. 4A to 4I.
- the channel estimation value interpolation circuit 10 performs the processes (1) to (9) shown in FIG. Hereinafter, these processes (1) to (9) will be described in order.
- the channel estimation value buffer 102 stores the channel estimation value 401 input from the preceding channel estimation circuit.
- channel estimation values 401 are discretely arranged (at regular intervals in the example of FIG. 3) on subcarriers within a predetermined bandwidth. Is estimated from the reference signal. In addition, channel estimation values corresponding to subcarriers outside the bandwidth among all subcarriers cannot be obtained directly. In the user data equalization process, it is necessary to obtain a channel estimation value corresponding to the subcarrier on which the user data signal is arranged by an interpolation process on the channel estimation value 401.
- the FFT interpolation method as an algorithm of this interpolation processing, it is necessary to first generate a virtual waveform of a channel estimation value corresponding to a subcarrier outside the bandwidth.
- the interval between subcarriers between reference signals is defined as m, and the number of all subcarriers is defined as “n ⁇ m”.
- the channel estimation value / delay profile conversion circuit 104 estimates “n ⁇ k” channel estimation values 402 corresponding to virtual reference signals existing outside the bandwidth. Specifically, as shown in FIG. 4A, the channel estimation value / delay profile conversion circuit 104 includes reference signals arranged at both left and right ends of the bandwidth in the channel estimation value 401 read from the channel estimation value buffer 102. The channel estimation values corresponding to are linearly interpolated, and the right ends of all subcarriers are joined to the left end.
- the channel estimation value / delay profile conversion circuit 104 merges the k channel estimation values 401 and the “n ⁇ k” channel estimation values 402 to obtain an FFT / inverse FFT calculator as n channel estimation values. 101, and the inverse FFT operation is performed.
- a delay profile 501 composed of n data components is obtained.
- This delay profile 501 is temporarily stored in the intermediate processing data buffer 103.
- the channel estimation value / delay profile conversion circuit 104 replaces the data component corresponding to the high delay portion in the delay profile 501 read from the intermediate processing data buffer 103 with “0”, thereby causing the delay profile shown in FIG. 4C. 501r is obtained.
- the data component corresponding to the high delay portion is a data component delayed by a predetermined threshold time 600 or more.
- the threshold time 600 is preferably set according to delay spread characteristics (that is, the actual situation of multipath propagation) in a wireless communication system to which the channel estimation value interpolation circuit 10 is applied.
- the error component generated in the high delay portion due to the linear interpolation outside the bandwidth is removed (in other words, the error component included in the virtual waveform of the channel estimation value outside the bandwidth is reduced).
- the channel estimation value / delay profile conversion circuit 104 inputs the post-replacement delay profile 501r obtained in the above process (3) to the FFT / inverse FFT calculator 101, and performs the FFT calculation.
- n channel estimation values 403 in which error components outside the bandwidth are reduced are obtained.
- This channel estimation value 403 is temporarily stored in the intermediate processing data buffer 103.
- the channel estimation value / delay profile conversion circuit 104 uses the “n ⁇ k” number of channels corresponding to subcarriers outside the bandwidth from the channel estimation value 403 read from the intermediate processing data buffer 103. Channel estimation value 403o is extracted.
- the channel estimation value interpolation circuit 10 can accurately generate a virtual waveform of the channel estimation value outside the bandwidth with a simple configuration.
- the channel estimation value / delay profile conversion circuit 104 includes k channel estimation values 401 read from the channel estimation value buffer 102 and “n ⁇ k” read from the intermediate processing data buffer 103.
- the “number of channel estimation values 403o (virtual waveform of channel estimation values outside the bandwidth) are merged to obtain n channel estimation values 404.
- the channel estimation value / delay profile conversion circuit 104 inputs the merged channel estimation value 404 obtained in the above process (5) to the FFT / inverse FFT calculator 101, and performs inverse FFT calculation. Make it.
- a delay profile 502 composed of n data components is obtained.
- This delay profile 502 is temporarily stored in the intermediate processing data buffer 103.
- the channel estimation value / delay profile conversion circuit 104 adds “n ⁇ m ⁇ n” pieces of data to the end (high delay side) of the delay profile 502 read from the intermediate processing data buffer 103. By adding “0”, “n ⁇ m” delay profiles 503 are obtained.
- the channel estimation value / delay profile conversion circuit 104 inputs the delay profile 503 obtained in the above process (8) to the FFT / inverse FFT calculator 101, and performs the FFT calculation.
- the channel estimation value 405 is a value obtained for a point obtained by dividing the subcarrier position corresponding to the original channel estimation values 401 and 402 by m (that is, all subcarriers), and the input channel estimation value 401 is interpolated. Will be.
- the channel estimation value 405 is given to an equalization processing circuit (not shown) in the subsequent stage.
- the channel estimation value interpolation circuit 10 can also perform the FFT interpolation without changing the configuration.
- the error component included in the virtual waveform of the channel estimation value outside the bandwidth can be further reduced. This is because the error component that is latent in the low delay portion in the delay profile is pushed out to the high delay portion, and the error component pushed out to the high delay portion is removed.
- the channel estimation value / delay profile conversion circuit 104 includes a selector 201, a linear interpolation calculator 202, and a control circuit 203 that controls the selector 201 and the linear interpolation calculator 202. .
- the selector 201 according to the selection signal from the control circuit 203, the channel estimation value (401) transferred from the channel estimation value buffer 102, the intermediate processing data (channel estimation value 403, In addition, any one of the delay profiles 501 and 502), the output data of the linear interpolation calculator 202 (channel estimation value 402), or “0” is dynamically selected, and the converted data (channel estimation value) is selected.
- 401 and 402 are merged, channel estimation values 401 and 403o are merged, channel estimate 404, and delay profiles 501r and 503).
- the linear interpolation computing unit 202 performs linear interpolation on the channel estimation value 401 in accordance with the control signal from the control circuit 203, thereby estimating the channel estimation value 402 corresponding to the subcarrier outside the bandwidth.
- the linear interpolation calculator 202 includes registers 301 and 302, a weighting coefficient ROM (Read Only Memory) 303, a subtractor 304, complex multipliers 305 and 306, And an adder 307.
- the register 301 stores the channel estimation value corresponding to the reference signal arranged on one end side of the bandwidth in the channel estimation value 401.
- the register 302 stores a channel estimation value corresponding to a reference signal arranged on the other end side of the bandwidth.
- the weighting coefficient ROM 303 stores a plurality of weighting coefficients, and any one of the weighting coefficients is output according to the control signal.
- the subtractor 304 subtracts the weighting coefficient output from the weighting coefficient ROM 303 from “1”.
- the output value of the subtractor 304 is “0.8”.
- the complex multiplier 305 performs complex multiplication of the channel estimation value stored in the register 301 and the weighting coefficient.
- the complex multiplier 306 performs complex multiplication on the channel estimation value stored in the register 302 and the output value (1-weighting coefficient) of the subtractor 304.
- the complex adder 307 adds the calculation result of the complex multiplier 305 and the calculation result of the complex multiplier 306, and outputs a channel estimated value 402 that has been linearly interpolated. In this way, by changing the weighting coefficient using the control signal, “n ⁇ k” linear interpolation results are output.
- k channel estimation values 401 within the bandwidth are output as they are as converted data via the selector 201, and thus the FFT / inverse FFT computing unit 101.
- the linear interpolation calculator 202 supplies “n ⁇ k” channel estimation values 402 outside the bandwidth obtained by the linear interpolation to the FFT / inverse FFT calculator 101 via the selector 201.
- the delay profile 501 stored in the intermediate processing buffer 103 is input as intermediate processing data.
- the data component corresponding to the low delay part in the delay profile 501 is output as it is via the selector 201.
- the control circuit 203 when the data component corresponding to the high delay portion is input (in the case where the delay profile 501 is input in order from the data component corresponding to the earliest time, as shown in FIG.
- the control circuit 203 When the threshold time 600 elapses), the control circuit 203 generates a selection signal and causes the selector 201 to output “0”.
- the delay profile 501r in which the data component corresponding to the high delay portion is replaced with “0” is given to the FFT / inverse FFT calculator 101.
- the channel estimation value 403 stored in the intermediate processing buffer 103 and the channel estimation value 401 stored in the channel estimation value buffer 102 are input in parallel.
- the control circuit 203 generates a selection signal, thereby switching between a state where the selector 201 selects the channel estimation value 403 and a state where the channel estimation value 401 is selected.
- the n channel estimation values 404 obtained by merging the “n ⁇ k” channel estimation values 403 o outside the bandwidth and the k channel estimation values 401 within the bandwidth are converted into the FFT / inverse FFT calculator 101. Will be given.
- the delay profile 502 stored in the intermediate processing buffer 104 is input as intermediate processing data and output as it is through the selector 201.
- the control circuit 203 generates a selection signal, thereby causing the selector 201 to output “n ⁇ m ⁇ n” “0” s.
- the delay profile 503 in which “0” is added to the high delay side is given to the FFT / inverse FFT calculator 101.
- the present invention is applied to interpolation of channel estimation values, and in particular, to the use of generating a virtual waveform of channel estimation values outside the bandwidth when interpolating channel estimation values in the OFDM scheme.
- a wireless communication device such as a cellular phone can be cited.
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Abstract
Description
まず、チャネル推定値バッファ102には、前段のチャネル推定回路から入力されたチャネル推定値401が格納される。
次に、チャネル推定値/遅延プロファイル変換回路104は、k個のチャネル推定値401と"n-k"個のチャネル推定値402をマージし、n個のチャネル推定値としてFFT/逆FFT演算器101に入力し、以て逆FFT演算を行わせる。
次に、チャネル推定値/遅延プロファイル変換回路104は、中間処理データバッファ103から読み出した遅延プロファイル501中の高遅延部に相当するデータ成分を"0"に置き換え、以て図4Cに示す遅延プロファイル501rを得る。ここで、高遅延部に相当するデータ成分とは、所定の閾値時間600以上遅延したデータ成分のことである。また、閾値時間600は、チャネル推定値補間回路10を適用する無線通信システムにおける遅延スプレッド特性(すなわち、マルチパス伝搬の実況)に応じて設定すると好適である。
次に、チャネル推定値/遅延プロファイル変換回路104は、上記の処理(3)で得た置換後の遅延プロファイル501rを、FFT/逆FFT演算器101に入力し、以てFFT演算を行わせる。
次に、図4Eに示すように、チャネル推定値/遅延プロファイル変換回路104は、中間処理データバッファ103から読み出したチャネル推定値403から、帯域幅外のサブキャリアに対応する"n-k"個のチャネル推定値403oを抽出する。
次に、図4Fに示すように、チャネル推定値/遅延プロファイル変換回路104は、チャネル推定値バッファ102から読み出したk個のチャネル推定値401と、中間処理データバッファ103から読み出した"n-k"個のチャネル推定値403o(帯域幅外のチャネル推定値の仮想波形)とをマージし、以てn個のチャネル推定値404を得る。
次に、チャネル推定値/遅延プロファイル変換回路104は、上記の処理(5)で得たマージ後のチャネル推定値404を、FFT/逆FFT演算器101に入力し、以て逆FFT演算を行わせる。
次に、図4Hに示すように、チャネル推定値/遅延プロファイル変換回路104は、中間処理データバッファ103から読み出した遅延プロファイル502の末尾(高遅延側)に、"n×m - n"個の"0"を追加し、以て"n×m"個の遅延プロファイル503を得る。
次に、チャネル推定値/遅延プロファイル変換回路104は、上記の処理(8)で得た遅延プロファイル503を、FFT/逆FFT演算器101に入力し、以てFFT演算を行わせる。
101 FFT/逆FFT演算器
102 チャネル推定値バッファ
103 中間処理データバッファ
104 チャネル推定値/遅延プロファイル変換回路
201 セレクタ
202 直線補間演算器
203 制御回路
301, 302 レジスタ
303 重み付け係数ROM
304 減算器
305, 306 複素乗算器
307 複素加算器
401, 402, 403, 403o, 404, 405 チャネル推定値
501, 501r, 502, 503 遅延プロファイル
Claims (8)
- FFT(Fast Fourier Transform)演算と逆FFT演算とを択一的に行う演算器と、
所定の帯域幅内のサブキャリアに離散的に配置されるリファレンス信号から推定された、第1のチャネル推定値を格納する第1のバッファと、
前記演算器で得られた演算結果を格納する第2のバッファと、
前記演算器、並びに前記第1及び第2のバッファに接続された変換回路と、を備え、
前記変換回路が、
(A)前記第1のバッファに格納された前記第1のチャネル推定値の内の、前記帯域幅の両端側に配置されたリファレンス信号に対応するチャネル推定値同士間を直線補間して、前記帯域幅外のサブキャリアに対応する第2のチャネル推定値を推定する処理と、
(B)前記演算器に、前記第1のチャネル推定値と前記第2のチャネル推定値とをマージしたチャネル推定値に対する逆FFT演算を行わせると共に、当該逆FFT演算により得られた第1の遅延プロファイルを前記第2のバッファへ格納させる処理と、
(C)前記第2のバッファに格納された前記第1の遅延プロファイル中の所定の閾値時間以上遅延したデータ成分を0に置換する処理と、
(D)前記演算器に、前記置換により得た遅延プロファイルに対するFFT演算を行わせると共に、当該FFT演算により得られた第3のチャネル推定値を前記第2のバッファへ格納させる処理と、
(E)前記第2のバッファに格納された前記第3のチャネル推定値から、前記帯域外のサブキャリアに対応するチャネル推定値を抽出する処理と、
を行う、チャネル推定値補間回路。 - 請求項1において、
前記変換回路が、
(F)前記第1のバッファに格納された前記第1のチャネル推定値と、前記抽出したチャネル推定値とをマージする処理と、
(G)前記演算器に、前記マージにより得た第4のチャネル推定値に対する逆FFT演算を行わせると共に、当該逆FFT演算により得られた第2の遅延プロファイルを前記第2のバッファへ格納させる処理と、
(H)前記第2のバッファに格納された前記第2の遅延プロファイルの末尾に、全サブキャリア数から前記第4のチャネル推定値の数を減算して得た数分の0を追加して、第3の遅延プロファイルを生成する処理と、
(I)前記演算器に、前記第3の遅延プロファイルに対するFFT演算を行わせる処理と、
をさらに行う、チャネル推定値補間回路。 - 請求項1又は2において、
前記変換回路が、前記抽出したチャネル推定値を前記第2のチャネル推定値として扱いながら、前記(B)~(E)の処理を繰り返し行う、チャネル推定値補間回路。 - 請求項1~3のいずれか一項において、
前記閾値時間が、自回路を適用する無線通信システムにおける遅延スプレッド特性に応じて設定される、チャネル推定値補間回路。 - (A)予め記憶され、且つ所定の帯域幅内のサブキャリアに離散的に配置されるリファレンス信号から推定された第1のチャネル推定値の内の、前記帯域幅の両端側に配置されたリファレンス信号に対応するチャネル推定値同士間を直線補間して、前記帯域幅外のサブキャリアに対応する第2のチャネル推定値を推定し、
(B)前記第1のチャネル推定値と前記第2のチャネル推定値とをマージしたチャネル推定値に対する逆FFT演算を行って、第1の遅延プロファイルを生成し、
(C)前記第1の遅延プロファイル中の所定の閾値時間以上遅延したデータ成分を0に置換し、
(D)前記置換により得た遅延プロファイルに対するFFT演算を行って、第3のチャネル推定値を生成し、
(E)前記第3のチャネル推定値から、前記帯域外のサブキャリアに対応するチャネル推定値を抽出する、
ことを含むチャネル推定値補間方法。 - 請求項5において、
(F)前記第1のチャネル推定値と前記抽出したチャネル推定値とをマージして、第4のチャネル推定値を生成し、
(G)前記第4のチャネル推定値に対する逆FFT演算を行って、第2の遅延プロファイルを生成し、
(H)前記第2の遅延プロファイルの末尾に、全サブキャリア数から前記第4のチャネル推定値の数を減算して得た数分の0を追加して、第3の遅延プロファイルを生成し、
(I)前記第3の遅延プロファイルに対するFFT演算を行う、
ことをさらに含むチャネル推定値補間方法。 - 請求項5又は6において、
前記抽出したチャネル推定値を前記第2のチャネル推定値として扱いながら、前記(B)~(E)を繰り返し行うことを含むチャネル推定値補間方法。 - 請求項5~7のいずれか一項において、
前記閾値時間を、無線通信システムにおける遅延スプレッド特性に応じて設定することを含むチャネル推定値補間方法。
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CN201080062983.1A CN102742192B (zh) | 2010-02-01 | 2010-12-07 | 信道估计内插电路和方法 |
US13/522,859 US8817901B2 (en) | 2010-02-01 | 2010-12-07 | Channel estimate interpolation circuit and method |
JP2011551602A JP5601330B2 (ja) | 2010-02-01 | 2010-12-07 | チャネル推定値補間回路及び方法 |
EP10844551.1A EP2533441B1 (en) | 2010-02-01 | 2010-12-07 | Channel estimate interpolation circuit and channel estimate interpolation method |
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JP2007077608A (ja) | 2005-09-12 | 2007-03-29 | Takenaka Komuten Co Ltd | ルーバ |
JP2008167088A (ja) | 2006-12-27 | 2008-07-17 | Matsushita Electric Ind Co Ltd | Ofdm受信装置 |
WO2009028589A1 (ja) * | 2007-08-28 | 2009-03-05 | Sharp Kabushiki Kaisha | 通信装置 |
JP2010020638A (ja) | 2008-07-11 | 2010-01-28 | Canon Inc | 言語処理装置および言語処理方法 |
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JP4284813B2 (ja) * | 2000-02-18 | 2009-06-24 | 株式会社デンソー | Ofdm用受信装置 |
WO2007077608A1 (ja) | 2005-12-28 | 2007-07-12 | Fujitsu Limited | 通信装置及びチャネル推定方法 |
JP4832261B2 (ja) * | 2006-11-15 | 2011-12-07 | 富士通株式会社 | チャネル推定装置 |
DE102007023881A1 (de) * | 2007-03-26 | 2008-10-02 | Rohde & Schwarz Gmbh & Co. Kg | Verfahren und Vorrichtung zur Ermittlung einer unverkürzten Kanalimpulsantwort in einem OFDM-Übertragungssystem |
US8275057B2 (en) * | 2008-12-19 | 2012-09-25 | Intel Corporation | Methods and systems to estimate channel frequency response in multi-carrier signals |
US20120328055A1 (en) * | 2010-03-05 | 2012-12-27 | Ntt Docomo, Inc. | Channel estimation circuit, channel estimation method, and receiver |
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JP2007077608A (ja) | 2005-09-12 | 2007-03-29 | Takenaka Komuten Co Ltd | ルーバ |
JP2008167088A (ja) | 2006-12-27 | 2008-07-17 | Matsushita Electric Ind Co Ltd | Ofdm受信装置 |
WO2009028589A1 (ja) * | 2007-08-28 | 2009-03-05 | Sharp Kabushiki Kaisha | 通信装置 |
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See also references of EP2533441A4 |
TAKASHI DATEKI ET AL.: "OFDM Channel Estimation by Adding a Virtual Channel Frequency Response", PROCEEDINGS OF THE IEICE GENERAL CONFERENCE, THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, 8 March 2006 (2006-03-08), pages 447, XP008167760 * |
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EP2533441A1 (en) | 2012-12-12 |
EP2533441B1 (en) | 2019-03-20 |
CN102742192A (zh) | 2012-10-17 |
JP5601330B2 (ja) | 2014-10-08 |
US8817901B2 (en) | 2014-08-26 |
US20120300865A1 (en) | 2012-11-29 |
EP2533441A4 (en) | 2014-10-15 |
JPWO2011092783A1 (ja) | 2013-05-30 |
CN102742192B (zh) | 2015-08-19 |
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