WO2011069370A1 - 高Ge组分沟道材料层的形成方法 - Google Patents

高Ge组分沟道材料层的形成方法 Download PDF

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WO2011069370A1
WO2011069370A1 PCT/CN2010/075375 CN2010075375W WO2011069370A1 WO 2011069370 A1 WO2011069370 A1 WO 2011069370A1 CN 2010075375 W CN2010075375 W CN 2010075375W WO 2011069370 A1 WO2011069370 A1 WO 2011069370A1
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composition
layer
channel material
material layer
sige
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French (fr)
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王敬
许军
郭磊
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清华大学
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Priority to US13/063,649 priority Critical patent/US20110212600A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66651—Lateral single gate silicon transistors with a single crystalline channel formed on the silicon substrate after insulating device isolation

Definitions

  • the present invention relates to the field of semiconductor fabrication and design, and more particularly to a method for preparing a high Ge composition channel material layer by a low temperature decompression chemical vapor deposition (RPCVD) process in combination with a selective epitaxial process.
  • RPCVD low temperature decompression chemical vapor deposition
  • silicon has been developed as a dominant semiconductor material for several decades, during which time it has shown good performance.
  • Si has been developed as a dominant semiconductor material for several decades, during which time it has shown good performance.
  • the size of a single transistor gradually reaches the physical and technical limits. Therefore, the mobility of CMOS devices using silicon as a channel material becomes lower and lower, and the device performance cannot be satisfied. Ascending requirements.
  • the prior art introduces a strain technique to increase the mobility of the silicon material, or directly replaces Si as a channel material of the device by using other materials with higher mobility, wherein the Ge material is relatively high.
  • the hole carrier mobility has been widely concerned.
  • SiGe materials have been found to have much higher hole mobility than existing Si materials, they are very suitable for the fabrication of PMOS devices in future CMOS processes.
  • CMOS processes since the existing Si process and equipment are very mature, considering the requirements of cost and compatibility, it is also necessary to use a Si wafer as a carrier to prepare a Ge layer or a high Ge group only at the surface of the Si wafer by various processes.
  • the SiGe layer is used as a channel material layer of the device, thereby realizing high mobility transport of carriers therein, improving device performance.
  • One current method is to directly epitaxially high Ge component materials globally on the original Si wafer, mainly using the following processes and methods to reduce the surface punching dislocation density, thereby reducing the surface defect density: for example, The process of epitaxial Ge composition graded SiGe layer may be used to obtain high Ge composition material; or the process of concentrating low Ge composition SiGe layer by thermal oxidation may be used to improve Ge composition; or rapid thermal annealing and secondary The method of growth, etc.
  • the advantage of these methods is the global extension of the whole piece, which facilitates the preparation of MOS devices in subsequent processes, and is compatible with traditional process flows, but these techniques are in terms of surface roughness, epitaxial layer thickness, process complexity and surface defect density. They all have their own shortcomings. And due to the limitations of the global heteroepitaxial process itself, the prepared material dislocation density is still relatively high, which is not suitable for the preparation of future nano-sized CMOS devices.
  • Another method currently uses a selective epitaxial process to deposit a dielectric layer on a Si wafer, and a deeper and wider epitaxial hole is formed on the dielectric layer by photolithography and etching, at the bottom of the epitaxial hole.
  • the Si material is exposed, and then the crystal material of the high Ge composition is epitaxially formed by a process such as ultra high vacuum epitaxy (UHVCVD).
  • UHVCVD ultra high vacuum epitaxy
  • the selective epitaxial process utilizes vertical sidewalls in the epitaxial holes to block the continued extension of dislocations so that they do not extend to the surface, and most of the dislocation defects can be filtered out by blocking the sidewalls of a certain height to obtain surface defects.
  • a low density, high Ge composition channel material layer allows MOS devices to be fabricated in these regions where high quality high Ge component materials are grown.
  • the gas such as HC1 can be simultaneously introduced to block the nucleation of the Ge material by these gases, thereby ensuring the crystal of the high Ge composition material.
  • the growth mainly occurs in the region of the exposed Si substrate in the epitaxial hole, so that the desired channel material can be obtained in a predetermined region.
  • this method generates a large number of dislocations extending vertically upwards, and the side walls on both sides cannot block these vertical upwardly extending dislocations. Therefore, the surface roughness and dislocation of the high Ge component channel material layer formed by this method are formed. Defect density and the like are not yet up to the requirements. Summary of the invention
  • the present invention will selectively epitaxial process and low temperature decompression chemical gas
  • the phase deposition (RPCVD) process is combined to produce a high Ge composition channel material layer having a low surface roughness, a thin epitaxial layer thickness, and a low defect density, such as a SiGe layer or a Ge layer of a high Ge composition.
  • the high Ge composition channel material layer prepared by the present invention can be applied to the preparation of a semiconductor device.
  • Step (1) selecting a raw Si wafer as a substrate or selecting a Si wafer having a low Ge composition SiGe layer as a substrate, and cleaning, in the low Ge composition SiGe material, Ge group
  • the fraction is not more than about 30%.
  • Step (2) using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) on the substrate according to the required size and aspect ratio of the high Ge composition channel material region hole
  • LPCVD low pressure chemical vapor deposition
  • PECVD plasma enhanced chemical vapor deposition
  • Step (3) defining and etching a set size epitaxial hole along the different crystal orientations on the SiO 2 dielectric layer by using a photolithography and dry etching process, wherein the epitaxial hole has an aspect ratio at least greater than 1 . Cleaning the exposed single crystal substrate in the epitaxial hole.
  • Step (4) exposing in the epitaxial hole by a low temperature decompression chemical vapor deposition (RPCVD) process at an epitaxial temperature of 350 ° C to 550 ° C, preferably at an epitaxial temperature of 450 ° C to 550 ° C
  • the high Ge composition channel material layer is selectively epitaxially grown on the single crystal substrate.
  • the high Ge composition channel material layer may be a layer such as a pure Ge layer or a high Ge composition SiGe layer.
  • the high Ge composition channel material layer may also be two layers, such as epitaxially epitaxially relaxing a high Ge composition SiGe layer, and then epitaxially straining a higher Ge content. SiGe layer or strained Ge layer.
  • FIG. 1 is a transmission electron microscope (TEM) image of a high Ge composition SiGe layer Si/SiGe interface epitaxially grown at 500 ° C in a low temperature RPCVD process according to an embodiment of the present invention
  • AFM atomic force microscope
  • Figure 4 is a schematic view of the first embodiment of the present invention.
  • FIG. 5 is a schematic diagram of Embodiment 2 of the present invention.
  • Figure 6 is a schematic view of Embodiment 3 of the present invention.
  • Figure 7 is a schematic view of Embodiment 4 of the present invention.
  • FIG. 8 is a schematic view of Embodiment 5 of the present invention.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention are described in detail below, and the examples of the embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals indicate the same or similar elements or elements having the same or similar functions.
  • the embodiments described below with reference to the drawings are intended to be illustrative of the invention and are not to be construed as limiting.
  • the components and arrangements of the specific examples are described below. Of course, they are merely examples and are not intended to limit the invention.
  • the present invention may repeat reference numerals and/or letters in different examples.
  • first and second features are formed in direct contact
  • additional features formed in the first and second features. In other embodiments, such first and second features may not be in direct contact.
  • the present invention has been studied for many years by low temperature reduced pressure chemical vapor deposition (RPCVD) for the preparation of high Ge composition SiGe single crystal thin films, and found that when the epitaxial temperature is between 350 ° C and 550 ° C, preferably at 450 ° C - 550
  • RPCVD low temperature reduced pressure chemical vapor deposition
  • the epitaxial temperature is between 350 ° C and 550 ° C, preferably at 450 ° C - 550
  • a SiGe film is epitaxially grown between °C and a gas source of Ge3 ⁇ 4 and Si3 ⁇ 4 gas
  • most of the dislocations caused by the mismatch are generated in a thin region at the Si/SiGe interface, and are about 60.
  • the degree extends obliquely upward in the SiGe toward the surface, and the number of dislocations extending vertically upward is very small, as shown in Fig.
  • the embodiment of the present invention can be combined with the selective epitaxial process to prevent the diagonal dislocations generated by the lattice mismatch from continuing to extend upward to the surface, and the low temperature RPCVD process is combined with the selection.
  • the epitaxial process filters out most of the upwardly extending dislocation surface punching dislocations. Therefore, the present invention can prevent most of the defects from extending upward by using a side wall of a smaller thickness, further reducing the thickness of the required side wall and the epitaxial layer, and since the number of dislocations extending vertically upward is small, the relative The dislocation density can be further reduced by other epitaxial processes.
  • the surface roughness of the epitaxial SiGe layer can be effectively reduced by low temperature RPCVD epitaxy.
  • the low temperature RPCVD process 500 for the embodiment of the present invention is used.
  • the materials prepared in the examples can be directly applied to device fabrication, so the chemical mechanical polishing (CMP) process steps can be omitted.
  • CMP chemical mechanical polishing
  • a high-quality, high-Ge-component channel material layer with a lower dislocation density, a smaller epitaxial layer thickness, and a low surface roughness, such as a Ge layer or a high Ge-component SiGe layer, can be applied to future high-performance MOS devices. Preparation.
  • FIG. 3 it is a flow chart of a method for forming a high Ge composition channel material layer according to an embodiment of the present invention.
  • the embodiment uses a low temperature decompression chemical vapor deposition combined with selective epitaxy to form a high Ge composition.
  • a channel material layer such as a Ge layer or a high Ge composition SiGe layer, the method comprising the steps of:
  • a substrate is provided and the substrate is cleaned.
  • the original Si wafer may be used as the substrate, or a low Ge composition SiGe layer may be epitaxially grown on the Si substrate as a substrate, for example, a SiGe layer having a Ge content of 30% or less.
  • Step b preparing a dielectric layer of a desired thickness on the substrate.
  • the thickness of the SiO 2 dielectric layer may be determined according to the required size of the epitaxial holes for selectively epitaxial SiGe or Ge, and the aspect ratio of the epitaxial holes is generally required to be at least 1. Depending on the requirements, the thickness may vary from tens of nm to several um.
  • different preparation methods such as thermal oxidation, chemical vapor deposition (LPCVD or PECVD), and sputtering may be selected.
  • step c an epitaxial hole of a desired size is formed on the dielectric layer.
  • a photolithography, dry etching process a high aspect ratio epitaxial hole of a desired size is defined along the different crystal orientations on the Si0 2 dielectric layer, and the substrate is exposed and cleaned at the bottom of the epitaxial hole.
  • Step d selectively elongating the desired material layer in the epitaxial hole.
  • selective epitaxy is performed in the epitaxial hole by low temperature decompression chemical vapor deposition (RPCVD), and the epitaxial temperature thereof may be about 350 ° C - 550 ° C, preferably 450 ° C - 550 ° C.
  • RPCVD low temperature decompression chemical vapor deposition
  • a high quality high Ge composition channel material layer is selectively epitaxially grown on the substrate exposed in the epitaxial hole.
  • the high Ge composition channel material layer may be a layer such as a pure Ge layer or a high Ge composition SiGe layer.
  • the high Ge composition channel material layer may also be two layers, such as epitaxially epitaxially relaxing a high Ge composition SiGe layer, and then epitaxy of a higher content strained SiGe.
  • a layer or a strained Ge layer for example, a high Ge composition SiGe layer in which an epitaxial Ge component is relaxed above 50%, and a strained SiGe layer or a strained Ge layer having a higher Ge content is epitaxially grown.
  • the embodiment of the present invention can obtain a high-quality high-Ge component channel material layer having a dislocation defect density of less than 10 6 cm - 2 , a surface roughness of less than 1 nm, and a relatively thin epitaxial layer, such as Ge.
  • a layer or high Ge composition SiGe layer can be applied to the fabrication of MOS devices in future CMOS processes.
  • a Si substrate 110 is provided, and then a desired thickness is prepared on the Si substrate 110 by a low pressure chemical vapor deposition (LPCVD) process according to the required high Ge composition channel material layer size (for example)
  • the SiO 2 dielectric layer 120 is defined by a photolithography and etching process on the SiO 2 dielectric layer 120 along the ⁇ 100> crystal orientation of the Si substrate 110 to define a desired size (for example, a side length of about 500 nm).
  • the hole, the thus obtained epitaxial hole has an aspect ratio of 2, to ensure that the sidewall of the epitaxial hole (Si0 2 dielectric layer 120) can filter out most of the dislocation lines.
  • the Ge or high Ge composition SiGe material is then epitaxially grown at 500 °C using an RPCVD apparatus to form a high Ge composition channel material layer 130.
  • Ge3 ⁇ 4 (flow rate about 400 sccm) and Si3 ⁇ 4 (flow rate about 0.05 slm) may be used as a gas source, and hydrogen chloride having a flow rate of about 0.1 lsm is introduced.
  • (HC1) gas reduces the nucleation probability and growth rate of SiGe on the SiO 2 dielectric layer 120, so that SiGe epitaxy occurs at the interface between the hole and the Si substrate 110 to ensure the two-dimensional growth of SiGe, thereby obtaining the desired A high Ge composition SiGe layer with low dislocation density and low surface roughness.
  • the obtained SiGe layer has a Ge composition content of about 87%, a dislocation density of less than about 10 6 cm - 2 , and a surface roughness of about 1 nm or less, which is suitable for MOS in a CMOS process.
  • Device preparation Its structure is as shown in FIG.
  • this embodiment although the formation of a high Ge composition SiGe layer is taken as an example, this embodiment can also be used to generate a Ge layer by selecting a gas source.
  • a Si substrate 210 is provided, and then a desired thickness (e.g., about lum) is prepared on the Si substrate 210 by a low pressure chemical vapor deposition (LPCVD) process according to the required high Ge composition channel material layer size.
  • LPCVD low pressure chemical vapor deposition
  • si0 2 dielectric layer 220, 210 ⁇ 100> defining a desired size (e.g. length of about 500 nm side) by photolithography and epitaxial holes in the Si substrate in an etching process on si0 2 dielectric layer 220, thus obtained
  • the epitaxial hole has an aspect ratio of 2 to ensure that the sidewall of the epitaxial hole (Si0 2 dielectric layer 220) can filter out most of the dislocation lines.
  • the Ge or high Ge composition SiGe material is then epitaxially grown at 550 ° C using an RPCVD apparatus to form a high Ge composition channel material layer 230.
  • Ge3 ⁇ 4 flow rate about 200 sccm
  • Si3 ⁇ 4 flow rate about 0.05 slm
  • hydrogen chloride having a flow rate of about 0.1 lsm is introduced ( HC1) gas reduces the nucleation probability and growth rate on the SiO 2 dielectric layer 220, so that SiGe epitaxy occurs at the interface between the epitaxial hole and the Si substrate 210 to ensure the two-dimensional growth of SiGe, thereby obtaining the desired High Ge composition SiGe layer with low dislocation density and low surface roughness.
  • the content of the Ge component in the obtained high Ge composition SiGe layer is about It is 53%, its dislocation density is less than about 10 6 cm - 2 , and its surface roughness is about 1 nm or less. It is suitable for MOS device fabrication in CMOS process. Its structure is as shown in FIG. Third embodiment
  • a Si substrate 310 is provided, and then a desired thickness (e.g., about lum) is prepared on the Si substrate 310 by a low pressure chemical vapor deposition (LPCVD) process according to the required size of the high Ge composition channel material layer.
  • LPCVD low pressure chemical vapor deposition
  • si0 2 dielectric layer 320, the Si substrate 310 ⁇ 110> crystal direction is defined by a photolithography and etching process in a desired size on dielectric si0 2 layer 320 (side of about 500 nm) epitaxial holes, thus obtained
  • the aspect ratio of the epitaxial hole is 2 to ensure that the sidewall of the epitaxial hole (Si0 2 dielectric layer 320) can filter out most of the dislocation lines.
  • the pure Ge or high Ge composition SiGe material is then epitaxially grown at 450 ° C using an RPCVD apparatus to form a high Ge composition channel material layer 330.
  • a SiGe layer forming a high Ge composition is exemplified, and Ge3 ⁇ 4 (flow rate about 450 sccm) and Si3 ⁇ 4 (flow rate about 0.05 slm) can be used as a gas source, and hydrogen chloride having a flow rate of about 0.1 lsm is introduced ( The HC1) gas reduces the nucleation probability and growth rate of SiGe on the Si0 2 dielectric layer 320, so that SiGe epitaxy occurs at the interface between the epitaxial hole and the Si substrate 310 to ensure the two-dimensional growth of SiGe, thereby obtaining the desired A high Ge composition SiGe layer with low dislocation density and low surface roughness.
  • the high Ge composition SiGe layer obtained in this embodiment has a Ge component content of about 92%, a dislocation density of less than about 10 6 cm - 2 , and a surface roughness of about 1 nm or less, which is suitable for a CMOS process.
  • a Si wafer 410 is provided, and then a low Ge composition SiGe layer 420 is epitaxially grown on the wafer 410 as a substrate, for example, a SiGe layer 420 having Ge less than 30% can be epitaxially grown.
  • a layer of Si0 2 dielectric layer of a desired thickness (about lum) is then formed on the low Ge composition SiGe layer 420 by a low pressure chemical vapor deposition (LPCVD) process according to the desired high Ge composition channel material layer size.
  • LPCVD low pressure chemical vapor deposition
  • an epitaxial hole of a desired size (about 500 nm in side length) is defined along the ⁇ 100> crystal orientation of the low Ge composition SiGe layer 420 on the SiO 2 dielectric layer 430 by photolithography and etching processes, thus obtaining
  • the epitaxial hole has an aspect ratio of 2 to ensure that the sidewall of the epitaxial hole can filter out most of the dislocation lines.
  • the Ge or high Ge composition SiGe material is then epitaxially grown at 500 °C using an RPCVD apparatus to form a high Ge composition channel material layer 440.
  • GeH 4 flow rate about 400 sccm
  • Si3 ⁇ 4 flow rate about 0.05 slm
  • a hydrogen chloride (HC1) gas having a flow rate of about 0.1 molm is introduced to lower the Si0 2 .
  • the nucleation probability and growth rate on the dielectric layer 430 cause SiGe epitaxy to occur at the interface between the epitaxial via and the low Ge composition SiGe layer 420 to ensure the two-dimensional growth of SiGe, thereby obtaining the desired low dislocation density and low.
  • the high Ge composition SiGe layer obtained in this embodiment has a Ge component content of about 87%, a dislocation density of less than about 10 6 cm 2 , and a surface roughness of about 1 nm or less, which is suitable for a CMOS process.
  • a Si wafer 510 is provided, and then a SiGe layer 520 of a low Ge composition is epitaxially grown on the Si wafer 510 as a substrate, for example, a SiGe layer 520 having Ge less than 30% can be epitaxially grown.
  • a layer of Si0 2 dielectric layer of a desired thickness (about lum) is then formed on the low Ge composition SiGe layer 520 by a low pressure chemical vapor deposition (LPCVD) process according to the desired high Ge composition channel material layer size.
  • LPCVD low pressure chemical vapor deposition
  • an epitaxial hole of a desired size (about 500 nm in side length) is defined along the ⁇ 110> crystal orientation of the SiGe layer 520 of the low Ge composition on the SiO 2 dielectric layer 530.
  • the obtained epitaxial hole has an aspect ratio of 2 to ensure that the sidewall of the epitaxial hole can filter out most of the dislocation lines.
  • a Ge or high Ge composition SiGe material is then epitaxially grown at 450 ° C using an RPCVD apparatus to form a high Ge composition channel material layer 540.
  • Ge3 ⁇ 4 (flow rate about 450 sccm) and Si3 ⁇ 4 (flow rate about 0.05 slm) may be used as a gas source, and a hydrogen chloride (HC1) gas having a flow rate of 0.1 mol% is introduced to reduce SiGe in the Si0 2 medium.
  • HC1 hydrogen chloride
  • the nucleation probability and growth rate on layer 530 cause Ge or SiGe epitaxy to occur in the epitaxial hole and at the interface with the low Ge composition SiGe layer 520 to ensure the two-dimensional growth of SiGe, thereby obtaining the desired low dislocation.
  • the high Ge composition SiGe layer obtained in this embodiment has a Ge component content of 92%, a dislocation density of less than 10 6 cm" 2 , and a surface roughness of 1 nm or less, which is suitable for a MOS device in a CMOS process.
  • the structure is as shown in Fig. 8.
  • Sixth embodiment Unlike the above embodiment, in this embodiment, after the epitaxial holes are formed, a Ge or a high Ge composition SiGe material is epitaxially grown at 350 ° C by an RPCVD apparatus, thereby forming a channel material layer of a high Ge composition.
  • a pure Ge layer or a high Ge composition SiGe layer is formed as an example
  • a RAPCVD epitaxial layer of high Ge may be used first.
  • the SiGe layer is further coated with a higher content strained SiGe layer or strained Ge layer by RPCVD.
  • an RPCVD epitaxial multilayered SiGe layer having a different Ge composition may be used, and then an RPCVD epitaxial multilayer strained SiGe layer or a strained Ge layer may be used.

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Description

高 Ge组分沟道材料层的形成方法 技术领 '域
本发明涉及半导体制造及设计技术领域，特别是涉及一种釆用低温减压化 学气相淀积（RPCVD )工艺结合选择性外延工艺制备高 Ge组分沟道材料层的 方法。 背景技术
在半导体产业中， 硅（Si )作为占据统治地位的半导体材料已经发展了几 十年， 在此期间其表现出了良好的性能。 然而， 随着器件特征尺寸的不断缩小 使得单个晶体管的尺寸逐渐达到物理和技术的双重极限， 因此以硅作为沟道材 料的 CMOS 器件的迁移率变得越来越低， 已经无法满足器件性能不断提升的 要求。 为了解决这种问题， 现有技术引入了应变技术来提高硅材料的迁移率， 或者直接釆用其它的迁移率更高的材料来代替 Si作为器件的沟道材料， 其中 由于 Ge材料具有比较高的空穴载流子迁移率而得到广关注。 由于 Ge材料或 高 Ge组分的 SiGe材料在研究中都呈现出了远远高于现有 Si材料的空穴迁移 率， 因此非常适合于应用于在未来 CMOS工艺中制备 PMOS器件。 但是由于 现有 Si工艺及设备非常成熟， 考虑成本与兼容性的要求， 因此还需要以 Si圓 片作为载体釆用各种工艺方法仅在 Si圓片的表面处制备出 Ge层或高 Ge组分 SiGe层作为器件的沟道材料层，从而在其中实现载流子的高迁移率输运，提高 器件的性能。
但是， 由于 Ge材料的晶格常数与 Si不同， 存在 4.2%晶格失配， 因此如 果直接在 Si衬底上外延 Ge层或高 Ge组分的 SiGe层则会产生大量的位错，这 些位错将会穿通到表面从而形成缺陷， 会极大地恶化制备出的 MOS器件的性 能。 因此这种技术还无法应用于半导体 MOS器件的制造中。 目前也提出了一 些新的工艺与技术， 以在 Si衬底上制备出一层低表面穿通位错密度的高 Ge组 分的沟道材料层， 使其可以应用于器件的制备。
目前的一种方法是在原始的 Si 圓片上整片全局地直接外延高 Ge组分材 料， 主要釆用以下几种工艺和方法来降低表面穿通位错密度， 从而减小表面缺 陷密度： 例如， 可釆用外延 Ge组分渐变的 SiGe层的工艺以得到高 Ge组分材 料； 或者釆用热氧化浓缩低 Ge组分 SiGe层的工艺以提高 Ge组分； 或者釆用 快速热退火及二次生长的方法等。 这些方法的优点是整片全局外延， 便于在后 续工艺中 MOS器件的制备， 且其与传统工艺流程兼容， 但是这些技术在表面 粗糙度，外延层厚度，工艺复杂性与表面缺陷密度等参数方面都有各自的缺点。 并且由于全局异质外延工艺本身的局限性， 制备出的材料表面穿通位错密度仍 旧比较高， 不适于未来纳米尺寸的 CMOS器件的制备。
目前的另一种方法是釆用选择性外延工艺， 在 Si圓片上淀积一层介质层， 利用光刻和刻蚀工艺在介质层上形成深宽比较高的外延孔，在外延孔的底部露 出 Si材料， 然后通过超高真空外延（UHVCVD )等工艺手段外延高 Ge组分的 晶体材料。该选择性外延工艺利用外延孔中垂直的侧墙阻挡住了位错的继续延 伸， 使其不能延伸到表面， 通过一定高度的侧墙阻挡就能滤去大部分的位错缺 陷， 得到表面缺陷密度较低的高 Ge组分沟道材料层， 从而可以在这些生长有 高质量高 Ge组分材料的区域中制备 MOS器件。 在其它的被绝缘介质覆盖的 区域， 由于高 Ge材料晶体成核困难， 可同时引入 HC1等气体通过这些气体对 Ge材料等的刻蚀作用阻挡其成核， 因此可以保证高 Ge组分材料晶体生长主要 发生在外延孔中棵露的 Si衬底的区域， 从而可在预定的区域得到所需要的沟 道材料。 但是这种方法会产生大量垂直向上延伸的位错， 而两侧的侧墙无法阻 挡这些垂直向上延伸的位错， 因此这种方法形成的高 Ge组分沟道材料层表面 粗糙度及位错缺陷密度等还不能达到要求。 发明内容
为了解决上述技术缺陷之一， 本发明将选择性外延工艺和低温减压化学气 相淀积 （RPCVD ) 工艺结合起来， 从而能够制备出表面粗糙度低、 外延层厚 度薄、 缺陷密度低的高 Ge组分沟道材料层， 例如高 Ge组分的 SiGe层或 Ge 层。 通过本发明制备出的高 Ge组分沟道材料层可应用于半导体器件的制备。
步骤（ 1 ) , 选择原始 Si圓片作为衬底或选择已外延了低 Ge组分 SiGe层 的 Si圓片作为衬底， 并清洗， 在所述的低 Ge组分 SiGe材料中， Ge的组分不 大于约 30%。
步骤（2 ), 根据所需要的高 Ge组分沟道材料区域孔的尺寸大小及深宽比 用低压化学气相淀积 （LPCVD )或等离子增强化学气相淀积 （PECVD )在所 述衬底上制备一层所需厚度的 Si02介质层， 在所述的高 Ge组分沟道材料中， Ge的组分为约 50%-100%, 所述 Si02介质层的厚度在几十纳米（ nm )—几个 微米（um )之间选取。
步骤（3 ),利用光刻和干法刻蚀工艺在所述的 Si02介质层上沿不同的晶向 定义并刻蚀出设定尺寸的外延孔， 所述外延孔的深宽比至少大于 1 , 并对所述 外延孔中棵露出的单晶衬底进行清洗。
步骤（4 ), 釆用低温减压化学气相淀积 （RPCVD )工艺在 350°C— 550°C 外延温度下，优选在 450°C— 550°C外延温度下在所述外延孔中棵露出的单晶衬 底上选择性外延出所述的高 Ge组分的沟道材料层。在本发明的一个实施例中， 该高 Ge组分沟道材料层可以为一层， 比如纯 Ge层或高 Ge组分 SiGe层。 在 本发明的另一个实施例中， 该高 Ge组分沟道材料层也可以为两层， 比如先外 延一层弛豫的高 Ge组分 SiGe层， 再外延一层 Ge含量更高的应变 SiGe层或 者应变 Ge层。
通过本发明实施例， 可以制备出位错缺陷密度低于 106cm-2, 表面粗糙度 lnm 以下， 且外延层厚度比较薄的高质量的高 Ge组分沟道材料层， 例如 Ge 层或高 Ge组分 SiGe层， 可应用于未来 CMOS工艺中的 MOS器件的制备。 附闺说明 图 1是根据本发明实施例釆用低温 RPCVD工艺 500°C下外延出的高 Ge 组分 SiGe层 Si/SiGe界面处的透射电子显微镜 ( TEM ) 图像；
图 2是根据本发明实施例釆用低温 RPCVD工艺 500°C下外延出的高 Ge 组分 SiGe层表面的原子力显微镜（AFM ) 图像；
SiGe材料的主要工艺流程图；
图 4是本发明实施例一的示意图；
图 5是本发明实施例二的示意图；
图 6是本发明实施例三的示意图；
图 7是本发明实施例四的示意图；
图 8是本发明实施例五的示意图。 具体实 i¾方式 下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其中自 始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元 件。 下面通过参考附图描述的实施例是示例性的， 仅用于解释本发明， 而不能 解释为对本发明的限制。 为了简化本发明的公开， 下文中对特定例子的部件和设置进行描述。 当然， 它 们仅仅为示例， 并且目的不在于限制本发明。 此外， 本发明可以在不同例子中 重复参考数字和 /或字母。这种重复是为了简化和清楚的目的，其本身不指示所 讨论各种实施例和 /或设置之间的关系。此外，本发明提供了的各种特定的工艺 和材料的例子，但是本领域普通技术人员可以意识到其他工艺的可应用于性和 /或其他材料的使用。 另外， 以下描述的第一特征在第二特征之 "上，，的结构可以 包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在 第一和第二特征之间的实施例， 这样第一和第二特征可能不是直接接触。
本发明通过对低温减压化学气相淀积 （RPCVD )制备高 Ge组分 SiGe单 晶薄膜的多年研究，发现当外延温度在 350°C-550°C之间，优选地，在 450 °C -550 °C之间， 且以 Ge¾和 Si¾气体为外延生长的气体源外延 SiGe薄膜时， 由失 配引起的位错绝大部分都产生在 Si/SiGe界面处很薄的区域内，且呈约 60度在 SiGe中斜向上往表面处延伸， 垂直向上延伸的位错数量非常少， 如图 1所示， 为本发明实施例的 Si/SiGe界面处的透射电子显微镜（TEM ) 图像， 从该图像 上可以看出， 位错呈 60度斜向上向表面处延伸， 垂直方向上的位错基本没有。
因此根据本发明发现的这种特性， 本发明实施例可以结合选择性外延工艺 利用侧墙阻挡住晶格失配产生的斜向位错继续向上延伸到表面的特点， 釆用低 温 RPCVD工艺结合选择性外延工艺过滤掉大部分向上延伸的位错表面穿通位 错。 从而本发明釆用较小厚度的侧墙就可阻挡住大部分的缺陷向上延伸， 进一 步减小了所需侧墙及外延层的厚度， 且由于垂直向上延伸的位错数量很少， 因 此相对于其他外延工艺可进一步降低位错密度。
并且， 作为本发明实施例的附加的优点， 釆用低温 RPCVD外延还可以有 效地降低外延出的 SiGe层的表面粗糙度， 如图 2所示， 为本发明实施例的釆 用低温 RPCVD工艺 500 °C下外延出的高 Ge组分 SiGe层表面的原子力显微镜 ( AFM ) 图像， 其外延层厚度 400nm, 表面粗糙度 RMS=0.389nm。 因此， 这
明实施例制备出的材料能够直接应用于器件制备， 因此可以省略掉化学机械抛 光（CMP )工艺步骤。
备出位错密度更低， 外延层厚度更小且表面粗糙度很低的高质量高 Ge组分沟 道材料层， 例如 Ge层或高 Ge组分 SiGe层， 可以应用于未来高性能 MOS器 件的制备。
如图 3所示， 为本发明实施例的高 Ge组分沟道材料层的形成方法流程图， 该实施例釆用低温减压化学气相淀积结合选择性外延的方式形成高 Ge组分的 沟道材料层， 例如 Ge层或高 Ge组分 SiGe层， 该方法包括以下步骤：
步骤 a, 提供衬底， 并对衬底进行清洗。 在本方法中既可以釆用原始 Si片 作为衬底， 也可以先在 Si衬底上外延一层低 Ge组分 SiGe层后作为衬底， 例 如 Ge含量 30%以下的 SiGe层。 步骤 b ,在衬底上制备符合要求厚度的介质层。在本发明的一个实施例中， 可根据所需要的用来选择性外延 SiGe或 Ge的外延孔的尺寸大小来确定 Si02 介质层的厚度， 一般要求外延孔的深宽比至少在 1以上。 根据不同的要求厚度 可能从几十 nm…几个 um, 根据不同的 Si02介质厚度要求， 可以选择不同的 制备方法， 如热氧化， 化学气相淀积 （ LPCVD或 PECVD ) 以及溅射等。
步骤 c, 在介质层上制作出所需要尺寸的外延孔。 利用光刻， 干法刻蚀工 艺在 Si02介质层上沿不同的晶向定义出所需尺寸的高深宽比的外延孔，以及在 外延孔的底部将衬底暴露， 并对其进行清洗。
步骤 d, 在外延孔中选择性外延所需的材料层。 在本发明实施例中釆用低 温减压化学气相淀积 （RPCVD )在外延孔中进行选择性外延， 其外延温度可 为约 350°C— 550°C , 优选为 450°C-550°C之间， 从而在外延孔中暴露出的衬底 上选择性外延出高质量的高 Ge组分沟道材料层。在本发明的一个实施例中， 该 高 Ge组分沟道材料层可以为一层， 比如纯 Ge层或高 Ge组分 SiGe层。 在本发明 的另一个实施例中， 该高 Ge组分沟道材料层也可以是两层， 比如先外延一层弛 豫的高 Ge组分 SiGe层， 再外延一层含量更高的应变 SiGe层或应变 Ge层， 例如 先外延 Ge组分在 50%以上弛豫的高 Ge组分 SiGe层， 再外延一层 Ge含量更高的 应变 SiGe层或者应变 Ge层。
通过以上步骤， 本发明实施例可以得到位错缺陷密度低于 106cm-2, 表面 粗糙度在 lnm以下， 且外延层厚度比较薄的高质量的高 Ge组分沟道材料层， 例如 Ge层或高 Ge组分 SiGe层， 可应用于未来 CMOS工艺中的 MOS器件的 制备。
为了能更清楚的理解本发明， 以下就以具体的实施例进行描述， 需要说明 的是以下仅是本发明的优选实施方式， 应当指出， 对于本技术领域的普通技术 人员来说， 在不脱离本发明技术原理的前提下， 还可以做出若干改进和替换， 这些改进和替换也应在本发明的保护范围之内。 第一实施例
首先提供 Si衬底 110, 然后根据所需要的高 Ge组分沟道材料层的大小通 过低压化学气相淀积（LPCVD )工艺在 Si衬底 110上制备一层所需厚度 (例如 约 lum)的 Si02介质层 120, 通过光刻以及刻蚀工艺在 Si02介质层 120上沿 Si 衬底 110的<100>晶向定义出所需尺寸 (例如边长约为 500nm)的外延孔，这样得 到的外延孔的深宽比为 2, 以保证外延孔的侧墙（Si02介质层 120 ) 能够滤掉 大部分的位错线。然后利用 RPCVD设备在 500 °C下外延 Ge或高 Ge组分 SiGe 材料， 从而形成高 Ge组分的沟道材料层 130。
在本发明的一个实施例中，以形成高 Ge组分 SiGe为例，可以以 Ge¾ (流 量约 400sccm )和 Si¾ (流量约 0.05slm )作为气源， 同时通入流量约为 O.lOslm 的氯化氢（HC1 ) 气体以降低 SiGe在 Si02介质层 120上的成核几率及生长速 度，使 SiGe外延都发生在孔内与 Si衬底 110的界面上以保证 SiGe的二维生长， 从而得到所需的低位错密度和低表面粗糙度的高 Ge组分 SiGe层。
其中， 在该实施例中， 得到的 SiGe层的 Ge组分含量约为 87%, 其位错密 度低于约 106cm-2, 表面粗糙度约在 lnm以下， 适用于 CMOS工艺中的 MOS 器件制备。 其结构如附图 4所示。 在该实施例中， 虽然以高 Ge组分 SiGe层的 生成为例， 但是该实施例也可通过选择气源用来生成 Ge层。 第二实施例
首先提供 Si衬底 210, 然后根据所需要的高 Ge组分沟道材料层的大小通 过低压化学气相淀积（ LPCVD )工艺在 Si衬底 210上制备一层所需厚度 (例如 约 lum)的 Si02介质层 220, 通过光刻以及刻蚀工艺在 Si02介质层 220上沿 Si 衬底 210 的<100>晶向定义出所需尺寸 (例如边长为约 500nm)的外延孔， 这样 得到的外延孔的深宽比为 2 , 以保证外延孔的侧墙（Si02介质层 220 ) 能够滤 掉大部分的位错线。然后利用 RPCVD设备在 550°C下外延 Ge或高 Ge组分 SiGe 材料， 从而形成高 Ge组分的沟道材料层 230。 在该实施例中， 以形成高 Ge组 分的 SiGe层为例， 可以以 Ge¾ (流量约 200sccm )和 Si¾ (流量约 0.05slm ) 作为气源， 同时通入流量约为 O.lOslm的氯化氢（HC1 ) 气体以降低在 Si02介 质层 220上的成核几率及生长速度， 使 SiGe外延都发生在外延孔内与 Si衬底 210的界面上以保证 SiGe的二维生长，从而得到所需的低位错密度和低表面粗 糙度的高 Ge组分 SiGe层。 其中， 得到的高 Ge组分 SiGe层中 Ge组分含量约 为 53%,其位错密度低于约 106cm-2,表面粗糙度约在 lnm以下，适用于 CMOS 工艺中的 MOS器件制备。 其结构如附图 5所示。 第三实施例
首先提供 Si衬底 310, 然后根据所需要的高 Ge组分沟道材料层的大小通 过低压化学气相淀积（ LPCVD )工艺在 Si衬底 310上制备一层所需厚度 (例如 约 lum)的 Si02介质层 320, 通过光刻以及刻蚀工艺在 Si02介质层 320上沿 Si 衬底 310的<110>晶向定义出所需尺寸 (边长约为 500nm)的外延孔，这样得到的 外延孔的深宽比为 2 , 以保证外延孔的侧墙（Si02介质层 320 ) 能够滤掉大部 分的位错线。 然后利用 RPCVD设备在 450°C下外延纯 Ge或高 Ge组分 SiGe 材料， 从而形成高 Ge组分的沟道材料层 330。 在该实施例中， 以形成高 Ge组 分的 SiGe层为例， 可以以 Ge¾ (流量约 450sccm )和 Si¾ (流量约 0.05slm ) 作为气源，同时通入流量约为 O.lOslm的氯化氢（HC1 )气体以降低 SiGe在 Si02 介质层 320上的成核几率及生长速度， 使 SiGe外延都发生在外延孔内与 Si衬 底 310的界面上以保证 SiGe的二维生长， 从而得到所需的低位错密度和低表 面粗糙度的高 Ge组分 SiGe层。 其中， 在该实施例中得到的高 Ge组分 SiGe 层中 Ge组分含量约为 92%, 其位错密度低于约 106cm-2, 表面粗糙度约在 lnm 以下， 适用于 CMOS工艺中的 MOS器件制备。 其结构如附图 6所示。 第四实施例
首先提供 Si圓片 410, 之后在圓片 410上外延一层低 Ge组分的 SiGe层 420作为衬底， 例如可外延含 Ge小于 30 %的 SiGe层 420。 然后根据所需要的 高 Ge组分沟道材料层的大小通过低压化学气相淀积（LPCVD )工艺在低 Ge 组分的 SiGe层 420上制备一层所需厚度 (约 lum)的 Si02介质层 430,接着通过 光刻以及刻蚀工艺在 Si02介质层 430上沿低 Ge组分 SiGe层 420的<100>晶向 定义出所需尺寸 (边长约为 500nm)的外延孔， 这样， 得到的外延孔的深宽比为 2, 以保证外延孔的侧墙能够滤掉大部分的位错线。 然后利用 RPCVD设备在 500 °C下外延 Ge或高 Ge组分 SiGe材料，从而形成高 Ge组分的沟道材料层 440。 在本发明的一个实施例中， 可以以 GeH4 (流量约 400sccm )和 Si¾ (流量约 0.05slm )作为气源， 同时通入流量约为 O.lOslm的氯化氢（ HC1 ) 气体以降低 在 Si02介质层 430上的成核几率及生长速度， 使 SiGe外延都发生在外延孔内 与低 Ge组分 SiGe层 420的界面上以保证 SiGe的二维生长， 从而得到所需的 低位错密度和低表面粗糙度的高 Ge组分 SiGe层。 其中， 在该实施例中得到的 高 Ge组分 SiGe层中 Ge组分含量约为 87%,其位错密度低于约 106cm-2,表面 粗糙度约在 lnm以下，适用于 CMOS工艺中的 MOS器件制备。其结构如附图 7所示。 第五实施例
首先提供 Si圓片 510, 接着在 Si圓片 510上外延一层低 Ge组分的 SiGe 层 520作为衬底， 例如可外延含 Ge小于 30 %的 SiGe层 520。 然后根据所需要 的高 Ge 组分沟道材料层的大小通过低压化学气相淀积 （LPCVD ) 工艺在低 Ge组分的 SiGe层 520上制备一层所需厚度 (约 lum)的 Si02介质层 530, 接着 通过光刻以及刻蚀工艺在 Si02介质层 530上沿低 Ge组分的 SiGe层 520的 <110>晶向定义出所需尺寸 (边长约为 500nm)的外延孔，这样，得到的外延孔的 深宽比为 2, 以保证外延孔的侧墙能够滤掉大部分的位错线。然后利用 RPCVD 设备在 450°C下外延 Ge或高 Ge组分 SiGe材料，从而形成高 Ge组分的沟道材 料层 540。 在本发明的一个实施例中， 可以以 Ge¾ (流量约 450sccm )和 Si¾ (流量约 0.05slm )作为气源， 同时通入流量为 O.lOslm的氯化氢（ HC1 ) 气体 以降低 SiGe在 Si02介质层 530上的成核几率及生长速度， 使 Ge或 SiGe外延 都发生在外延孔内且与低 Ge组分的 SiGe层 520的界面上以保证 SiGe的二维 生长，从而得到所需的低位错密度和低表面粗糙度的高 Ge组分 SiGe层。其中， 在该实施例中得到的高 Ge组分 SiGe层中 Ge组分含量 92%, 其位错密度低于 106cm"2, 表面粗糙度在 lnm以下， 适用于 CMOS工艺中的 MOS器件制备。 其结构如附图 8所示。 第六实施例 与上述实施例不同的是，在该实施例中在形成了外延孔之后，利用 RPCVD 设备在 350°C下外延 Ge或高 Ge组分 SiGe材料，从而形成高 Ge组分的沟道材 料层。 虽然在上述实施例中， 以形成一层纯 Ge层或高 Ge组分 SiGe层为例进行 描述， 但是在本发明的其他实施例中， 还可先釆用 RPCVD外延一层弛豫的高 Ge组分 SiGe层， 再釆用 RPCVD外延一层含量更高的应变 SiGe层或者应变 Ge层。 或者也可以先釆用 RPCVD外延多层弛豫的 Ge组分不同的 SiGe层， 再釆用 RPCVD外延多层应变 SiGe层或应变 Ge层。这些结构都在本发明的权 利保护范围之内。
尽管已经示出和描述了本发明的实施例， 对于本领域的普通技术人员而 言， 可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多 种变化、 修改、 替换和变型， 本发明的范围由所附权利要求及其等同限定。

Claims

权利要求书
1、 一种高 Ge组分沟道材料层的形成方法， 其特征在于， 包括以下步骤： 提供衬底；
在所述衬底上形成介质层；
高 Ge组分沟道材料层的外延孔； 和
釆用低温减压化学气相淀积 RPCVD在所述外延孔中形成高 Ge组分沟道 材料层。
2、 如权利要求 1所述的高 Ge组分沟道材料层的形成方法， 其特征在于， 所述高 Ge组分沟道材料层包括 Ge层或高 Ge组分的 SiGe层。
3、 如权利要求 2所述的高 Ge组分沟道材料层的形成方法， 其特征在于， 所述高 Ge组分的 SiGe层中 Ge含量大于 50 %。
4、 如权利要求 1所述的高 Ge组分沟道材料层的形成方法， 其特征在于， 所述釆用 RPCVD在外延孔中形成高 Ge组分沟道材料层进一步包括：
釆用 RPCVD在外延孔中形成弛豫的高 Ge组分 SiGe层； 和
釆用 RPCVD在所述弛豫的高 Ge组分 SiGe层之上形成一层 Ge含量更高 的应变 SiGe层或者应变 Ge层。
5、 如权利要求 2所述的高 Ge组分沟道材料层的形成方法， 其特征在于， 所述低温减压化学气相淀积 RPCVD的温度约为 350°C— 550°C。
6、 如权利要求 5所述的高 Ge组分沟道材料层的形成方法， 其特征在于， 所述低温减压化学气相淀积 RPCVD以硅烷 Si¾和锗烷 Ge¾作为气源。
7、 如权利要求 6所述的高 Ge组分沟道材料层的形成方法， 其特征在于， 在外延时， 还包括：
通入氯化氢 HC1气体以降低 Ge或 SiGe在所述介质层上的成核率及生长速率。
8、 如权利要求 2所述的高 Ge组分沟道材料层的形成方法， 其特征在于， 所述衬底包括 Si衬底或在 Si上生长的低 Ge组分的 SiGe层。
9、 如权利要求 1所述的高 Ge组分沟道材料层的形成方法， 其特征在于， 所述外延孔的深宽比至少大于 1。
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