CN101916770B - 具有双缓变结的Si-Ge-Si半导体结构及其形成方法 - Google Patents

具有双缓变结的Si-Ge-Si半导体结构及其形成方法 Download PDF

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CN101916770B
CN101916770B CN201010230174.9A CN201010230174A CN101916770B CN 101916770 B CN101916770 B CN 101916770B CN 201010230174 A CN201010230174 A CN 201010230174A CN 101916770 B CN101916770 B CN 101916770B
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CN101916770A (zh
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王敬
许军
郭磊
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Tsinghua University
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Abstract

本发明提出一种具有双缓变结的Si-Ge-Si半导体结构，包括：衬底；形成在所述衬底之上的过渡层或绝缘层；形成在所述过渡层或绝缘层之上的应变SiGe层，其中，所述应变SiGe层中心部分的Ge组分最高，上下两个表面处的Ge组分最低，所述中心部分至所述上下两个表面的Ge组分呈渐变分布。本发明使用缓变结来代替突变结，从而形成三角形的空穴势阱，这样不仅能够使空穴载流子大部分分布于高Ge材料层中，还能够降低界面散射引起的载流子迁移率下降的问题，进一步改善器件性能。

Description

具有双缓变结的Si-Ge-Si半导体结构及其形成方法
技术领域
本发明涉及半导体制造及设计技术领域，特别涉及一种具有双缓变结的Si-Ge-Si半导体结构及其形成方法。
背景技术
目前，随着场效应晶体管特征尺寸的不断缩小，其工作速度也越来越快，但是目前的特征尺寸已接近了极限，因此想通过继续缩小特征尺寸来提高速度则将会变得越来越困难和难以实现。
因此，以Si作为沟道材料的CMOS器件的迁移率变得越来越低，已经无法满足器件性能不断提升的要求。为了解决这种问题，现有技术引入了应变技术来提高硅材料的迁移率，或者直接采用其它的迁移率更高的材料来代替Si作为器件的沟道材料，其中由于Ge材料具有比较高的空穴载流子迁移率而得到广关注。Ge材料或高Ge组分的SiGe材料在研究中都呈现出了远远高于现有Si材料的空穴迁移率，因此非常适合于应用于在未来CMOS工艺中制备PMOS器件。
但是Ge沟道材料的传统场效应晶体管也面临着自身的问题：如窄禁带导致的BTBT带间漏电，沟道与栅绝缘层介质间难以得到良好界面，漏源注入激活率过低，注入掺杂在高温下极易扩散导致结深过深等一系列问题。
因此，现有技术提出了Si-Ge-Si结构来克服上述缺陷，如图1所示，为现有技术中Si-Ge-Si结构的示意图，在衬底110之上形成有过渡层120，在所述过渡层120之上依次形成有第一应变Si层130、应变Ge层140和第二应变Si层150。Si-Ge-Si结构不仅能够很好的抑制BTBT漏电，通过上层的薄膜Si层还可有效改善Ge材料与栅极材料的界面状态，另外，Si-Ge-Si结构还可形成空穴势阱，这样大部分空穴载流子可分布在中间的Ge材料层中，从而进一步提高载流子的迁移率，改善器件性能。
现有技术存在的缺点是，在现有的Si-Ge-Si结构存在着Si-Ge和Ge-Si两个突变界面，由于材料的突变会在两种材料之间产生界面态，从而对载流子的输运形成散射，最终会降低载流子的迁移率。
发明内容
本发明的目的旨在至少解决上述技术缺陷，特别是解决现有技术中由于两个突变界面之间的界面态导致的载流子迁移率降低的缺陷。
为达到上述目的，本发明一方面提出一种具有双缓变结的Si-Ge-Si半导体结构，包括：衬底；形成在所述衬底之上的过渡层或绝缘层；形成在所述过渡层或绝缘层之上的应变SiGe层，其中，所述应变SiGe层中心部分的Ge组分最高，上下两个表面处的Ge组分最低，所述中心部分至所述上下两个表面的Ge组分呈渐变分布。
本发明另一方面还提出了一种具有双缓变结的Si-Ge-Si半导体结构的形成方法，包括以下步骤：提供衬底；在所述衬底之上形成过渡层或绝缘层；采用低温CVD并控制掺杂气体中Ge组分以在所述过渡层或绝缘层之上形成应变SiGe层，其中，所述应变SiGe层中心部分的Ge组分最高，上下两个表面处的Ge组分最低，所述中心部分至所述上下两个表面的Ge组分呈渐变分布。
在本发明实施例中，可通过流量和/或温度来控制Ge组分的分布。本发明使用缓变结来代替突变结，从而形成三角形的空穴势阱，这样不仅能够使空穴载流子大部分分布于高Ge材料层中，还能够降低界面散射引起的载流子迁移率下降的问题，进一步改善器件性能。
本发明附加的方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。
附图说明
本发明上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1为现有技术中Si-Ge-Si结构的示意图；
图2为本发明实施例一的具有双缓变结的Si-Ge-Si半导体结构示意图；
图3为本发明实施例二的具有双缓变结的Si-Ge-Si半导体结构示意图；
图4为本发明实施例的具有双缓变结的Si-Ge-Si半导体结构的形成方法中中间状态示意图。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。
下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的可应用于性和/或其他材料的使用。另外，以下描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
本发明主要在于，使用缓变结来代替突变结，从而形成三角形的空穴势阱，本发明提出了具有双缓变结的Si-Ge-Si半导体结构，但是本领域技术人员应当理解，还可对这种具有双缓变结的Si-Ge-Si半导体结构进行扩展或者变换，这些扩展或变换均应包含在本发明的保护范围之内。
如图2所示，为本发明实施例一的具有双缓变结的Si-Ge-Si半导体结构示意图，该半导体结构包括衬底210，形成在衬底210之上的过渡层或绝缘层220，以及形成在过渡层或绝缘层220之上的应变SiGe层230，其中，应变SiGe层230中心部分的Ge组分最高，上下两个表面处的Ge组分最低，且中心部分至上下两个表面的Ge组分呈渐变分布。
在本发明的一个实施例中，该衬底210可为任何半导体衬底材料，包括但不限于硅、锗、锗化硅、碳化硅、砷化镓或者任何III/V族化合物半导体等衬底。
在本发明的一个实施例中，过渡层可为驰豫SiGe虚拟衬底，绝缘层可包括SiO2等绝缘材料。在本发明实施例中，如果选择绝缘层，则在形成应变SiGe层230之前，可采用智能剥离(smart cut)技术在绝缘层之上先形成一层应变Si层。
如图3所示，为本发明实施例二的具有双缓变结的Si-Ge-Si半导体结构示意图。该实施例的半导体结构还包括形成在应变SiGe层230之上的栅堆叠结构240，以及形成在应变SiGe层230之中及栅堆叠结构240两侧的源漏极250。在本发明的一个实施例中，栅堆叠240可包括栅介质层和栅极，优选地，可包括高k栅介质层和金属栅极，当然其他氮化物或氧化物介质层或多晶硅栅极也可应用在本发明中，因此也应包含在本发明的保护范围之内。在其他实施例中，栅堆叠240还可包含其他材料层以改善栅极的某些其他特性，可以看出本发明对栅堆叠的结构并没有限制，可采用任何类型的栅结构。在另一个实施例中，在栅堆叠240的两侧还可包括一层或多层侧墙。
在本发明的上述实施例一和二中，可采用低温CVD形成应变SiGe层230，并在CVD过程中控制掺杂气体中Ge的组分以使Ge组分呈渐变分布，这样不仅能保证形成的应变SiGe层230的质量，还可减慢生长速度，因此可以精确控制Ge组分的变化或温度变化，从而本发明也可以在很薄的厚度内实现Ge组分的连续变化，最终在应变SiGe层230中形成三角形的空穴势阱。在本发明的其他实施例中，还可通过温度的变化控制Ge的组分，例如在初始阶段采用高温，降低Ge组分提高Si组分，接着逐渐降低温度以降低Si组分而提高Ge组分，在形成了中心部分之后接着逐渐提高温度，从而形成最终的应变SiGe层230。优选地，在本发明中还可以同时通过流量和温度一同达到控制Ge组分分布的目的，在此不再赘述。
为了更清楚的理解本发明实施例提出的上述半导体结构，本发明还提出了形成上述半导体结构的方法的实施例，需要注意的是，本领域技术人员能够根据上述半导体结构选择多种工艺进行制造，例如不同类型的产品线，不同的工艺流程等等，但是这些工艺制造的半导体结构如果采用与本发明上述结构基本相同的结构，达到基本相同的效果，那么也应包含在本发明的保护范围之内。为了能够更清楚的理解本发明，以下将具体描述形成本发明上述结构的方法及工艺，还需要说明的是，以下步骤仅是示意性的，并不是对本发明的限制，本领域技术人员还可通过其他工艺实现。
如图4所示，为本发明实施例的具有双缓变结的Si-Ge-Si半导体结构的形成方法中中间状态示意图。该方法包括以下步骤：
步骤S101，提供衬底210。
步骤S102，在衬底210之上形成过渡层或绝缘层220，如图4所示。在本发明的一个实施例中，过渡层可为驰豫SiGe虚拟衬底，绝缘层可包括SiO2等绝缘材料。
步骤S103，采用低温CVD并控制掺杂气体中Ge组分和/或温度以在过渡层或绝缘层220之上形成应变SiGe层230，如图2所示，其中，应变SiGe层230中心部分的Ge组分最高，上下两个表面处的Ge组分最低，中心部分至上下两个表面的Ge组分呈渐变分布。
在本发明的一个实施例中，可以采用超高真空化学气相淀积UHVCVD形成应变SiGe层230，其中，UHVCVD的外延温度为200℃-550℃，生长过程中生长腔的气压为10-2-10-3帕之间。
在本发明的一个实施例中，可以采用低温减压化学气相淀积RPCVD形成应变SiGe层230，其中，RPCVD的外延温度为300℃-600℃，生长过程中生长腔的气压为10-100帕之间。
在本发明实施例中，采用低温CVD形成应变SiGe层230，并在CVD过程中控制掺杂气体中Ge的组分以使Ge组分呈渐变分布，这样不仅能保证形成的应变SiGe层230的质量，还可减慢生长速度，因此可以精确控制Ge组分的变化，本发明也可以在很薄的厚度内实现Ge组分的连续变化，从而在应变SiGe层230中形成三角形的空穴势阱。在上述实施例中，CVD的气源为硅烷SiH4和锗烷GeH4的混合气体，在CVD的过程中锗烷GeH4的流量先逐步提高，接着再逐步降低，本发明逐步提高和降低锗烷GeH4的流量可以固定的步长进行调整，也可不以固定步长调整，只要能使Ge组分的连续变化，避免出现突变界面即可。
在本发明的其他实施例中，还可通过外延温度进行控制，例如对于使用RPCVD淀积的情况，在初期可采用600℃的外延温度，提高Si组分的成核几率，接着逐步地降低外延温度，例如在接近中心部分时可将外延温度降低至300℃，然后再逐步提高外延温度，这样通过温度也可以控制Ge组分的分布。在本发明的优选实施例中，可同时控制温度和流量达到精确控制Ge组分分布的目的。
步骤S104，在应变SiGe层230之上形成栅堆叠结构240。
步骤S105，在应变SiGe层230之中及栅堆叠结构240两侧形成源漏极250，如图3所示。
本发明使用缓变结来代替突变结，从而形成三角形的空穴势阱，这样不仅能够使空穴载流子大部分分布于高Ge材料层中，还能够降低界面散射引起的载流子迁移率下降的问题，进一步改善器件性能。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本发明的范围由所附权利要求及其等同限定。

Claims (12)

1.一种具有双缓变结的Si-Ge-Si半导体结构，其特征在于，包括：
衬底；
形成在所述衬底之上的过渡层或绝缘层；和
形成在所述过渡层或绝缘层之上的应变SiGe层，其中，所述应变SiGe层中心部分的Ge组分最高，上下两个表面处的Ge组分最低，所述中心部分至所述上下两个表面的Ge组分呈渐变分布。
2.如权利要求1所述的具有双缓变结的Si-Ge-Si半导体结构，其特征在于，还包括：
形成在所述应变SiGe层之上的栅堆叠结构，及形成在所述栅堆叠结构两侧的一层或多层侧墙；和
形成在所述应变SiGe层之中及所述栅堆叠结构两侧的源漏极。
3.如权利要求1或2所述的具有双缓变结的Si-Ge-Si半导体结构，其特征在于，所述应变SiGe层通过低温化学气相淀积CVD形成，在CVD过程中控制掺杂气体中Ge的组分以使所述Ge组分呈渐变分布。
4.如权利要求3所述的具有双缓变结的Si-Ge-Si半导体结构，其特征在于，其中，所述CVD为超高真空化学气相淀积UHVCVD，所述UHVCVD的外延温度为200℃-550℃，生长过程中生长腔的气压为10-2-10-3帕之间。
5.如权利要求3所述的具有双缓变结的Si-Ge-Si半导体结构，其特征在于，所述CVD为低温减压化学气相淀积RPCVD，所述RPCVD的外延温度为300℃-600℃，生长过程中生长腔的气压为10-100帕之间。
6.如权利要求1所述的具有双缓变结的Si-Ge-Si半导体结构，其特征在于，在所述应变SiGe层中形成三角形的空穴势阱。
7.一种具有双缓变结的Si-Ge-Si半导体结构的形成方法，其特征在于，包括以下步骤：
提供衬底；
在所述衬底之上形成过渡层或绝缘层；和
采用低温CVD并控制掺杂气体中的Ge组分以在所述过渡层或绝缘层之上形成应变SiGe层，其中，所述应变SiGe层中心部分的Ge组分最高，上下两个表面处的Ge组分最低，且所述中心部分至所述上下两个表面的Ge组分呈渐变分布。
8.如权利要求7所述的具有双缓变结的Si-Ge-Si半导体结构的形成方法，其特征在于，还包括：
在所述应变SiGe层之上形成栅堆叠结构，并在所述栅堆叠结构的两侧形成一层或多层侧墙；和
在所述应变SiGe层之中及所述栅堆叠结构两侧形成源漏极。
9.如权利要求7或8所述的具有双缓变结的Si-Ge-Si半导体结构的形成方法，其特征在于，所述CVD为超高真空化学气相淀积UHVCVD，所述UHVCVD的外延温度为200-550℃，生长过程中生长腔的气压为10-2-10-3帕之间。
10.如权利要求7或8所述的具有双缓变结的Si-Ge-Si半导体结构的形成方法，其特征在于，所述CVD为低温减压化学气相淀积RPCVD，所述RPCVD的外延温度为300-600℃，生长过程中生长腔的气压为10-100帕之间。
11.如权利要求7所述的具有双缓变结的Si-Ge-Si半导体结构的形成方法，其特征在于，所述CVD的气源为硅烷SiH4和锗烷GeH4的混合气体，在CVD的过程中锗烷GeH4流量与硅烷SiH4流量之比先逐步提高，接着再逐步降低。
12.如权利要求10所述的具有双缓变结的Si-Ge-Si半导体结构的形成方法，其特征在于，在CVD的过程中外延温度先逐步降低，接着再逐步升高。
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