WO2011066750A1 - 全硅化金属栅电极的制备方法 - Google Patents

全硅化金属栅电极的制备方法 Download PDF

Info

Publication number
WO2011066750A1
WO2011066750A1 PCT/CN2010/074603 CN2010074603W WO2011066750A1 WO 2011066750 A1 WO2011066750 A1 WO 2011066750A1 CN 2010074603 W CN2010074603 W CN 2010074603W WO 2011066750 A1 WO2011066750 A1 WO 2011066750A1
Authority
WO
WIPO (PCT)
Prior art keywords
polysilicon
gate electrode
annealing
implantation
gate
Prior art date
Application number
PCT/CN2010/074603
Other languages
English (en)
French (fr)
Inventor
周华杰
徐秋霞
Original Assignee
中国科学院微电子研究所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 中国科学院微电子研究所 filed Critical 中国科学院微电子研究所
Priority to US12/990,042 priority Critical patent/US20110237048A1/en
Publication of WO2011066750A1 publication Critical patent/WO2011066750A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/2822—Making the insulator with substrate doping, e.g. N, Ge, C implantation, before formation of the insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28238—Making the insulator with sacrificial oxide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors

Definitions

  • the present invention relates to the field of microelectronic ultra-deep sub-micron technology complementary metal oxide semiconductor devices (CMOS) and ultra-large-scale integration technology, and more particularly to a fully-silicided metal gate for ultra-deep sub-micron technology complementary metal oxide semiconductor devices and circuits.
  • CMOS complementary metal oxide semiconductor devices
  • a method of preparing an electrode Background technique
  • the transistor's feature size will reach 7nm by 2018.
  • the continued shrinking of the size has led to an increase in the performance (speed) of the transistor, which has enabled us to integrate more devices on the same area of the chip.
  • the integrated circuit is becoming more and more powerful, while reducing the cost per unit of function.
  • CMOS complementary metal oxide semiconductor
  • Metal grids are considered to be the most promising alternative.
  • Using a metal as the gate electrode can fundamentally eliminate the polysilicon gate depletion effect and the boron (B) penetration effect of the P-type field effect transistor, while achieving a very low gate sheet resistance.
  • fully silicided metal gate technology is a relatively simple metal gate preparation method and has good compatibility with CMOS technology.
  • a one-step annealing process was generally used, that is, only one annealing was used to realize the silicidation of the entire gate electrode, so the preparation method of the annealing process was very simple.
  • the annealing process has the disadvantages of uneven silicide film formation and line width effect.
  • the method for preparing a fully silicided metal grid has the following main steps: 1) local oxidation isolation or shallow trench isolation, pre-injection oxidation, and then inject 14 N+;
  • step 1) the local oxidation temperature is 1000 ° C, the thickness of the isolation layer is 3000-5000 A, the thickness of the pre-oxidation is 100-200 A; the condition of injecting 14 N + is: the implantation energy is 10-30 Kev, The implantation dose is Ixl0 14 -6xl0 l4 cm- 2 .
  • An aqueous solution of hydrofluoric acid/isopropanol is immersed for 5 minutes at room temperature; the first etching solution is a H 2 S0 4 and 3 ⁇ 40 2 solution having a volume ratio of 5:1; the second etching solution is a volume ratio of 0.8:1.
  • step 3 a photoresist having a thickness of 1.5 ⁇ m is used as a mask for photolithography, and polysilicon is etched by reactive ions to etch the polysilicon in the field region to form a polysilicon gate electrode.
  • the impurity implanted into the P-type field effect transistor is a P-type impurity BF 2; the impurity implanted into the N-type field effect transistor is an N-type impurity As or P; for the P-type impurity BF 2 , an implantation condition
  • the injection energy is 15-30Kev, the implantation dose is Ixl0 15 -5xl0 15 cm- 2 ; for the N-type impurity As, the injection condition is: injection energy 30-60Kev, the implantation dose is lxlO 15 - 5xl0 15 cm- 2 ;
  • Type impurity P the implantation conditions are: injection energy 40-60Kev, injection dose is 1 ⁇ 10 15 -3 ⁇ 10 15 cm- 2 ; impurity activation conditions are: temperature 950-1020 ° C, time 2-20 seconds.
  • the metal nickel Ni deposited in step 5 has a thickness of 600 to 2000 ⁇ .
  • the polysilicon at the top of the polysilicon gate is controlled to react with the metallic nickel to form a nickel silicide, and a portion of the polysilicon is not reacted near the interface of the gate dielectric, and the annealing conditions are: temperature 340 to 390 . C, time 30 to 90 seconds.
  • step 7) 'I' is performed by using a first etching solution for corrosion removal, the first etching solution being 5:1 by volume H 2 S0 4 and H 2 0 2 solution, corrosion time is 20 to 30 minutes;
  • the second annealing in step 8) causes the remaining polysilicon near the interface of the gate dielectric to react with the metallic nickel to form nickel silicide, and the entire gate electrode is completely converted into nickel silicide to form a fully silicided metal gate electrode; annealing conditions It is: temperature 450 to 600 ° C, time 30 to 90 seconds.
  • the method for preparing a metal gate electrode provided by the present invention overcomes the disadvantages of uneven coating of a silicide film and a line width effect in a one-step annealing process
  • the method for preparing a metal gate electrode provided by the invention has a simple preparation method, is easy to integrate, has good compatibility with a CMOS process, and has great application value.
  • FIG. 1 is a flow chart of a method for preparing a fully silicided metal gate drain capacitor using a two-turn annealing process provided by the present invention.
  • 2(a)-(f) are process flow diagrams for preparing a fully silicided metal gate electrode capacitor using a two-step annealing process provided by the present invention.
  • Figure 3 (a), Figure 3 (b) shows the SEM image of the gate electrode when the first annealing temperature is too low;
  • Figure 3 (a) is the scanning electron micrograph of the gate electrode after the first annealing (SEM) ), wherein the annealing condition is 280 ° C, 60 seconds;
  • 3 (b) is the SEM image of the gate electrode after the second annealing, in which the annealing condition is 530 ° C for 30 seconds.
  • FIG. 4(a) and 4(b) show the SEM image of the gate electrode when the first annealing temperature is too high; wherein FIG. 4(a) is the SEM image of the gate electrode after the first annealing, wherein the annealing condition is 410. °C, 60 seconds; Figure 4 (b) is the SEM image of the gate electrode after the second annealing, in which the annealing conditions are 530 degrees, 30 seconds.
  • Figure 5 (a) Figure 5 (b) shows the SEM image of the gate electrode when the first annealing temperature is suitable; wherein Figure 5 (a) is the SEM image of the gate electrode after the first annealing, wherein the annealing condition is 360 ° C, 60S; Figure 5 (b) is the SEM image of the gate electrode after the second annealing, wherein the annealing conditions are 530 degrees, 30 seconds. detailed description
  • the present invention provides a method of preparing a fully silicided metal gate electrode for ultra deep submicron complementary metal oxide semiconductor devices and circuits by depositing metallic nickel Ni and performing two rapid thermal annealing RTAs to metal nickel Ni and The polysilicon reacts completely to form a fully silicided metal gate.
  • FIG. 1 is a flow chart of a method for preparing a fully silicided metal gate electrode capacitor by a two-step annealing process according to the present invention, the method comprising the following steps:
  • Step 101 partial oxidation isolation or shallow trench isolation, performing pre-injection oxidation, and then injecting 14 N + ; in this step, the oxidation temperature is 1000 ° C, the thickness of the isolation layer is 3000-5000 A; in the step of oxidation before injection, The oxidation thickness is 100-200 A; in the step of injecting 14 N+, the implantation conditions are: the implantation energy is 10-30 KeV, and the implantation dose is I xl 0 14 -6x l 0 14 cm- 2 .
  • Step 102 rinsing the oxide film before implantation, gate oxidation, and depositing polysilicon
  • the thickness of the gate oxide is 15 to 50 A, and the deposited polysilicon is deposited by chemical vapor deposition LPCVD, and the thickness of the deposited polysilicon is 1000 to 2000 A.
  • Step 103 photolithography and etching to form a polysilicon gate electrode
  • a photoresist having a thickness of 1.5 ⁇ m (for example, a 9918 type photoresist) is used as a mask for photolithography, and polysilicon is reactively etched to etch the polysilicon in the field region to form a polysilicon gate electrode.
  • Step 104 implanting impurities and performing impurity activation
  • the conditions for impurity activation are: temperature 950-1020 ° C, 2-20 seconds between turns, P-type field effect transistor implanted impurities are P-type impurity BF 2 , N-type field effect transistor N-type impurity As or P;
  • the implantation conditions are: the implantation energy is 15-30Kev, the implantation dose is I xl 0 15 -5 xl 0 15 cm_ 2 ;
  • the implantation condition is: the implantation energy is 30-60Kev, The implantation dose is 1 ⁇ 10 15 - 5x l 0 15 cm - 2 ;
  • the implantation conditions are: implantation energy 40-60Kev, injection dose is lx lO 15 - 3 ⁇ 10 15 cm - 2 ;
  • the activation conditions are: temperature 950-1020 ° C, time 2-20 seconds.
  • the thickness of the deposited metal nickel Ni is 600-2000 A.
  • Step 106 first annealing, reacting a part of polysilicon with metallic nickel;
  • the annealing conditions are: temperature 340-390 ° C, time 30-90 seconds;
  • Step 107 selecting to remove unreacted metallic nickel Ni
  • the first etching solution is used for the corrosion removal using a first etching solution, which is a H 2 S0 4 and H 2 0 2 solution having a volume ratio of 5:1, and the etching time is 20-30 minutes.
  • Step 108 performing a second annealing to completely convert the gate electrode into a metal nickel silicide to form a fully silicide metal gate electrode;
  • the conditions for annealing in this step are: temperature 450-600 ° C, time 30-90 seconds.
  • FIG. 2 is a flow chart showing a process for preparing a metal gate electrode capacitor by using a two-turn annealing process according to the present invention
  • (a) is a structural diagram formed by depositing polysilicon and photolithography and etching;
  • (b) being an ion Injection and annealing activation diagram;
  • (c) schematic diagram after deposition of metallic nickel Ni;
  • (d) schematic diagram of gate electrode after first annealing;
  • Step 1 Field oxidation; 1000 ° C, 3000-5000 A;
  • Step 2 Oxidation before injection; thickness 100-200 A;
  • Step 3 Inject 14 N+, the energy is 10-30Kev, and the dose is I xl0 14 -6xl0 14 cm_ 2 ;
  • Step 5 cleaning; the first etching solution is washed for 10 minutes, the second etching solution is washed for 5 minutes, and the HF/isopropyl alcohol (IPA) aqueous solution is immersed for 5 minutes at room temperature;
  • IPA isopropyl alcohol
  • Step 6 Gate oxidation; thickness 15-50 A;
  • Step 7 Chemical vapor deposition LPCVD polysilicon; 2000 A;
  • Step 8 Photolithography polysilicon; using a photoresist having a thickness of 1.5 ⁇ m (for example, a 9918 type photoresist) as a mask;
  • Step 9 reactive ion etching polysilicon; field area engraved pure polysilicon;
  • Step 10 gate implantation; implant impurity As, implant energy 10-50Kev, dose I x l0 15 -5xl0 15 cm- 2 ; step 11: impurity activation; 950-1020 ° C, time 2-20 seconds;
  • Step 12 sputtering metal nickel Ni; thickness, 1400 A;
  • Step 15 Second rapid thermal annealing RTA; temperature 530 ° C, time 30 seconds.
  • a key technique of the invention is to control the first annealing conditions. If the first annealing temperature is too high or the time is too long, the gate electrode will be completely silicided during the first annealing; if the first annealing temperature is too low, the polysilicon will not be sufficiently reacted, so that after the second annealing, The gate electrode is completely silicided, causing the polysilicon gate electrode to be not completely silicided; suitable annealing conditions are: after the first annealing, only a portion of the polysilicon remains in the vicinity of the gate dielectric is not silicided, and the gate electrode is completely silicided after the second annealing.
  • Figure 3 shows an SEM image of the gate electrode when the first annealing temperature is too low. It can be seen from Fig. 3(a) that when the first annealing temperature is too low (annealing conditions: 280 ⁇ , 60 sec), only a small portion of the polysilicon reacts with the metallic nickel to form nickel silicide at the top of the gate, and most of the polysilicon does not have Ni. Reaction; It can be seen from Fig. 3(b) that after the second annealing (annealing conditions: 53 (TC, 30 seconds), the thickness of the silicide becomes thicker, but still most of the polysilicon does not react to form silicide, resulting in no Complete silicidation.
  • annealing conditions 280 ⁇ , 60 sec
  • Figure 4 shows an SEM image of the gate electrode when the first annealing temperature is too high. It can be seen from Fig. 4 (a) that when the first annealing temperature is too high (annealing conditions: 410 ° C, 60 seconds), the first annealing causes the entire polysilicon gate electrode to be completely converted into silicide; b) It can be seen that after the second annealing (annealing conditions: 530 ° C, 30 seconds), only the roughness of the silicide is improved, and it is possible to cause excessive metal nickel to enter the gate dielectric layer, affecting the characteristics of the device.
  • annealing conditions 410 ° C, 60 seconds
  • Figure 5 shows an SEM image of the gate electrode when the first annealing temperature is appropriate. It can be seen from Fig. 5(a) that after the first annealing (annealing conditions: 360 ° C, 60 seconds), most of the polysilicon at the top has been converted into silicide, and some polysilicon remains in the vicinity of the gate dielectric. It can be seen from Fig. 5(b) that after the second annealing (annealing conditions: 530 ⁇ , 30 seconds), the entire gate electrode has been converted into silicide to form a fully silicided metal gate electrode.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

全硅化金属栅电极的制备方法 技术领域
本发明涉及微电子超深亚微米技术互补金属氧化物半导体器件 （CMOS ) 及超大 规模集成技术领域， 尤其涉及一种用于超深亚微米技术互补金属氧化物半导体器件以 及电路的全硅化金属栅电极的制备方法。 背景技术
自从第一个晶体管发明以来， 经过半个多世纪的飞速发展， 晶体管的横向和纵向 尺寸都迅速缩小。 根据国际半导体技术发展蓝图 （ITRS ) 的预测， 到 2018 年晶体管 的特征尺寸将达到 7nm。 尺寸的持续缩小使晶体管的性能 （速度） 不断提高， 也使得 我们能够在相同面积的芯片上集成更多的器件， 集成电路的功能越来越强， 同吋降低 了单位功能成本。
在集成电路的发展中， 多晶硅作为栅电极已有四十多年的历史， 但是当传统的多 晶硅栅晶体管尺寸缩小到一定程度后， 将出现多晶硅耗尽效应和 PMOS管硼穿透效应 以及过高的栅电阻， 这将阻碍晶体管性能的提升， 成为进一步提高互补金属氧化物半 导体 （CMOS ) 器件性能的瓶颈。
为了解决这些问题， 研究人员进行了大量的研究工作以寻找合适的替代技术。 而 金属栅被认为是最有希望的替代技术。 用金属作栅电极， 可以从根本上消除多晶硅栅 耗尽效应和 P型场效应晶体管的硼 （B) 穿透效应， 同吋获得非常低的栅极薄层电阻。
在各类金属栅制备方法中，全硅化金属栅技术是一种比较简单的金属栅制备方法, 并与 CMOS工艺具有很好的兼容性。早期的全硅化金属栅制备方法一般都采用一步退 火工艺， 即只采用一次退火实现整个栅电极的硅化， 因此一歩退火工艺制备方法十分 简单。 但是一歩退火工艺方法存在生成的硅化物薄膜不均匀、 存在线宽效应等缺点。
发明内容
本发明的目的在于提供一种全硅化金属栅的制备方法， 以克服一步退火方法存在 的缺点。
为实现上述目的， 本发明提供的全硅化金属栅的制备方法， 主要步骤如下： 1) 局部氧化隔离或浅槽隔离， 进行注入前氧化， 然后注入 14N+;
2) 漂净注入前氧化膜， 栅氧化， 并沉积多晶硅；
3) 光刻、 刻蚀形成多晶硅栅电极；
4) 注入杂质， 并进行杂质激活；
5) 淀积金属镍 Ni;
6) 第一次退火， 使金属镍和一部分多晶硅反应；
7) 选择去除未反应的金属镍 Ni;
8) 第二次退火， 使栅电极全部转变为金属镍硅化物形成全硅化物金属栅电极。 其中， 歩骤 1) 中： 局部氧化的温度为 1000°C， 隔离层厚度为 3000-5000A, 前氧 化的厚度为 100-200 A; 注入 14N+的条件为： 注入能量为 10-30Kev， 注入剂量为 Ixl014-6xl0l4cm— 2。
其中， 步骤 2) 中： 漂净注入前氧化膜是先采用体积比为 H20:HF=9:1的溶液进行 漂洗， 然后采用第一腐蚀液清洗 10分钟， 第二腐蚀液清洗 5分钟， 氢氟酸 /异丙醇的 水溶液室温下浸渍 5分钟； 该第- 腐蚀液是体积比为 5:1的 H2S04与 ¾02溶液； 该第 二腐蚀液是体积比为 0.8:1:5的 NH4OH+H202+H20溶液；氢氟酸 /异丙醇 /水的体积比为 0.2-0.7%:0.01-0.04%:1%； 栅氧化并沉积多晶硅中， 栅氧化的厚度为 15-50 A， 沉积多 晶硅采用化学气相淀积方法， 沉积的多晶硅的厚度为 1000-2000 A。
其中， 步骤 3) 中是采用厚度为 1.5微米的光刻胶作为掩模进行光刻， 采用反应离 子刻蚀多晶硅， 将场区内多晶硅刻蚀干净， 形成多晶硅栅电极。
其中， 歩骤 4) 中： 对于 P型场效应晶体管注入的杂质为 P型杂质 BF2; 对于 N 型场效应晶体管注入的杂质为 N型杂质 As或 P; 对于 P型杂质 BF2， 注入条件为： 注 入能量 15-30Kev， 注入剂量为 Ixl015-5xl015cm— 2； 对于 N型杂质 As， 注入条件为： 注 入能量 30-60Kev， 注入剂量为 lxlO15- 5xl015cm— 2； 对于 N型杂质 P， 注入条件为： 注 入能量 40-60Kev，注入剂量为 1χ1015-3χ1015 cm—2;杂质激活的条件为：温度 950-1020°C， 时间 2-20秒。
其中， 步骤 5) 中淀积金属镍 Ni的厚度为 600至 2000 A。
其中， 步骤 6) 中的第一次退火， 控制多晶硅栅顶部的多晶硅与金属镍反应生成 镍硅化物， 而在靠近栅介质界面附近保 ¾有一部分多晶硅没有反应， 退火条件为： 温 度 340至 390。C， 时间 30至 90秒。
其中， 歩骤 7) 'I'是采用第一腐蚀液进行腐蚀去除， 该第一腐蚀液为体积比 5:1的 H2S04与 H202溶液， 腐蚀时间为 20至 30分钟；
其中， 步骤 8 ) 中的第二次退火， 使剩余的靠近栅介质界面附近的多晶硅与金属 镍反应生成镍硅化物， 整个栅电极全部转变为镍硅化物， 形成全硅化金属栅电极； 退 火条件为： 温度 450至 600°C， 时间 30至 90秒。
本发明具有以下有益效果：
1、本发明提供的这种制备金属栅电极的方法， 采用金属硅化物作为金属互补氧化 物半导体器件的栅电极。 与其它金属栅电极制备方法相比工艺复杂度大大降低， 比较 简单， 不存在污染问题和刻蚀困难；
2、本发明提供的这种制备金属栅电极的方法， 克服了一步退火工艺存在的硅化物 薄膜不均勾、 存在线宽效应等缺点；
3、 本发明提供的这种制备金属栅电极的方法， 其制备方法简单,易于集成， 与 CMOS工艺具有很好的兼容性， 具有很大的应用价值。 附图说明
下而结合附图和实施例对本发明进一步说明：
图 1 是本发明提供的采用两歩退火工艺制备全硅化金属栅屯极电容的方法流程 图。
图 2(a)- (f)是本发明提供的采用两步退火工艺制备全硅化金属栅电极电容的工艺流 程图。
图中的符号： 1-体硅衬底， 2-栅氧化层， 3-多晶硅栅电极， 4-STI 隔离， 5-离子注 入元素， 6-淀积的金属镍 Ni， 7-反应生成的金属镍 Ni硅化物。
图 3 (a)、 图 3 (b)示出了第一次退火温度过低时栅电极的 SEM图； 其中图 3 (a) 为第一次退火后栅电极的扫描电子显微图 （SEM)， 其中退火条件为 280°C， 60秒； 图
3 (b) 为第二次退火后栅电极 SEM图， 其中退火条件这 530°C， 30秒。
图 4 (a)、 图 4 (b)示出了第一次退火温度过高时栅电极的 SEM图； 其中图 4 (a) 为第一次退火后栅电极 SEM图， 其中退火条件为 410°C， 60秒； 图 4 (b) 为第二次 退火后栅电极 SEM图， 其中退火条件为 530度、 30秒。
图 5 (a)、 图 5 (b)示出了第一次退火温度合适时栅电极的 SEM图； 其中图 5 (a) 为第一次退火后栅电极 SEM图， 其中退火条件为 360°C， 60S； 图 5 (b) 为第二次退 火后栅电极 SEM图， 其中退火条件为 530度、 30秒。 具体实施方式
为使本发明的目的、 技术方案和优点更加清楚明白， 以下结合具体实施例， 并参 照附图， 对本发明进一步详细说明。
本发明提供了一种制备用于超深亚微米互补金属氧化物半导体器件和电路的全硅 化金属栅电极的方法， 采用淀积金属镍 Ni并进行两次快速热退火 RTA, 使金属镍 Ni 和多晶硅完全反应形成全硅化物金属栅。
如图 1所示， 图 1是本发明提供的采用两步退火工艺制备全硅化金属栅电极电容 的方法流程图， 该方法包括以下步骤：
步骤 101 : 局部氧化隔离或浅槽隔离， 进行注入前氧化， 然后注入 14N+; 在本步 骤中， 氧化温度为 1000°C， 隔离层厚度为 3000-5000 A; 注入前氧化的步骤中， 氧化 厚度为 100-200 A; 注入 14N+的步骤中， 注入条件为： 注入能量为 10- 30Kev， 注入剂 量为 I x l 014-6x l 014cm一 2。
步骤 102: 漂净注入前氧化膜， 栅氧化， 并沉积多晶硅；
在本步骤中， 采用体积比为 H20:HF=9:1 的溶液进行漂洗， 然后采用第一腐蚀液 清洗 10分钟， 第二腐蚀液清洗 5分钟， 氢氟酸 /异丙醇水溶液室温下浸渍 5分钟； 该 第一腐蚀液是体积比为 5:1 的 H2S04与 ¾02溶液； 该第二腐蚀液是体积比为 0.8:1 :5 的 NH4OH+H202+¾0溶液； 氢氟酸 /异丙醇 /水是体积比为 0.2-0.7%:0.01- 0.04%:1%。
栅氧化的厚度为 15至 50 A， 沉积多晶硅采用化学气相淀积 LPCVD方法， 沉积的 多晶硅的厚度为 1000 至 2000 A。
步骤 103: 光刻、 刻蚀形成多晶硅栅电极；
在本步骤中， 采用厚度为 1.5微米的光刻胶（例如 9918型光刻胶） 作为掩模进行 光刻， 采用反应离子刻蚀多晶硅， 将场区内多晶硅刻蚀干净， 形成多晶硅栅电极。
步骤 104: 注入杂质， 并进行杂质激活；
在本步骤中， 杂质激活的条件为： 温度 950-1020°C， 吋间 2-20秒， P型场效应晶 体管注入的杂质为 P型杂质 BF2， N型场效应晶体管 N型杂质 As或 P; 对于 P型杂质 BF2， 注入条件为： 注入能量 15- 30Kev， 注入剂量为 I x l 015-5 x l 015cm_2 ; 对于 N型杂 质 As, 注入条件为： 注入能量 30-60Kev， 注入剂量为 1 <1015- 5x l 015 cm— 2； 对于 N型 杂质 P， 注入条件为： 注入能量 40-60Kev， 注入剂量为 l x lO15- 3 < 1015cm— 2 ； 所述杂质 激活的条件为： 温度 950-1020°C， 时间 2-20秒。 歩骤 105: 淀积金属镍 Ni;
在本歩骤中， 淀积金属镍 Ni的厚度为 600-2000 A,
歩骤 106: 第一次退火， 使一部分多晶硅与金属镍反应；
本步骤中， 退火条件为： 温度 340-390°C， 时间 30-90秒；
歩骤 107: 选择去除未反应的金属镍 Ni;
在本步骤中，采用第一腐蚀液进行腐蚀去除，该第一腐蚀液为体积比 5:1的 H2S04 与 H202溶液， 腐蚀时间为 20-30分钟。
步骤 108: 第二次退火， 使栅电极全部转变为金属镍硅化物形成全硅化物金属栅 电极；
本歩骤中退火的条件为： 温度 450-600°C， 时间 30-90秒。
图 2示出了本发明提供的采用两歩退火工艺制备金属栅电极电容的工艺流程图； 其中， （a)为淀积多晶硅并光刻、 刻蚀后形成的结构示意图； （b)为离子注入并退火激活 示意图； （c)为淀积金属镍 Ni后示意图； （d)为第一次退火后栅电极示意图； （e)为选择 去除未反应的金属镍 Ni后示意图； （f) 为第二次退火后栅电极示意图。 以下结合具体 实施例进一步详细说明本发明提供的技术方案：
步骤 1 : 场氧化； 1000°C , 3000-5000 A;
步骤 2: 注入前氧化； 厚 100-200 A;
步骤 3: 注入 14N+， 能量为 10-30Kev， 剂量为 I xl014-6xl014cm_2 ;
步骤 4: 漂净注入前氧化层； H20:HF=9:1溶液中漂净；
步骤 5:清洗；第一腐蚀液清洗 10分钟，第二腐蚀液清洗 5分钟， HF/异丙醇（IPA) 水溶液室温下浸渍 5分钟；
歩骤 6: 栅氧化； 厚度 15-50 A;
步骤 7: 化学气相淀积 LPCVD多晶硅； 2000 A;
歩骤 8: 光刻多晶硅； 采用厚度为 1.5微米的光刻胶 （例如 9918型光刻胶） 作为 掩模；
歩骤 9: 反应离子刻蚀多晶硅； 场区刻千净多晶硅；
步骤 10: 栅注入； 注入杂质 As， 注入能量 10-50Kev， 剂量 I x l015-5xl015cm— 2； 歩骤 11 : 杂质激活； 950-1020°C , 时间 2-20秒；
步骤 12: 溅射金属镍 Ni; 厚度， 1400 A;
步骤 13: 第一次快速热退火 RTA; 温度 360°C， 时间 60秒； 步骤 14: 选择腐蚀； 第一腐蚀液 (H2S04:H20,=5: 1 ), 20- 30分钟， 将未反应的金 属镍 Ni去除；
步骤 15: 第二次快速热退火 RTA； 温度 530 °C， 时间 30秒。
本发明的关键技术是控制第一次退火条件。 如果第一次退火温度过高或时间过长 会导致栅电极在第一次退火时就被全部硅化； 第一次退火温度过低会导致多晶硅没有 充分的反应， 使得第二次退火后也不能将栅电极完全硅化， 造成多晶硅栅电极未完全 硅化； 合适的退火条件是， 第一次退火后在栅介质附近只保留一部分多晶硅没有被硅 化， 第二次退火后将栅电极全部硅化。
图 3示出了第一次退火温度过低时栅电极的 SEM图。 从图 3 (a) 中可以看出第 一次退火温度过低 （退火条件： 280Ό , 60 秒） 时， 只有栅顶部一少部分多晶硅与金 属镍反应生成镍硅化物， 大部分多晶硅没有和 Ni反应； 从图 3 (b) 可以看出， 第二 次退火后 （退火条件： 53(TC， 30 秒） 硅化物的厚度变厚了， 但是仍然有大部分多晶 硅没有反应生成硅化物，造成未完全硅化现象。
图 4示出了第一次退火温度过高时栅电极的 SEM图。 从图 4 (a) 中可以看出第 一次退火温度过高 （退火条件： 410°C， 60 秒） 时， 第一次退火就使整个多晶硅栅电 极全部转变为硅化物； 从图 4 (b) 可以看出， 第二次退火后 （退火条件： 530°C， 30 秒） 仅改善了硅化物的粗糙度， 而且有可能导致过多的金属镍进入栅介质层， 影响器 件的特性。
图 5示出了第一次退火温度合适时栅电极的 SEM图。 从图 5 (a) 可以看出第一 次退火后 （退火条件： 360°C， 60 秒） 顶部的大部分多晶硅已经转变为硅化物， 而靠 近栅介质附近仍然保留有一部分多晶硅没有形成硅化物； 从图 5 (b) 可以看出， 第二 次退火后 （退火条件： 530Ό , 30 秒） 整个栅电极都已经转变为硅化物， 形成全硅化 金属栅电极。
以上所述的具体实施例， 对本发明的目的、 技术方案和有益效果进行了进一步详 细说明， 所应理解的是， 以上所述仅为本发明的具体实施例而已， 并不用于限制本发 明， 凡在本发明的精神和原则之内， 所做的任何修改、 等同替换、 改进等， 均应包含 在本发明的保护范围之内。

Claims

权 利 要 求
1、 一种全硅化金属栅的制备方法， 包括以下步骤-
1 ) 局部氧化隔离或浅槽隔离， 进行注入前氧化， 然后注入 14N+ ;
2) 漂^注入前氧化膜， 栅氧化， 并沉积多晶硅；
3 ) 光刻、 刻蚀形成多晶硅栅电极；
4) 注入杂质， 并进行杂质激活；
5 ) 淀积金属镍 Ni ;
6) 进行第一次退火， 控制在金属镍和部分多晶硅反应；
7 ) 选择去除未反应的金屈镍 Ni;
8)进行第二次退火，使栅电极全部转变为金属镍硅化物形成全硅化物金属栅电极。
2、 根据权利要求 1的制备方法， 其中， 步骤 1中：
局部氧化的温度为 1000Ό , 隔离层厚度为 3000- 5000A, 前氧化的厚度为 100-200 A; 注入 14N+的条件为: 注入能量为 10-30Kev， 注入剂量为 l ><1014-6x l 014 Cm—2。
3、 根据权利要求 1的制备方法， 其中， 步骤 2中：
漂净注入前氧化膜是先采用体积比为 H20:HF=9: 1 的溶液进行漂洗， 然后采用第 -一腐蚀液清洗 10分钟， 第二腐蚀液清洗 5分钟， 以及在氢氟酸 /异丙醇的水溶液中室 温下浸渍 5分钟； 该第一腐蚀液是体积比为 5:1的 H2S04与 ¾02溶液； 该第二腐蚀液 是体积比为 0.8:1 :5 的 Ν ΟΗ+Η202+Η20 溶液； 氢氟酸 /异丙醇 /水的体积比为 0.2%-0.7%:0.01%-0.04%:1%；
栅氧化并沉积多晶硅中， 栅氧化的厚度为 15-50 A, 沉积多晶硅采用化学气相淀积 方法， 沉积的多晶硅的厚度为 1000- 2000 Α。
4、 根据权利要求 1的制备方法， 其中， 步骤 3中是采用厚度为 1.5微米的光刻胶 作为掩模进行光刻， 采用反应离子刻蚀多晶硅， 将场区内多晶硅刻蚀干净， 形成多晶 硅栅电极。
5、 根据权利要求 1的制备方法， 其中， 步骤 4中： 对于 Ρ型场效应晶体管注入的 杂质为 Ρ型杂质 BF2 ; 对于 N型场效应晶体管注入的杂质为 N型杂质 As或 P;
对于 P 型杂质 BF2， 注入条件为： 注入能量 15-30Kev， 注入剂量为 I x l015-5x l015cm"2;
对于N型杂质 As， 注入条件为： 注入能量 30-60Kev, 注入剂量为 1 χ1015-5χ 1015 cm ；
对于 N型杂质 P，注入条件为：注入能量 40- 60Kev，注入剂量为 1 χ 10Ι5-3χ 1015 cm-2; 杂质激活的条件为： 温度 950-102CTC， 时间 2-20秒。
6、 根据权利要求 1 的制备方法， 其中， 歩骤 5中， 淀积金属镍 Ni的厚度为 600 至 2000 A c
7、 根据权利要求 1的制备方法， 其中， 步骤 6中的第一次退火， 控制多晶硅栅顶 部的多晶硅与金属镍反应生成镍硅化物， 而在靠近栅介质界面附近保留有一部分多晶 硅没有反应， 退火条件为： 温度 340至 39(TC， 时间 30至 90秒。
8、 根据权利要求 1的制备方法， 其中， 步骤 7中， 是采用第一腐蚀液进行腐蚀去 除， 该第一腐蚀液为体积比 5: 1的 H2S()4与 02溶液， 腐蚀时间为 20至 30分钟。
9、 根据权利要求 1的制备方法， 其中， 步骤 8中的第二次退火， 使剩余的靠近栅 介质界面附近的多晶硅与金属镍反应生成镍硅化物，整个栅电极全部转变为镍硅化物， 形成全硅化金属栅电极； 退火条件为： 温度 450至 600°C， 时间 30至 90秒。
PCT/CN2010/074603 2009-12-02 2010-06-28 全硅化金属栅电极的制备方法 WO2011066750A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US12/990,042 US20110237048A1 (en) 2009-12-02 2010-06-28 Method for manufacturing a full silicidation metal gate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN2009102416862A CN102087969A (zh) 2009-12-02 2009-12-02 一种全硅化金属栅的制备方法
CN200910241686.2 2009-12-02

Publications (1)

Publication Number Publication Date
WO2011066750A1 true WO2011066750A1 (zh) 2011-06-09

Family

ID=44099696

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2010/074603 WO2011066750A1 (zh) 2009-12-02 2010-06-28 全硅化金属栅电极的制备方法

Country Status (3)

Country Link
US (1) US20110237048A1 (zh)
CN (1) CN102087969A (zh)
WO (1) WO2011066750A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103035497B (zh) * 2011-09-29 2016-01-06 中芯国际集成电路制造(上海)有限公司 镍硅化物形成方法及晶体管形成方法
CN103515319B (zh) * 2012-06-20 2015-08-19 中芯国际集成电路制造(上海)有限公司 形成cmos全硅化物金属栅的方法
CN102969234B (zh) * 2012-11-01 2017-04-19 上海集成电路研发中心有限公司 一种金属栅电极的制造方法
CN103165433B (zh) * 2013-04-01 2015-10-28 清华大学 一种半导体栅结构及其形成方法
CN103943482B (zh) * 2014-04-22 2017-08-08 上海华力微电子有限公司 降低多晶硅栅极与活化区镍硅化物厚度比的方法
CN104409340A (zh) * 2014-11-07 2015-03-11 上海华力微电子有限公司 自对准金属硅化物的形成方法
CN117936570A (zh) * 2024-03-20 2024-04-26 芯众享(成都)微电子有限公司 局部加厚栅介质的平面型分裂栅SiC MOSFET器件及其制造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101447421A (zh) * 2007-11-28 2009-06-03 中国科学院微电子研究所 一种制备金属栅电极的方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003017555A (ja) * 2001-06-29 2003-01-17 Hitachi Ltd 半導体集積回路装置およびその製造方法
US7247569B2 (en) * 2003-12-02 2007-07-24 International Business Machines Corporation Ultra-thin Si MOSFET device structure and method of manufacture
US7105889B2 (en) * 2004-06-04 2006-09-12 International Business Machines Corporation Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectrics
US8629021B2 (en) * 2007-11-02 2014-01-14 Texas Instruments Incorporated Integration scheme for an NMOS metal gate
TW200910526A (en) * 2007-07-03 2009-03-01 Renesas Tech Corp Method of manufacturing semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101447421A (zh) * 2007-11-28 2009-06-03 中国科学院微电子研究所 一种制备金属栅电极的方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SANG HAIPING ET AL.: "Two-Step Ni Silicide Process And Influence Of Protective N2 Gas", JOURNAL OF SEMICONDUCTORS, vol. 30, no. 9, September 2009 (2009-09-01), pages 096002-1 - 096002-3 *

Also Published As

Publication number Publication date
CN102087969A (zh) 2011-06-08
US20110237048A1 (en) 2011-09-29

Similar Documents

Publication Publication Date Title
KR100352758B1 (ko) 반도체디바이스및이를제조하기위한방법
WO2011066750A1 (zh) 全硅化金属栅电极的制备方法
US6475874B2 (en) Damascene NiSi metal gate high-k transistor
JP4484392B2 (ja) 半導体素子のゲート電極形成方法
US5937315A (en) Self-aligned silicide gate technology for advanced submicron MOS devices
CN105336620B (zh) 半导体结构及其形成方法
JPH10173177A (ja) Ｍｉｓトランジスタの製造方法
KR20030078205A (ko) 소오스 및 드레인 영역의 실리사이드층이 확장된 모스트랜지스터 및 그 제조방법
TW200423400A (en) Schottky barrier transistor and method of manufacturing the same
US20070132057A1 (en) Active region spacer for semiconductor devices and method to form the same
US7867901B2 (en) Method for forming silicide in semiconductor device
Huang et al. A Unique Approach to Generate Self-Aligned T-Gate Transistors in Counter-Doped Poly-Si With High Etching Selectivity and Isotropy
KR100511043B1 (ko) 반도체 장치의 금속 실리사이드 층의 형성 방법
CN101447421B (zh) 一种制备金属栅电极的方法
CN102074468A (zh) 一种实现源漏和栅分开硅化的方法
JP2004356576A (ja) 半導体装置およびその製造方法
US7517780B2 (en) Method for eliminating polycide voids through nitrogen implantation
CN111785782B (zh) 一种适用于平面工艺的InAs-GaSb TFET
KR100588780B1 (ko) 반도체 소자의 제조 방법
KR100545902B1 (ko) 반도체 소자의 제조 방법
KR100765617B1 (ko) 반도체 소자의 살리사이드 형성 방법
JPH113872A (ja) 半導体装置の製造方法
KR100806135B1 (ko) 금속 게이트전극을 갖는 반도체소자의 제조 방법
CN1283001C (zh) 一种晶体管的制造工艺
KR100334866B1 (ko) 반도체소자의트랜지스터형성방법

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 12990042

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10834183

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10834183

Country of ref document: EP

Kind code of ref document: A1