WO2011063650A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2011063650A1
WO2011063650A1 PCT/CN2010/074620 CN2010074620W WO2011063650A1 WO 2011063650 A1 WO2011063650 A1 WO 2011063650A1 CN 2010074620 W CN2010074620 W CN 2010074620W WO 2011063650 A1 WO2011063650 A1 WO 2011063650A1
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layer
source
dielectric layer
gate
metal silicide
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PCT/CN2010/074620
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English (en)
French (fr)
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骆志炯
尹海洲
朱慧珑
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中国科学院微电子研究所
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Priority to US12/937,321 priority Critical patent/US8658485B2/en
Publication of WO2011063650A1 publication Critical patent/WO2011063650A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Definitions

  • the present invention relates to the field of semiconductors, and in particular to a semiconductor device and a method of fabricating the same, and more particularly to a transistor structure for forming a metal silicide in a gate, a source/drain region, and a method of fabricating the same. Background technique
  • a self-aligned silicide technique has been proposed.
  • a metal such as titanium (Ti), tungsten (W) or cobalt (Co) and a semiconductor such as Si are formed on a substrate through a source, a drain region composed of an impurity diffusion layer and a gate composed of polysilicon.
  • the reaction product is a silicide (metal silicide).
  • the metal silicide is formed only of a metal material in contact with the source/drain regions and the gate, it is referred to as a "self-aligned" silicidation process.
  • a metal silicide By forming a metal silicide, the resistivity in each region is reduced.
  • the thickness of the silicide film in the reaction region is increased.
  • this metal diffuses into the active region of the device, it causes unnecessary unnecessary silicidation in the junction region.
  • This causes junction leakage in the impurity diffusion layers of the gate and/or source/drain regions. That is, the metal silicide formed in the junction region will become a source of leakage current.
  • the operating rate of the semiconductor device can be increased by lowering the resistance of the gate. Therefore, it is desirable to convert the silicon material in the gate to silicide as much as possible in order to reduce its resistance. That is, it is often desirable to have "complete silicidation" in the gate.
  • the gate is completely silicided, if the silicidation reaction is simultaneously performed on the gate and the source/drain regions according to a conventional technique, an excessively thick metal silicide will be formed in the source/drain regions, resulting in an undesired leak. Current.
  • a dielectric layer is laid thereon, and then a contact hole is formed at a portion corresponding to the gate and the source/drain regions, and the contact hole is formed through the contact hole.
  • a metal such as aluminum or copper is filled in to form a gate, source/drain connection line. Since the gate region is higher than the source/drain regions in a typical device, the depths of the corresponding contact holes of the gate and source/drain regions in the dielectric layer are different. Thus, for example, when forming contact holes by reactive ion etching (RIE), it is necessary to separately control the depth of etching for the gate and source/drain regions, which is difficult in the process, especially in today's device integration. The situation is getting bigger and bigger. Summary of the invention
  • One of the objects of the present invention is to provide a semiconductor device and a method of fabricating the same that enable a gate resistance of a semiconductor device to be sufficiently reduced without causing an undesired source of leakage current, while the structure of the semiconductor device is advantageous for contact holes in a subsequent process. Formation.
  • a method of fabricating a semiconductor device comprising: forming a transistor structure including a gate, a source and a drain region in a semiconductor substrate; performing a first silicidation process at the source and Forming a first metal silicide layer on the drain region; depositing a first dielectric layer on the substrate, the top of the first dielectric layer being flat with the top of the gate region; and the source and the first dielectric layer Forming a contact hole at a portion corresponding to the drain region; and performing a second silicidation process to form a second metal silicide in the gate region and the contact hole, wherein the first metal silicide layer causes the source and drain regions to be avoided
  • the silicidation reaction occurs again during the second silicidation treatment.
  • the step of performing the first silicidation process comprises: depositing a first material on the substrate and performing annealing to cause a silicidation reaction of the first material in the source and drain regions to form a first metal silicide layer.
  • the step of performing the second silicidation process includes: implanting polysilicon in the contact hole; and depositing a second material on the first dielectric layer and performing annealing to cause a silicide reaction of the second material in the gate region and the contact hole to form The second metal silicide.
  • the annealing temperature in the second silicidation process is selected such that the second material does not substantially react with the source and drain regions.
  • the annealing temperature in the second silicidation process is not higher than the temperature in the first silicidation process.
  • the method further comprises: forming a masking layer on the gate region to prevent the first material from reacting with the gate region before performing the first silicidation process; and removing the masking layer before performing the second silicidation process .
  • the step of depositing the first dielectric layer on the substrate comprises: depositing a first dielectric layer on the substrate, and then grinding the first dielectric layer using chemical mechanical polishing until the masking layer is exposed .
  • the step of implanting polysilicon in the contact hole comprises: depositing a polysilicon layer on the substrate, and then grinding the polysilicon layer using chemical mechanical polishing until the masking layer is exposed.
  • the gate region includes a gate insulating layer and a polysilicon layer, and a metal layer is formed between the gate insulating layer and the polysilicon layer.
  • the method further includes: after performing the second silicidation process, forming a second dielectric layer on the first dielectric layer, corresponding to the gate, source, and drain regions in the second dielectric layer The portion forms a contact hole, and a metal is deposited in the contact hole to form a connection line.
  • a semiconductor device comprising: a semiconductor substrate; at the semiconductor a transistor structure formed in a bulk substrate, the transistor structure including a gate, a source and a drain region; a first metal silicide layer formed on the source and drain regions; and a first formed on the semiconductor substrate a dielectric layer, a top of the first dielectric layer being flush with a top of the gate region; a contact hole formed in a portion of the first dielectric layer corresponding to the source and drain regions; and a contact hole and a gate A second metal silicide formed in the polar region, wherein the first metal silicide layer causes the source and drain regions to avoid re-silicide reaction during formation of the second metal silicide.
  • the first metal silicide layer is formed at a first annealing temperature and the second metal silicide is formed at a second annealing temperature not higher than the first annealing temperature.
  • the gate region includes a gate insulating layer, a metal layer, and a polysilicon layer which are sequentially formed.
  • the semiconductor device further includes: a second dielectric layer formed on the first dielectric layer; a contact hole formed in a portion of the second dielectric layer corresponding to the gate, the source, and the drain region; And a connecting line formed in the contact hole.
  • the resistivity of the gate can be lowered by forming a metal silicide in the gate region. Moreover, prior to siliciding the gate, a first metal silicide layer is first formed in the source/drain regions, the first metal silicide layer preventing the source/drain regions from occurring during silicidation of the gate The secondary silicidation effectively avoids the erosion of the silicide to the active region and thus prevents the formation of a source of leakage current.
  • a dielectric layer is deposited over the semiconductor substrate to be flush with the top of the gate.
  • a contact hole is formed in a portion corresponding to the source/drain regions in the dielectric layer, and a metal silicide is also formed in the contact hole, which is equivalent to "pulling" the height of the source/drain regions to the gate
  • the height of the poles is the same.
  • FIG. 1 to 10 are structural views showing respective stages of fabrication of a semiconductor device in accordance with an embodiment of the present invention. detailed description
  • the semiconductor structure includes a plurality of transistor structures 100A, 100B ⁇ separated by shallow trench isolation (STI) 101.
  • STI shallow trench isolation
  • the transistor structure (eg, 100A or 100B) includes a substrate 1000 doped with an N-type or P-type impurity, a lightly doped region 1001A doped with an N-type or P-type impurity, and a heavily doped region 1001B
  • the source/drain region 1001 is formed on a semiconductor substrate
  • the above transistor structure can be fabricated by the following steps. First, a gate electrode 1004 such as polysilicon is formed on a gate insulating layer 1002 such as SiO 2 ; then, a lightly doped region 1001A is formed using, for example, ion implantation using the gate electrode 1004 as a mask; A spacer 1005 is formed on the sidewall of the electrode 1004.
  • the spacer 1005 may comprise any suitable dielectric material, such as SiO 2 , SiN x or a combination thereof; and then both the gate electrode 1004 and the spacer 1005 are used as a mask. Ion implantation is performed to form a heavily doped region for B.
  • transistor structure can be formed in various ways. How to form a crystal tube structure is not a main feature of the present invention, and therefore, it is only briefly described in the present specification so that those skilled in the art can easily implement the present invention. One of ordinary skill in the art can fully envision other ways to fabricate such a transistor structure.
  • a metal layer 1003 may be additionally formed on the gate insulating layer 1002, and then the gate electrode 1004 is formed.
  • the metal layer 1003 may be one or a combination of TiN, TaN, ⁇ 1 ⁇ , and Ta.
  • the metal layer 1003 does not undergo a silicidation reaction with a semiconductor material such as polysilicon during the subsequent silicidation process, thereby preventing the metal silicide formed by the silicidation treatment in the gate electrode 1004 from coming into contact with the gate insulating layer 1002.
  • the masking layer 1006 is deposited over the entire structure, such as by chemical vapor deposition, in accordance with an embodiment of the present invention, wherein, for example, by engraving
  • the etch causes the masking layer 1006 to remain only over the gate electrode 1004, exposing the source/drain regions 1001.
  • Masking layer 1006 is, for example, composed of a nitride for preventing the deposited metal from reacting with the gate electrode 1004 when the source/drain regions are subsequently subjected to metal silicidation.
  • the masking layer 1006 may include SiO 2 , SiN, SiC, or the like.
  • a metal layer 1007 is deposited on the substrate.
  • the material of the metal layer 1007 may be, for example, Ni, Co, Ti, W or the like.
  • the deposited metal layer 1007 is silicided with the exposed source/drain regions 1001, thereby forming a metal silicide layer 1008.
  • the unreacted metal layer remaining on the substrate eg, the metal layer on the gate electrode
  • etching such as wet etching using phosphoric acid, hydrochloric acid, sulfuric acid or a mixture thereof, or It is carried out by other etching methods.
  • the structure obtained by the above treatment is shown in Fig. 3. Among them, it is particularly noted that the metal layer 1007 cannot react with the polysilicon in the gate electrode 1004 due to the presence of the masking layer 1006.
  • the mask layer 1006 is utilized to prevent the metal layer 1007 from reacting with the polysilicon in the gate electrode 1004.
  • the metal layer 1007 is only present on the source/drain regions 1001 by, for example, etching or the like, and is not present on the gate region. Thus, silicidation reaction in the gate region can also be prevented.
  • the annealing temperature and annealing time in the silicidation process depend on the kind of metal used and the thickness of the metal silicide layer 1008 to be formed. Simply put, the metal silicidation reaction is the phase shifting process of the material. When the temperature is higher than the phase shift temperature of the material, the material changes from the original phase to the other phase. Different phases of the material have different atomic arrangements and characteristics.
  • nickel ( ⁇ ) has a first phase shift temperature of about 250 ° C ; when the temperature is above 250 , nickel reacts with silicon to form NiSi.
  • nickel has another second phase shift temperature of about 700 ° C; when the temperature is higher than 700 ° C, NiSi will be converted to NiSi 2 . Therefore, an annealing temperature of 300 to 65 (TC is usually used to form the MSi. For example, an annealing temperature of less than 500 ° C can be used, and the annealing time is less than 60 seconds.
  • CoSi 2 is typically formed using a two-stage rapid annealing process.
  • the annealing temperature is about 300 to 650 ° C to form CoSi or Co 2 Si.
  • the annealing temperature is higher than 650 ° C to form low resistivity CoSi 2 .
  • a dielectric layer 1009 (such as SiO 2 ) is deposited on the surface of the substrate.
  • the thickness of the deposit should be sufficient to embed the protruding gate portion.
  • the deposited dielectric layer 1009 is polished, for example, by a chemical mechanical polishing (CMP) process, and the masking layer 1006 acts as a polish stop layer. That is, CMP is performed until the masking layer 1006 is exposed.
  • CMP chemical mechanical polishing
  • a hole is formed in a portion corresponding to the source/drain regions in the dielectric layer 1009, thereby forming a shape A source/drain contact hole 1010.
  • punching can be performed by RIE (Reactive Ion Etching).
  • polysilicon 1011 is filled in the formed contact hole 1010.
  • this can be done, for example, by the following steps. First, a polysilicon layer is deposited on the surface of the structure, the thickness of which should be sufficient to fill the formed contact holes 1010. Thereafter, the deposited polysilicon layer is polished by a CMP process, and the masking layer 1006 is also used as a polishing stop layer. That is, CMP is performed until the masking layer 1006 is exposed.
  • the masking layer 1006 is removed to expose the upper surface of the gate electrode 1004.
  • the masking layer 1006 is silicon nitride
  • the masking layer 1006 can be etched by a phosphoric acid solution.
  • the masking layer 1006 can be dry etched by an RIE process.
  • another metal layer 1012 is deposited on the upper surface of the structure shown in Fig. 7 (including the upper surface of the exposed gate electrode).
  • the metal layer 1012 may be Ni, Co, Ti, W, or the like. Annealing is performed at a temperature such that the deposited metal layer 1012 reacts with the polysilicon in the gate electrode 1004 and the polysilicon 1011 in the source/drain contact hole 1010 to form metal silicides 1013 and 1014.
  • the previously formed metal silicide layer 1008 should preferably have a blocking effect on the current silicidation reaction. That is, the metal silicide layer 1008 should preferably be capable of preventing the source/drain regions from undergoing a secondary silicidation reaction during the present annealing.
  • the temperature in the annealing treatment is not higher than the temperature in the first annealing treatment. Therefore, this annealing treatment does not affect the layer of metal silicide 1008 formed in the previous annealing process, so that the metal silicide layer 1008 can prevent the current silicidation reaction from spreading into the active region.
  • the metal silicide layer 1008 may be CoSi 2 formed by the above two-stage annealing treatment (annealing temperature: first stage 300 to 65 (TC, second stage is higher than 650 ⁇ ) ; and the metal layer 1012 may be Ni, It is annealed at a temperature of about 250 ° C to form a low resistivity NiSi.
  • the object 1008 may be an MSi formed by reacting Ni with Si at an annealing temperature of about 500 ⁇ ; and when annealing the metal layer 1012 also including Ni, an annealing temperature of about 400 ⁇ may be employed, thereby forming NiSi.
  • the metal layer 1012 should preferably have a sufficient thickness to completely convert the polysilicon in the gate electrode 1004 into a silicided metal. At this time, the polysilicon 1011 in the contact hole 1010 on the source/drain regions may be completely silicided. Thereafter, the residual metal after the reaction is removed, thereby obtaining the semiconductor structure according to the embodiment of the present invention shown in FIG.
  • the annealing temperature in the second silicidation reaction is not higher than the first silicidation reaction, the formation of the silicide layer 1008 on the source/drain regions during the second silicidation reaction can prevent the silicidation reaction from being diffused. Into the active area, the formation of a leakage current source is avoided. Moreover, since the polysilicon in the contact hole 1010 is also completely silicided into the silicide 1014, it is equivalent to "extending" the source/drain regions to be equal to the gate region.
  • a dielectric layer 1015 is deposited on the structure.
  • contact holes 1016 are formed at positions corresponding to the gate and source/drain regions, respectively.
  • the contact hole 1016 is formed by RIE.
  • a metal such as aluminum or copper is then deposited in the contact hole 1016 to form a connecting line 1017. Since the heights between the gate and source/drain regions are equal in the structure shown in FIG. 9, the contact holes 1016 corresponding to the respective regions have the same depth. Thus, for example, in the RIE process of etching contact holes, the etching conditions can be conveniently controlled.
  • the contact hole 1016 and the connection line 1017 are shown only on one transistor structure, but the contact hole and the connection line may also be formed on other transistor structures.
  • CMOS complementary metal oxide semiconductors
  • a silicide layer 1008 is first formed on the source/drain regions, so that when the gate silicide is subsequently formed, the active region of the drain/source portion is not affected, and thus the semiconductor is improved Device reliability.
  • the gate electrode is completely silicided, so that the resistance of the gate electrode can be sufficiently lowered.
  • silicide 1014 is formed on the drain/source region, the complexity of the subsequent process can be simplified.

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Description

半导体器件及其制造方法
技术领域
本发明涉及半导体领域， 具体地， 涉及一种半导体器件及其制造方法， 特别是涉 及在栅极、 源 /漏极区中形成金属硅化物的晶体管结构及其制造方法。 背景技术
随着技术的发展， 集成电路中器件的集成化程度越来越高， 导致晶片上单个器件 的尺寸越来越小。 为了抑制器件本身尺寸的小型化而导致寄生电阻增大， 提出了自对 准硅化物技术。 在这种技术中， 在衬底上通过杂质扩散层构成的源、 漏区以及由多晶 硅构成的栅极处， 形成金属如钛 （Ti)、 钨 （W) 或钴 （Co) 与半导体如 Si的反应生 成物即硅化物 （金属硅化物）。 由于金属硅化物仅由与源 /漏极区以及栅极相接触的金 属材料形成， 因此称之为 "自对准 "硅化工艺。 通过形成金属硅化物， 减少各区域中 的电阻率。
然而， 在进行硅化时， 如果存在过多的金属， 则会增大反应区域的硅化物膜的厚 度。 当这种金属扩散到元件的有源区时， 就在结区域中导致不必要的多余硅化反应。 这会在栅极和 /或源 /漏极区的杂质扩散层中引起结泄漏。 即， 结区域中形成的金属硅 化物将会成为漏电流源。
另一方面， 通过降低栅极的电阻可增加半导体器件的工作速率。 因此， 希望尽可 能多的将栅极中的硅材料转变成硅化物， 以便降低其电阻。 也就是说， 通常期望在栅 极中进行 "完全硅化"。 然而， 在完全硅化栅极时， 如果按照常规技术， 在栅极以及 源 /漏区上同时进行硅化反应， 那么将在源 /漏区中形成过厚的金属硅化物， 从而导致 不期望的漏电流。
此外， 在衬底上形成栅极、 源 /漏极结构之后， 在其上敷设一层介电层， 然后在与 栅极、源 /漏极区相对应的部位形成接触孔， 通过在接触孔中填入金属例如铝或铜来形 成栅极、 源 /漏极连接线。 由于通常的器件中栅极区高于源 /漏极区， 因此介电层中栅 极、 源 /漏极区分别对应的接触孔深度是不一样的。 这样， 例如在通过反应离子刻蚀 (RIE) 来形成接触孔时， 需要针对栅极、 源 /漏极区来分别控制刻蚀的深度， 这在工 艺上是困难的， 尤其是在现今器件集成度越来越大的情况下。 发明内容
鉴于上述问题， 提出了本发明。 本发明的目的之一在于提供一种半导体器件及其 制造方法， 使得能够充分降低半导体器件的栅电阻而不会导致不期望的漏电流源， 同 时该半导体器件的结构有利于后继工艺中接触孔的形成。
根据本发明的一个方面， 提供了一种制造半导体器件的方法， 包括： 在半导体衬 底中形成包括栅极、 源极和漏极区的晶体管结构； 执行第一硅化处理， 以在源极和漏 极区上形成第一金属硅化物层； 在衬底上沉积第一介电层， 该第一介电层的顶部与栅 极区的顶部持平； 在第一介电层中与源极和漏极区相对应的部位形成接触孔； 以及执 行第二硅化处理， 以在栅极区、 接触孔中形成第二金属硅化物， 其中， 第一金属硅化 物层使得源极和漏极区避免在第二硅化处理时再次发生硅化反应。
优选地， 执行第一硅化处理的步骤包括： 在衬底上沉积第一材料且进行退火， 使 第一材料在源极和漏极区发生硅化反应， 从而形成第一金属硅化物层。 执行第二硅化 处理的步骤包括： 在接触孔中注入多晶硅； 以及在第一介电层上沉积第二材料且进行 退火， 使第二材料在栅极区以及接触孔中发生硅化反应， 从而形成第二金属硅化物。 其中， 选择第二硅化处理中的退火温度， 使得第二材料实质上不会与源极和漏极区发 生反应。
优选地， 第二硅化处理中的退火温度不高于第一硅化处理中的温度。
优选地， 该方法还包括： 在执行第一硅化处理之前， 在栅极区上形成掩蔽层， 以 防止第一材料与栅极区发生反应； 以及在执行第二硅化处理之前， 去除该掩蔽层。
优选地， 在衬底上沉积第一介电层的歩骤包括： 在衬底上沉积第一介电层， 然后 使用化学机械抛光对该第一介电层进行研磨， 直至露出所述掩蔽层。
优选地， 在接触孔中注入多晶硅的步骤包括： 在衬底上沉积多晶硅层， 然后使用 化学机械抛光对该多晶硅层进行研磨， 直至露出所述掩蔽层。
优选地， 栅极区包括栅极绝缘层以及多晶硅层， 并且在栅极绝缘层与多晶硅层之 间形成有金属层。
优选地， 该方法还包括： 在执行第二硅化处理之后， 在第一介电层上形成第二介 电层， 在该第二介电层中与栅极、 源极、 漏极区相对应的部位形成接触孔， 并在接触 孔中沉积金属， 以形成连接线。
根据本发明的另一方面， 提供了一种半导体器件， 包括： 半导体衬底； 在该半导 体衬底中形成的晶体管结构， 所述晶体管结构包括栅极、 源极和漏极区； 在源极和漏 极区上形成的第一金属硅化物层； 在半导体衬底上形成的第一介电层， 该第一介电层 的顶部与栅极区的顶部持平； 在第一介电层中与源极和漏极区相对应的部位中形成的 接触孔； 以及在接触孔和栅极区中形成的第二金属硅化物， 其中， 第一金属硅化物层 使得源极和漏极区避免在形成第二金属硅化物的过程中再次发生硅化反应。
优选地， 第一金属硅化物层在第一退火温度下形成， 第二金属硅化物在不高于第 一退火温度的第二退火温度下形成。
优选地， 栅极区包括依次形成的栅极绝缘层、 金属层以及多晶硅层。
优选地， 该半导体器件还包括： 在第一介电层上形成的第二介电层； 在第二介电 层中与栅极、 源极、 漏极区相对应的部位形成的接触孔； 以及在接触孔中形成的连接 线。
根据本发明的实施例，通过在栅极区中形成金属硅化物，可以降低栅极的电阻率。 而且， 在对栅极进行硅化之前， 首先在源 /漏极区中形成第一金属硅化物层， 该第一金 属硅化物层可以防止源 /漏极区在对栅极进行硅化的过程中发生二次硅化，从而有效避 免了硅化物向有源区的侵蚀， 并因此可以防止漏电流源的形成。
此外， 根据本发明的实施例， 在半导体衬底上沉积了一层介电层， 使其与栅极顶 部齐平。通过在该介电层中与源 /漏极区相对应的部位中形成接触孔， 并且在接触孔中 也形成金属硅化物， 相当于将源 /漏极区的高度 "拉升"到与栅极的高度相同。 这样， 在后继工艺中， 当要在栅极、 源 /漏极区相对应的位置形成接触孔以便制造连接线时， 这些接触孔的深度是一样的， 从而可以降低形成接触孔的工艺如 RIE的难度。 附图说明
本领域技术人员通过结合附图阅读如下说明， 可以更好地理解本发明的上述以及 其他目的、 特征和优点。 在附图中：
图 1〜10是示出了根据本发明实施例的半导体器件的各制造阶段的结构图。 具体实施方式
以下， 将参照附图来描述本发明的实施例。
需要指出， 附图仅仅是示意性的， 用来说明本发明的实施例。 为了清楚起见， 附 图中各个部分、 区域的大小被放大， 而且并非是按比例绘制的。 另外， 附图中所示出 的各个部分、 区域的形状是理想情况下的示例， 在实际中可能由于制造工艺或公差而 造成与图示形状的偏离。 例如， 图中示出为直角的各角落部位在实际中可以为钝角或 者为圆滑的形状。 此外， 在以下描述中， 当某一层被称作在另一层之上时， 不排除这 两层之间存在中间层的可能。
图 1示出了根据本发明实施例的一半导体结构的示意图。 该半导体结构包括多个 经浅沟槽隔离 （STI) 101分隔的晶体管结构 100A、 100B〜。 尽管在以下的描述中， 针 对半导体晶片上形成的多个晶体管结构来进行描述， 但是应该指出的是， 本发明同样 适用于单个晶体管结构。
这种半导体结构例如可以通过常规的 CMOS工艺来制作。 具体地， 例如， 晶体管 结构 （如 100A或 100B ) 包括经 N型或 P型杂质掺杂的衬底 1000, 经 N型或 P型杂质掺杂 的轻度掺杂区 1001A以及重度掺杂区 1001B所构成的源 /漏极区 1001， 在半导体衬底
1000上形成的栅极绝缘层 1002， 以及在栅极绝缘层 1002之上形成的栅电极 1004。
具体地， 例如， 上述晶体管结构可通过如下步骤来制作。 首先， 在例如 Si02之类 的栅极绝缘层 1002上形成例如多晶硅的栅电极 1004;然后，利用栅电极 1004作为掩模， 例如通过离子注入来形成轻度掺杂区 1001A; 接着， 在栅电极 1004的侧壁上形成间隔 物 1005， 间隔物 1005可以包含任何适当的介电材料， 例如 Si02、 SiNx或其组合物； 然 后利用栅电极 1004以及间隔物 1005两者作为掩模， 再进行离子注入， 以形成重度掺杂 区讓 B。
在此， 需耍指出的是， 可以通过多种方式来形成上述的晶体管结构。 如何形成晶 体管结构并非本发明的主要特征所在， 因此在本说明书中只是对其进行简要的介绍， 以便本领域普通技术人员能够容易地实施本发明。 本领域普通技术人员完全可以设想 别的方式来制作这种晶体管结构。
另外， 根据本发明的实施例， 优选地可以在栅极绝缘层 1002上另外形成一金属层 1003, 然后再形成栅电极 1004。 例如， 该金属层 1003可以为 TiN、 TaN、 ΉΑ1Ν及 Ta中 的一种或其组合。 优选地， 该金属层 1003在随后的硅化处理过程中并不与半导体材料 如多晶硅发生硅化反应， 从而避免栅电极 1004中通过硅化处理而形成的金属硅化物与 栅极绝缘层 1002相接触。
通过如上所述， 形成了图 1中所示的晶体管结构 100A、 100B之后， 根据本发明的 实施例， 在整个结构之上例如通过化学气相沉积等技术， 沉积掩蔽层 1006, 其中， 例 如通过刻蚀使得掩蔽层 1006仅留于栅电极 1004之上， 而露出源 /漏极区 1001。该掩蔽层 1006例如由氮化物构成， 用来在随后对源 /漏极区进行金属硅化处理时， 防止沉积的金 属与栅电极 1004发生反应。 例如， 该掩蔽层 1006可以包括 Si02、 SiN、 SiC等。
然后， 如图 2所示， 在衬底上沉积金属层 1007。 该金属层 1007的材料例如可以是 Ni、 Co、 Ti、 W等。 然后， 通过在一定温度下进行退火， 使得沉积的金属层 1007与露 出的源 /漏极区 1001发生硅化反应， 从而形成金属硅化物层 1008。衬底上残留的未反应 金属层 （如， 栅电极上的金属层） 通过刻蚀去除， 这种刻蚀例如是利用磷酸、 盐酸、 硫酸或其混合物等进行的湿法刻蚀， 或者也可通过其他刻蚀方式来进行。 附图 3中示 出了经上述处理后得到的结构。 其中， 特别需要指出， 由于掩蔽层 1006的存在， 金属 层 1007不能与栅电极 1004中的多晶硅发生反应。
这里需要指出的是， 在以上描述的实施例中， 利用掩蔽层 1006来防止金属层 1007 与栅电极 1004中的多晶硅发生反应。 但是， 本领域技术人员可以想到其他方式来防止 这种反应的发生。 例如， 不是沉积掩蔽层 1006， 而是通过例如刻蚀等方式使得金属层 1007仅存在于源 /漏极区 1001上， 而不存在于栅极区上。这样， 也可以防止在栅极区中 发生硅化反应。
硅化处理中的退火温度与退火时间取决于所使用的金属种类以及所要形成的金 属硅化物层 1008的厚度。 简单而言， 金属硅化反应即为材料的相移过程。 当温度高于 材料的相移温度时， 该材料就会从原有相转变为另一相。 材料的不同相之间具有不同 的原子排列和特性。
例如， 镍 （Νί) 的第一相移温度约为 250°C ; 当温度高于 250Γ时， 镍将与硅反应 而形成 NiSi。 此外， 镍还存在另一第二相移温度， 约为 700'C ; 当温度高于 700°C时， NiSi将转变为 NiSi2。 因此， 通常采用 300〜65(TC之间的退火温度来形成 MSi。 例如， 可以使用低于 500°C的退火温度， 退火时间少于 60秒。
又如， CoSi2通常采用两个阶段的快速退火处理来形成。在第一退火阶段中， 退火 温度约为 300〜650°C， 以形成 CoSi或 Co2Si。在第二退火阶段中， 退火温度高于 650°C， 以形成低电阻率的 CoSi2。
然后， 如图 4所示， 在衬底表面上沉积介电层 1009 (如 Si02)。 沉积厚度应足以埋 入突出的栅极部位。之后，例如通过化学机械抛光（CMP)工艺对所沉积的介电层 1009 进行抛光， 而掩蔽层 1006则充当抛光停止层。 也就是说， 进行 CMP， 直到露出了掩蔽 层 1006。 通过该处理， 使得介电层 1009的顶部与栅极区的顶部持平。
接下来， 如图 5所示， 在介电层 1009中与源 /漏极区相对应的部位中打孔， 从而形 成源 /漏极的接触孔 1010。 在此， 例如可以通过 RIE (反应离子刻蚀） 来进行打孔。 随后， 如图 6所示， 在所形成的接触孔 1010中填充多晶硅 1011。 具体地， 这例如 可以通过如下歩骤来进行。 首先， 在该结构的表面上沉积多晶硅层， 沉积的厚度应足 以填充所形成的接触孔 1010。 之后， 通过 CMP工艺对所沉积的多晶硅层迸行抛光， 同 样利用掩蔽层 1006作为抛光停止层。 也就是说， 进行 CMP， 直到露出了掩蔽层 1006。
然后， 如图 7所示， 去除掩蔽层 1006， 以露出栅电极 1004的上表面。 例如， 当掩 蔽层 1006为氮化硅时， 可以通过磷酸溶液来刻蚀掩蔽层 1006。 或者， 也可以通过 RIE 工艺， 来干法刻蚀掩蔽层 1006。
接着， 如图 8所示， 在图 7所示结构的上表面 （包括露出的栅电极的上表面） 上沉 积另一金属层 1012。 同样地， 该金属层 1012可以为 Ni、 Co、 Ti、 W等。 在一定的温度 下进行退火， 从而所沉积的金属层 1012与栅电极 1004中的多晶硅以及源 /漏极接触孔 1010中的多晶硅 1011发生反应， 以形成金属硅化物 1013和 1014。
为了避免在有源区中发生过多的硅化反应从而形成漏电流源， 先前形成的金属硅 化物层 1008优选地对于本次硅化反应应当具有阻挡作用。 也就是说， 金属硅化物层 1008优选地应当能够防止源 /漏极区在本次退火时发生二次硅化反应。
为此， 优选地， 本次退火处理中的温度不高于第一次退火处理时的温度。 因此， 本次退火处理不会影响到先前退火处理中形成的金属硅化物 1008层， 从而该金属硅化 物层 1008可以防止本次硅化反应蔓延到有源区中。 例如， 金属硅化物层 1008可以是通 过上述两阶段退火处理 （退火温度： 第一阶段 300〜65(TC， 第二阶段高于 650Ό ) 形 成的 CoSi2 ; 而金属层 1012则可以为 Ni， 对其在约 250°C的温度下进行退火， 从而形成 低电阻率的 NiSi。 当然， 本领域技术人员可以设想到多种金属材料及其退火处理温度 的组合， 以实现上述目的。 例如， 金属硅化物 1008可以是 Ni在约 500Ό的退火温度下 与 Si反应生成的 MSi; 而在对同样包括 Ni的金属层 1012进行退火时， 可采用约 400Ό的 退火温度， 从而同样形成 NiSi。
金属层 1012优选地应具有足够的厚度， 以便使得栅电极 1004中的多晶硅完全转变 为硅化金属。 此时， 源 /漏极区上的接触孔 1010中的多晶硅 1011可以全部硅化。 之后， 去除反应后的残留金属， 从而得到图 9所示的根据本发明实施例的半导体结构。
在此， 由于第二次硅化反应时的退火温度不高于第一次硅化反应， 从而在第二次 硅化反应时， 在源 /漏极区上形成硅化物层 1008可以防止这种硅化反应扩散到有源区 中， 从而避免了漏电流源的形成。 而且， 由于在接触孔 1010中的多晶硅也被完全硅化为硅化物 1014， 从而相当于将 源 /漏区 "延伸"到与栅极区等高。 这样， 随后在该器件上形成介电层， 且然后在该介 电层中与栅极、 源 /漏极相对应的区域例如通过 RIE形成接触孔时， 各个接触孔的深度 是一样的， 从而大大简化了工艺。
具体地， 参照附图 10， 在得到图 9所示的结构之后， 在该结构上沉积一介电层 1015
(例如， Si02 )。 然后， 分别在栅极、 源 /漏极区域相对应的位置形成接触孔 1016。 例 如， 接触孔 1016通过 RIE来形成。 然后在接触孔 1016中沉积金属如铝或铜， 来形成连 接线 1017。 由于在图 9所示的结构中， 栅极、 源 /漏极区域之间的高度是相等的， 因此 各个区域所对应的接触孔 1016的深度相同。 从而， 例如在刻蚀接触孔的 RIE工艺中， 可以方便地控制刻蚀条件。 这里， 仅在一个晶体管结构上示出了接触孔 1016、 连接线 1017， 但是也可以在其他晶体管结构上同样形成接触孔和连接线。
以上制造工艺可应用于各种不同类型的半导体器件， 且特别适用于亚微米互补金 属氧化物半导体 （CMOS )。 根据本发明的实施例， 首先在源 /漏极区上形成硅化物层 1008, 从而在随后形成栅极硅化物时， 不会影响到漏 /源极部位的有源区， 并因此提高 了半导体器件的可靠性。 此外， 根据本发明的优选实施例， 将栅极完全硅化， 从而可 以使栅电极的电阻充分降低。 而且， 通过在漏 /源区上形成硅化物 1014， 可以简化后续 工艺的复杂度。
上面的描述仅用于说明本发明的实施方式， 而并非要限制本发明的范围。 本领域 的技术人员应该理解， 本发明的范围 所附权利要求限定。 不脱离本发明的精神和原 理的任何修改或局部替换， 均应落入本发明的范围之内。

Claims

权 利 要 求
1.一种制造半导体器件的方法， 包括：
在半导体衬底中形成包括栅极、 源极和漏极区的晶体管结构；
执行第一硅化处理， 以在源极和漏极区上形成第一金属硅化物层；
在衬底上沉积第 ··介电层， 该第一介电层的顶部与栅极区的顶部持平； 在第一介电层中与源极和漏极区相对应的部位形成接触孔； 以及
执行第二硅化处理， 以在栅极区、 接触孔中形成第二金属硅化物，
其中， 第一金属硅化物层使得源极和漏极区避免在第二硅化处理时再次发生硅化 反应。
2. 如权利要求 1所述的方法， 其中，
执行第一硅化处理的步骤包括：
在衬底上沉积第一材料且进行退火， 使第一材料在源极和漏极区发生硅化反 应， 从而形成第一金属硅化物层； 以及，
执行第二硅化处理的歩骤包括：
在接触孔中注入多晶硅； 以及
在第一介电层上沉积第二材料且进行退火， 使第二材料在栅极区以及接触孔 中发生硅化反应， 从而形成第二金属硅化物，
其中， 选择第二硅化处理中的退火温度， 使得第二材料实质上不会与源极和漏极 区发生反应。
3. 如权利要求 2所述的方法， 其中， 第二硅化处理中的退火温度不高于第一硅化 处理中的温度。
4. 如权利要求 2所述的方法， 还包括：
在执行第一硅化处理之前， 在栅极区上形成掩蔽层， 以防止第一材料与栅极区发 生反应； 以及
在执行第二硅化处理之前， 去除该掩蔽层。
5. 如权利要求 4所述的方法， 其中， 在衬底上沉积第一介电层的歩骤包括： 在衬底上沉积第一介电层， 然后使用化学机械抛光对该第一介电层进行研磨， 直 至露出所述掩蔽层。
6. 如权利要求 4所述的方法， 其中， 在接触孔中注入多晶硅的步骤包括： 在衬底上沉积多晶硅层， 然后使用化学机械抛光对该多晶硅层进行研磨， 直至露 出所述掩蔽层。
7. 如权利要求 1所述的方法， 其中， 栅极区包括栅极绝缘层以及多晶硅层， 并且 在栅极绝缘层与多晶硅层之间形成有金属层。
8. 如权利要求 1所述的方法， 还包括：
在执行第二硅化处理之后， 在第一介电层上形成第二介电层， 在该第二介电层中 与栅极、 源极、 漏极区相对应的部位形成接触孔， 并在接触孔中沉积金属， 以形成连 接线。
9. 一种半导体器件， 包括：
半导体衬底；
在该半导体衬底中形成的晶体管结构，所述晶体管结构包括栅极、源极和漏极区； 在源极和漏极区上形成的第一金属硅化物层；
在半导体衬底上形成的第一介电层， 该第一介电层的顶部与栅极区的顶部持平； 在第一介电层中与源极和漏极区相对应的部位中形成的接触孔； 以及
在接触孔和栅极区中形成的第二金属硅化物，
其中， 第一金属硅化物层使得源极和漏极区避免在形成第二金属硅化物的过程中 再次发生硅化反应。
10. 如权利要求 9所述的半导体器件， 其中， 第一金属硅化物层在第一退火温度 下形成， 第二金属硅化物在不高于第一退火温度的第二退火温度下形成。
11. 如权利要求 9所述的半导体器件， 其中， 栅极区包括依次形成的栅极绝缘层、 金属层以及多晶硅层。
12. 如权利要求 9所述的半导体器件， 还包括：
在第一介电层上形成的第二介电层；
在第二介电层中与栅极、 源极、 漏极区相对应的部位形成的接触孔； 以及 在接触孔中形成的连接线。
PCT/CN2010/074620 2009-11-24 2010-06-28 半导体器件及其制造方法 WO2011063650A1 (zh)

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