CN101093816A - 完全金属硅化栅极与无金属硅化电阻与其制备方法 - Google Patents

完全金属硅化栅极与无金属硅化电阻与其制备方法 Download PDF

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CN101093816A
CN101093816A CNA2006100574980A CN200610057498A CN101093816A CN 101093816 A CN101093816 A CN 101093816A CN A2006100574980 A CNA2006100574980 A CN A2006100574980A CN 200610057498 A CN200610057498 A CN 200610057498A CN 101093816 A CN101093816 A CN 101093816A
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metal
resistance
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silication
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丁煜明
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种完全金属硅化栅极与无金属硅化电阻与其制备方法。图案化栅极与电阻的半导体材料后，以第一介电层保护多晶硅免于金属硅化，接着进行第一次金属硅化将晶体管的栅极部分金属硅化。厚层栅极则以第二介电层保护电阻免于金属硅化，接着进行第二次金属硅化使栅极完全金属硅化。

Description

完全金属硅化栅极与无金属硅化电阻与其制备方法
技术领域
本发明有关于集成电路与其制备方法，更特别关于完全金属硅化栅极与无金属硅化电阻的制备方法。
背景技术
随着技术进步，集成电路(以下简称IC)设计变得更复杂。为了增加性能与降低成本，改善IC的结构设计与制程为主要重点。举例来说，这需减少栅极氧化物厚度以提高栅极电容，以及缩小晶体管沟道的长度以维持栅极的沟道控制。掺杂多晶硅栅极中，掺杂物有限的溶解度会限制栅极的电阻下限，并于栅极/氧化物界面形成缺乏带电载流子的有限厚度空间电荷层。该绝缘多晶空乏层将增加有效氧化层厚度，降低栅极电容并多方面限制元件尺寸。
若以金属栅极代替多晶硅栅极，高载流子浓度的金属可解决多晶空乏的问题。然而金属栅极的问题包括蚀刻制程，热预算限制以及金属污染。将金属合金于已知图案化后的多晶硅栅极，以形成完全金属硅化栅极的方法格外引人注目。已知IC制程已倚重单一金属硅化制程制造多晶栅极与漏极/源极的接触面，因此整合完全金属硅化栅极制程只需极少改良。
已知IC制程中，于植入与退火漏极/源极后，沉积介电层前，会形成漏极/源极与栅极的金属硅化接触面。全面式溅镀沉积金属薄膜后的热制程可使金属与晶圆上露出的硅区域反应，形成源极/漏极与栅极的金属硅化接触面。为避免接点漏电，需缩小金属硅化接触面的深度，而一般多晶硅栅极的厚度大于漏极/源极与栅极的金属硅化接触面深度，在考虑到金属硅化接触面深度后，只金属硅化栅极上面的一部分。接着以湿式蚀刻去除未反应的多余金属，包括沉积于介电侧壁物与绝缘层上的金属。由于只有露出硅的区域被反应，所以为自我对准制程，且常被称作自对准金属硅化制程。
对于完全金属硅化栅极制程而言，主要的改良重点在于完全金属硅化栅极后，还能保持漏极/源极金属硅化接触面的浅度。方法是分开处理漏极/源极的金属硅化与栅极的完全金属硅化，于已知金属硅化后，另外将栅极单独地金属硅化。先用全区式介电层沉积以保护漏极/源极，并回磨至栅极露出为止，之后进行的第二次金属硅化便可避免过度金属硅化漏极/源极。
已知IC制程中，相同掺杂多晶硅层除了形成栅极外，也可形成多晶硅电阻。金属硅化的多晶硅电阻比无金属硅化掺杂的多晶硅电阻低，为维持一特定电阻值，应使用无金属硅化的掺杂多晶硅为电阻。已知IC制程为避免金属硅化该多晶硅电阻，于掺杂漏极/源极后，先图案化额外的介电层再进行金属硅化制程。在完全金属硅化制程中，因为有两步金属硅化，必需进行额外制程以避免多晶硅电阻被金属硅化。
发明内容
本发明有关于一种完全金属硅化栅极与无金属硅化电阻的制备方法，当栅极厚度小于500埃时，包括以半导体材料形成至少一栅极与一电阻；形成一第一介电层以覆盖该电阻；进行一金属硅化制程，至少金属硅化部分该栅极且不金属硅化该电阻。当栅极厚度大于500埃时，更包括于前述制程后形成第二介电层以覆盖该电阻，并进行第二金属硅化制程以完全金属硅化该栅极。
本发明所述的完全金属硅化栅极与无金属硅化电阻的制备方法，该栅极的厚度小于500埃。
本发明所述的完全金属硅化栅极与无金属硅化电阻的制备方法，该半导体材料为多晶或非晶的半导体材料。
本发明所述的完全金属硅化栅极与无金属硅化电阻的制备方法，该第一金属化制程更包括将一金属层设置于栅极上；以及进行高温制程使90％以上的该栅极金属硅化。
本发明所述的完全金属硅化栅极与无金属硅化电阻的制备方法，形成该第二介电层之前，更包括：形成一层间介电层覆盖该电阻以及栅极；以及移除部分该层间介电层与部分该第一介电层，直至露出该电阻与该栅极。
本发明所述的完全金属硅化栅极与无金属硅化电阻的制备方法，更包括形成一绝缘结构于半导体基板中，且该电阻设置于该绝缘结构上。
本发明所述的完全金属硅化栅极与无金属硅化电阻的制备方法，该第一或第二金属硅化制程更包括设置一金属层于该栅极上，进行一高温制程形成金属硅化层于栅极上；于该第二金属硅化制程后该栅极至少有90％以上金属硅化。
本发明所述的完全金属硅化栅极与无金属硅化电阻的制备方法，该第一或第二介电层包括氧化硅，或含氮介电材料。
本发明更提供一种完全金属硅化栅极与无金属硅化电阻，包括一电阻，置于一半导体基板上，其中该电阻无金属硅化；以及一栅极，置于一半导体基板上且完全金属硅化。
本发明所述的完全金属硅化栅极与无金属硅化电阻，该半体体的材料包括多晶硅、非晶硅、或硅/锗合金。
本发明所述的完全金属硅化栅极与无金属硅化电阻，该金属硅化栅极包括镍、钴、钨、铂、锆、钛、或锗硅化物的金属硅化物。
本发明所述的完全金属硅化栅极与无金属硅化电阻，更包括形成一绝缘结构于半导体基板中，该电阻设置于该绝缘结构上，该栅极设置于该半导体基板上。
附图说明
图1A～1E是本发明第一实施例中，半导体结构的部分剖视图，图示薄层多晶栅极晶体管的制程。
图2A～2G是本发明第二实施例中，半导体结构的部分剖视图，图示厚层多晶栅极晶体管的制程，与其所需的额外步骤。
图3是本发明第一实施例与第二实施例的制程流程图。
具体实施方式
下述具体实施例配合附图可清楚地说明本发明的优点，以及本发明中操作方法与结构。
本发明提供下述两个实施例，可同时制造无金属硅化电阻(多晶或非晶)与金属硅化的MOSFET。MOSFET基板上，包括部分金属硅化源极/漏极，与完全金属硅化栅极。沉积金属层时为避免金属硅化电阻，需要一介电阻挡层(一般为氧化物)以阻挡金属接触电阻的多晶硅或非晶硅材料。
图1A～1E为本发明第一实施例中，制造薄层多晶栅极晶体管的制程部分剖视图。所谓的薄层多晶栅极是指500埃(Angstrom，以下简称埃)以下。图1A为本发明第一实施例的部分剖视图100。剖视图100包括金属氧化物半导体晶体管102与多晶电阻104，均有侧壁间隔物106。金属氧化物半导体晶体管102设置于半导体基板107上。多晶电阻104可为掺杂或非掺杂。金属氧化物半导体晶体管102包括沉积于栅极介电层109(较佳为热成长氧化物)上的多晶栅极108；还包括一源极110与一漏极112。多晶电阻104下的绝缘结构113可为硅的浅槽绝缘(以下简称STI)或部分氧化。必需了解的是源极110与漏极112的位置可对调。
图1B为本发明第一实施例的部分剖视图114。第一介电层116沉积于多晶栅极108与多晶电阻104上。第一介电层116的组成可为一种以上的预定氧化物，作为金属硅化的阻挡层。
图1C为本发明第一实施例中部分剖视图118。以蚀刻(实施例为湿式蚀刻)将多晶栅极108、源极110与漏极112上的第一介电层116移除。注意第一介电层116仍保留于多晶电阻104上。
图1D为本发明第一实施例的部分剖视图120。第一金属层122沉积于多晶栅极108、源极110与漏极112，以及保护多晶电阻104的第一介电层116上。
图1E为本发明第一实施例中的部分剖视图124。高温制程将第一金属层122，与多晶栅极108、源极110与漏极112上露出的硅反应。结果形成完全金属硅化薄层多晶栅极126，金属硅化源极128与金属硅化漏极130。第一介电层116保护多晶电阻104免于金属硅化。此外，此步骤还移除未金属硅化的金属。
图2A～2G是本发明第二实施例中，为制造厚层多晶栅极晶体管所需制程的部分剖视图。所谓厚层多晶栅极即厚度超过500埃。图2A是本发明第二实施例的部分剖视图200。剖视图200的结构依据图1A～1D的制程所得，但多晶栅极较厚。该剖视图200包括金属氧化物半导体晶体管202与多晶电阻204，均有侧壁间隔物206。金属氧化物半导体晶体管202设置于半导体基板207上。金属氧化物半导体晶体管202包括沉积于栅极介电层209上的厚层多晶栅极208；还包括一源极210与一漏极212。以第一介电层214保护硅的STI或部分氧化所形成的绝缘结构213上多晶电阻204。
第一次金属硅化后，形成厚层多晶栅极208的上层金属硅化部分216，金属硅化源极218与金属硅化漏极220。图1E与图2A均为金属硅化制程，但图2A中厚层多晶栅极208变成金属硅化物的比例较少。
图2B为本发明第二实施例的部分剖视图222。首先沉积一层间介电层224。此阶段必需了解虽只部分金属硅化厚层多晶栅极上层，但金属氧化物半导体晶体管202的源极210与漏极212已充分金属硅化为金属硅化源极218与金属硅化漏极220。第一介电层214可保护多晶电阻204不受本制程影响。
图2C为本发明第二实施例的部分剖视图226。以例如化学机械研磨的平坦化制程处理层间介电层224，直到露出上层金属硅化部分216与多晶电阻204为止。
图2D为本发明第二实施例中的部分剖视图228。沉积第二介电层230于上层金属硅化部分216与多晶电阻204上。第二介电层230为有效金属硅化阻挡层(一般为氧化物)，以避免金属层沉积时接触电阻体的多晶硅或非晶硅。
图2E为本发明第二实施例中的部分剖视图232。蚀刻上层金属硅化部分216上的第二介电层230，保留多晶电阻204上的第二介电层230以保护电阻。
图2F为本发明第二实施例中的部分剖视图234。沉积第二金属层236于上层金属硅化部分216与保留的第二介电层230上。值得注意的是第二金属层并不接触多晶电阻204、金属硅化源极218、或金属硅化漏极220。
图2G为本发明第二实施例的部分剖视图238。第二次高温制程将第二金属层236与上层金属硅化部分216反应，并形成完全金属硅化厚层多晶栅极240。金属硅化90％以上的厚层多晶栅极208与栅极介电层209的界面，应已完全金属硅化多晶栅极。同时层间介电层224保护金属硅化源极218与金属硅化漏极220，第二介电层230保护多晶电阻，以免金属硅化于第二次合金制程。此外移除层间介电层224与第二介电层上未反应的金属。此第二金属硅化过程(图2B～2G)将部分金属硅化栅极(图2A)完全金属硅化。
图3显示本发明实施例的制造过程流程图。302为图1B的制程，沉积介电层116。304为图1C的制程，蚀刻金属氧化物半导体晶体管102上的介电层116。306为图1D的制程，第一金属层122沉积于多晶栅极108、源极110与漏极112上。308为图1E的制程，第一金属层122于高温制程可形成完全金属硅化薄层多晶栅极126，金属硅化源极128，与金属硅化漏极130。310为考虑栅极元件厚薄的步骤，若为薄层多晶栅极则结束流程，若为厚层多晶栅极(厚度超过500埃)，则继续图2A的制程312，沉积层间介电层224。314为图2C的制程，以化学机械研磨使层间介电层224平坦化，直到露出上层金属硅化部分216与多晶电阻204为止。316为图2D的制程，沉积一第二介电层230于上层金属硅化部分216与多晶电阻204上。318为图2E的制程，蚀刻第二介电层230直至露出上层金属硅化部分216为止。320为图2F的制程，沉积第二金属层236于上层金属硅化部分216与保留的第二介电质230上。322为图2G的制程，第二金属层236于第二次高温制程将形成完全金属硅化厚层多晶栅极240。蚀刻移除多余的金属后，则完成一厚层多晶栅极晶体管元件。
半导体基板可为硅，硅锗合金或锗。半导体基板可为基体基板或绝缘层上半导体基板。栅极介电层可为二氧化硅，含氮的氧化硅，或介电常数大于4的材料。金属硅化的金属可由下述金属与硅基板或多晶硅合金制成：钴，镍，钴/镍，钨，铂，锆，或钛。电阻材料可为多晶硅，非晶硅或硅/锗合金(非栅极结构使用的金属硅化物)。侧壁间隔物可由下述物质形成：二氧化硅，含氮介电层或两者的组合。金属硅化阻挡层可由介电材料形成，如二氧化硅，氮化硅，含氮介电质或类似材料。
虽然本发明已通过较佳实施例说明如上，但该较佳实施例并非用以限定本发明。本领域的技术人员，在不脱离本发明的精神和范围内，应有能力对该较佳实施例做出各种更改和补充，因此本发明的保护范围以权利要求书的范围为准。
附图中符号的简单说明如下：
100、114、118、120、124：本发明第一实施例的部分剖视图
102：金属氧化物半导体晶体管
104：多晶电阻
106：侧壁间隔物
107：半导体基板
108：多晶栅极
109：栅极介电层
110：源极
112：漏极
113：绝缘结构
116：第一介电层
122：第一金属层
126：完全金属硅化薄层多晶栅极
128：金属硅化源极
130：金属硅化漏极
200、222、226、228：本发明第二实施例的部分剖视图
232、234、238：本发明第二实施例的部分剖视图
202：金属氧化物半导体晶体管
204：多晶电阻
206：侧壁间隔物
208：厚层多晶栅极
207：半导体基板
209：栅极介电层
210：源极
212：漏极
213：绝缘结构
214：第一介电层
216：上层金属硅化部分
218：金属硅化源极
220：金属硅化漏极
224：层间介电层
230：第二介电层
236：第二金属层
240：完全金属硅化的厚层多晶栅极
300：本发明实施例的制程流程图
302：图1B的制程
304：图1C的制程
306：图1D的制程
308：图1E的制程
310：考虑多晶栅极厚薄的步骤
312：图2B的制程
314：图2C的制程
316：图2D的制程
318：图2E的制程
320：图2F的制程
322：图2G的制程

Claims (13)

1.一种完全金属硅化栅极与无金属硅化电阻的制备方法，其特征在于，该方法包括：
以半导体材料形成至少一栅极与一电阻；
形成一第一介电层以覆盖该电阻；以及
进行第一金属硅化制程，至少金属硅化部分该栅极且不金属硅化该电阻。
2.根据权利要求1所述的完全金属硅化栅极与无金属硅化电阻的制备方法，其特征在于，该栅极的厚度小于500埃。
3.根据权利要求1所述的完全金属硅化栅极与无金属硅化电阻的制备方法，其特征在于，该半导体材料为多晶或非晶的半导体材料。
4.根据权利要求1所述的完全金属硅化栅极与无金属硅化电阻的制备方法，其特征在于，该第一金属化制程更包括将一金属层设置于栅极上；以及进行高温制程使90％以上的该栅极金属硅化。
5.根据权利要求1所述的完全金属硅化栅极与无金属硅化电阻的制备方法，其特征在于，该栅极厚度大于500埃且更包括形成第二介电层以覆盖该电阻，以及进行第二金属硅化制程以完全金属硅化该栅极。
6.根据权利要求5所述的完全金属硅化栅极与无金属硅化电阻的制备方法，其特征在于，形成该第二介电层之前，更包括：
形成一层间介电层覆盖该电阻以及栅极；以及
移除部分该层间介电层与部分该第一介电层，直至露出该电阻与该栅极。
7.根据权利要求5所述的完全金属硅化栅极与无金属硅化电阻的制备方法，其特征在于，更包括形成一绝缘结构于半导体基板中，且该电阻设置于该绝缘结构上。
8.根据权利要求5所述的完全金属硅化栅极与无金属硅化电阻的制备方法，其特征在于，该第一或第二金属硅化制程更包括设置一金属层于该栅极上，进行一高温制程形成金属硅化层于栅极上；于该第二金属硅化制程后该栅极至少有90％以上金属硅化。
9.根据权利要求5所述的完全金属硅化栅极与无金属硅化电阻的制备方法，其特征在于，该第一或第二介电层包括氧化硅，或含氮介电材料。
10.一种完全金属硅化栅极与无金属硅化电阻，其特征在于，该完全金属硅化栅极与无金属硅化电阻包括：
一电阻，置于一半导体基板上，其中该电阻无金属硅化；以及
一栅极，置于一半导体基板上且至少有90％以上金属硅化。
11.根据权利要求10所述的完全金属硅化栅极与无金属硅化电阻，其特征在于，该半体体的材料包括多晶硅、非晶硅、或硅/锗合金。
12.根据权利要求10所述的完全金属硅化栅极与无金属硅化电阻，其特征在于，该金属硅化栅极包括镍、钴、钨、铂、锆、钛、或锗硅化物的金属硅化物。
13.根据权利要求10所述的完全金属硅化栅极与无金属硅化电阻，其特征在于，更包括形成一绝缘结构于半导体基板中，该电阻设置于该绝缘结构上，该栅极设置于该半导体基板上。
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