TWI326899B - Method for forming fully silicided gate electrodes and unsilicided poly resistor - Google Patents

Method for forming fully silicided gate electrodes and unsilicided poly resistor Download PDF

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TWI326899B
TWI326899B TW095108952A TW95108952A TWI326899B TW I326899 B TWI326899 B TW I326899B TW 095108952 A TW095108952 A TW 095108952A TW 95108952 A TW95108952 A TW 95108952A TW I326899 B TWI326899 B TW I326899B
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metal
gate
resistor
free
semiconductor substrate
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TW095108952A
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TW200727366A (en
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Ming Ting Steve
Chih Hao Wang
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Taiwan Semiconductor Mfg
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H01L29/4975—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 being a silicide layer, e.g. TiSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

1326899 '九、發明說明： 【發明所屬之技術領域】 本發明係有關於積體電路與其製備方法，更特別關 於完全金屬矽化閘極與無金屬矽化電阻之製備方法。 【先前技術】 隨著技術進步，積體電路（以下簡稱ic)設計變得更 複雜。為了增加性能與降低成本，改善1C之結構設計與 製程為主要重點。舉例來說，這需減少閘極氧化物厚度 以提高閘極電容，以及縮小電晶體通道之長度以維持閘 極之通道控制。掺雜多晶矽閘極中，掺雜物有限的溶解 度會限制閘極的電阻下限，並於閘極/氧化物界面形成缺 乏帶電載子之有限厚度空間電荷層。該絕緣多晶空乏層 將增加有效氧化層厚度，降低閘極電容並多方面限制元 件尺寸。 若以金屬閘極代替多晶矽閘極，高載子濃度之金屬 可解決多晶空乏的問題。然而金屬閘極的問題包括蝕刻 製程，熱預算限制以及金屬污染。將金屬合金於習知圖 案化後之多晶矽閘極，以形成完全金屬矽化閘極之方法 格外引人注目。習知1C製程已倚重單一金屬矽化製程製 造多晶閘極與汲極/源極之接觸面，因此整合完全金屬矽 化閘極製程只需極少改良。 習知1C製程中，於植入與退火汲極/源極後，沉積介 電層前，會形成汲極/源極與閘極的金屬矽化接觸面。全 0503-A30970TWF/bsuhuche 5 1326899 沉積金屬薄膜後之熱製程可使金屬與晶圓上露 之石夕區域反應’形成源極/汲極與閘極之金屬魏接觸 。為避免接點漏電，需縮小金屬耗接觸面之深度， =般以㈣極之厚度大於汲極m極與閘極的金屬石夕 =接觸面深度，在考慮到金屬魏接觸面深度後，只金 之石閘：上面的一部份。接著以溼式蝕刻去除未反應 屬夕 '金，包括沉積於介電側壁物與絕緣層上之： 屬。由於只有露出石夕的區域被反應， 制 程，且常被稱作自對準金屬石夕化製程。 我對丰衣 對於完全金屬魏_製程而言， 在於完全金屬石夕化間極後’還 ☆文良重點 =”度。方法是分開處理汲 ：【： 間極的完全金屬石夕化 夕化舁 單獨地金屬石夕化。先用全區式介金電 伴另f外將閉極 極，並回磨至間極露出為止，；源 化便可避免過度金屬石夕化汲極/源極。$一:人金屬石夕 白去1C製程中，相同掺雜多晶 外，亦可形❹㈣電阻。金切 1 了形成閘極 ，化接雜之多晶彻低，為维：:=阻比無 應使用無金屬魏之掺雜多晶 2 “電阻值， 避免金屬石夕化該多晶石夕電阻，於挨=知κ製程為 案化額外的介電層再進行金屬石夕f匕^極=極後，先圖 化製程中’因為有兩步金屬魏，必:在元全金屬石夕 避免多晶梦電阻被金屬魏。 雨進仃額外製程以 0503-A30970TWF/hsuhuch, 6 1326899 【發明内容】 本發明係有關於一種完全金屬矽化閘極與無金屬矽 化電阻之製備方法，當閘極厚度小於500埃時，包括以 半導體材料形成至少一閘極與一電阻；形成一介電層以 覆蓋該電阻；進行一金屬矽化製程，至少金屬矽化部份 該閘極且不金屬矽化該電阻。當閘極厚度大於500埃時， 更包括於前述製程後形成第二介電層以覆蓋該電阻，並 進行第二金屬矽化製程以完全金屬矽化該閘極。本發明 更提供一種完全金屬矽化閘極與無金屬矽化電阻，包括 一電阻，置於一半導體基板上，其中該電阻無金屬矽化； 以及一閘極，置於一半導體基板上且完全金屬矽化。 下述具體實施例配合圖式可清楚說明本發明之優 點，以及本發明中操作方法與結構。 【實施方式】 本發明提供下述兩實施例，可同時製造無金屬矽化 電阻（多晶或非晶）與金屬矽化之MOSFET°MOSFET基板 上，包括部份金屬矽化源極/汲極，與完全金屬矽化閘極。 沉積金屬層時為避免金屬矽化電阻，需要一介電阻擋層 (一般為氧化物）以阻擋金屬接觸電阻的多晶矽或非晶矽 材料。 第1A〜1E圖為本發明第一實施例中，製造薄層多晶 閘極電晶體之製程部份剖視圖。所謂的薄層多晶閘極意 指500埃（Angstrom，以下簡稱埃）以下。第1A圖為本發 明第一實施例之部份剖視圖1〇〇。剖視圖100包括金氧半 0503-A30970TWF/hsuhuche 7 半=102與多晶電11 且104，均有側壁間隔物106。金氧 可體102叹置於半導體基板107上。多晶電阻104 介雷^雜或非掺雜。金氧半電晶體102包括沉積於問極 枯胃109(較佳為熱成長氧化物）上之多晶閑極⑽；亦 原極11G與—汲極112。絕緣結構113丨之多晶電 〇石夕之淺槽絕緣（以下簡稱 了解的是源請與汲極⑴的位置可對調 —八第1B圖為本發明第—實施例之部份剖視圖114。第 ”電層116 >儿積於多晶問極1〇8與多晶電阻刚上。 ^ 116之組成可為一種以上之預定氧化物，作 為金屬石夕化之阻擋層。 ^1C圖為本發明第一實施例中部份剖視圖118。以 〆’（貫施例為濕式钱刻）將多晶閑極108、源極m 極m上之第一介電層116移除。 仍保留於多晶電阻104上。 电貝 第1D圖為本發明第一實施例之部份剖視圖12〇。第 、金屬層122 /儿積於多晶閘極1〇8、源極與没極112， 以及保護多晶電阻1〇4之第一介電層ιΐ6上。 ▲ f 1E圖為本發明第—實施例中之部份剖視圖124。 南溫製程將第一金屬層122，與多晶間極ι〇8、源極ιι〇 露出之石夕反應。結果形成完全金屬石夕化薄 二夕I入丄 屬石夕化源極128與金屬石夕化汲極 ⑽。弟-介電層116保護多晶電阻1〇4免於金屬石夕化。 此外，此步驟亦移除未金屬魏之金屬。 0503^A30970TWF/hsuhuche 1326899 第2A〜2G圖係本發明第二實施例中，為製造厚層多 晶閘極電晶體所需製程之部份剖視圖。所謂厚層多晶閘 極即厚度超過500埃。第2A圖係本發明第二實施例之部 份剖視圖200。剖視圖200之結構係依據第1A〜1D之製 程所得，但多晶閘極較厚。該剖視圖200包括金氧半電 晶體202與多晶電阻204，均有側壁間隔物206。金氧半 電晶體202設置於半導體基板207上。金氧半電晶體202 包括沉積於閘極介電層209上之厚層多晶閘極208 ;亦包 括一源極210與一汲極212。以第一介電層214保護矽之 STI或部份氧化所形成之絕緣結構213上多晶電阻204。 第一次金屬梦化後’形成厚層多晶閘極208之上層 金屬矽化部份216,金屬矽化源極218與金屬矽化汲極 220。第1E圖與第2A圖均為金屬矽化製程，但第2A圖 中厚層多晶閘極208變成金屬矽化物之比例較少。 第2B圖為本發明第二實施例之部份剖視圖222。首 先沉積一層間介電層224。此階段必需了解雖只部份金屬 矽化厚層多晶閘極上層，但金氧半電晶體202之源極210 與汲極212已充份金屬矽化為金屬矽化源極218與金屬 矽化汲極220。第一介電層214可保護多晶電阻204不受 本製程影響。 第2C圖為本發明第二實施例之部份剖視圖226。以 例如化學機械研磨之平坦化製程處理層間介電層224,直 到露出上層金屬石夕化部份216與多晶電阻204為止。 第2D圖為本發明第二實施例中之部份剖視圖228。 0503-A30970TWF/hsuhuche 9 1326899 ’=:介!層上3。於上層金屬秒化部份216與多晶電 或" ）丨電層230為有效金屬石夕化阻擋層（-般 化物)，以避免金屬層沉積時接觸電阻體之 或 非晶石夕。 射ί 圖Μ為本發明第二實施例中之部份剖視圖232。 #刻上層金屬石夕化部份216上之第二介電層23〇，保留多 晶電阻2G4上之第二介電層23Q以保護電阻。 第2F圖為本發明第二實施例中之部份剖視圖w。 Ϊ積第二金屬層236於上層金屬錢部份216與保留之 ，二电層230 _L。值得注意的是第二金屬層並不接觸 0曰笔阻2〇4、金屬石夕化源極218、或金屬石夕化沒極22〇。 第犯圖為本發明第二實施例之部份剖視圖㈣。第 -=溫製程將第二金屬層236與上層金屬魏部份216 反應’亚形成完全金屬石夕化厚層多晶間極24〇。金屬石夕化 90%=上的厚層多晶閘極2〇8與閑極介電層之界面， 應已完全金切化多晶㈣。同時層 源…金輪一 保5蔓夕日日電阻，以免今®石々外认哲 兄隹屬矽化於苐二次合金製程。此外 ^除層^介電層224與第二介電層上未反應之金屬。此 弟二金屬^化過程（第2B〜2G圖）將部份金屬石夕化閘極 (第2A圖）元全金屬發化。 第3圖顯示本發明實施例之製造過程流程圖。搬為 B圖之襄知，’儿積介電層116。3()4為第…圖之製程， 钱刻金氧半電晶體102上之介電層Π6。遍為第10圖 0503-A30970TWF/hsuhuch( 10 1326899 之製程，第一金屬層122沉積於多晶閘極108、源極110 與汲極112上。308為第1E圖之製程，第一金屬層122 於高溫製程可形成完全金屬矽化薄層多晶閘極126,金屬 矽化源極128，與金屬矽化汲極130。310為考慮閘極元 件厚薄之步驟，若為薄層多晶閘極則結束流程，若為厚 層多晶閘極（厚度超過500埃），則繼續第2A圖之製程 312，沉積層間介電層224。314為第2C圖之製程，以化 學機械研磨使層間介電層224平坦化，直到露出上層金 屬矽化部份216與多晶電阻204為止。316為第2D圖之 製程，沉積一第二介電層230於上層金屬矽化部份216 與多晶電阻204上。318為第2E圖之製程，蝕刻第二介 電層230直至露出上層金屬矽化部份216為止。320為第 2F圖之製程，沉積第二金屬層236於上層金屬矽化部份 216與保留之第二介電質230上。322為第2G圖之製程， 第二金屬層236於第二次高溫製程將形成完全金屬矽化 厚層多晶閘極208。蝕刻移除多餘之金屬後，則完成一厚 層多晶閘極電晶體元件。 半導體基板可為矽，矽鍺合金或鍺。半導體基板可 為基體基板或絕緣層上半導體基板。閘極介電層可為二 氧化矽，含氮之氧化矽，或介電常數大於4之材料。金 屬矽化之金屬可由下述金屬與矽基板或多晶矽合金製 成：銘，鎳，銘/鎳，鎢，銘，錄，或鈦。電阻材料可為 多晶矽，非晶矽或矽/鍺合金（非閘極結構使用之金屬矽化 物）。側壁間隔物可由下述物質形成：二氧化矽，含氮介 0503-A30970TWF/hsuhuche 11 1326899 、 電層或兩者的組合。金屬矽化阻擋層可由介電材料形 成，如二氧化矽，氮化矽，含氮介電質或類似材料。 雖然本發明已以數個較佳實施例揭露如上，然其並 非用以限定本發明，任何熟習此技藝者，在不脫離本發 明之精神和範圍内，當可作任意之更動與潤飾，因此本 發明之保護範圍當視後附之申請專利範圍所界定者為 準。 0503-A30970TWF/hsuhuche 12 1326899 '【圖式簡單說明】 第1A〜1E圖：本發明苐一實施例中，半導體結構之部 份剖視圖，圖示薄層多晶閘極電晶體之製程。 第2A〜2G圖：本發明第二實施例中，半導體結構之部 份剖視圖，圖示厚層多晶閘極電晶體之製程，與其所需 之額外步驟。 第3圖：本發明第一實施例與第二實施例之製程流程 圖。 【主要元件符號說明】 100、114、118、120、124〜本發明第一實施例之部 分剖視圖； 104〜多晶電阻； 107〜半導體基板； 109〜閘極介電層； 112〜汲極； 116〜第一介電層； ' 102〜金氧半電晶體； 106〜側壁間隔物； 108〜多晶閘極； 110〜源極； • 113〜絕緣結構； 122〜第一金屬層； 12 6〜完全金屬石夕化薄層多晶閘極； 128〜金屬矽化源極； 130〜金屬矽化汲極； 200、222、226、228、232、234、238〜本發明第二 實施例之部分剖視圖； 202〜金氧半電晶體； 204〜多晶電阻； 206〜側壁間隔物； 208〜厚層多晶閘極； 0503-A30970TWF/hsuhuche 13 1326899 209〜閘極介電層； 212〜汲極； 214〜第一介電層； 218〜金屬矽化源極； 224〜層間介電層； 236〜第二金屬層； 207~半導體基板； 210〜源極； 213〜絕緣結構； 216~上層金屬梦化部份； 220〜金屬矽化汲極； 230〜第二介電層； 240〜完全金屬矽化之厚層多晶閘極； 300~本發明實施例之製程流程圖； 302〜第1B圖之製程； 304〜第1C圖之製程； 306〜第1D圖之製程； 308〜第1E圖之製程； 310〜考慮多晶閘極厚薄之步驟； 312〜第2B圖之製程； 314〜第2C圖之製程； 316〜第2D圖之製程； 318〜第2丑圖之製程； 320〜第2F圖之製程； 322〜第2G圖之製程。 0503-A30970TWF/hsuhuche 14

Claims (1)

1326899 修正日期：99.5.3 第95108952號申請專利範圍修正本 十、申請專利範圍： 1. 一種完全金屬矽化閘極與無金屬矽化電阻之製備 方法，包括： 以半導體材料形成至少一厚度大於500埃之閘極、 一源極/汲極、與一電阻於一半導體基板； 形成第一介電層以覆蓋該電阻； 進行第一金屬矽化製程，金屬矽化部份該閘極與部 份該源極/汲極，且不金屬矽化該電阻； 形成第二介電層以覆蓋該電阻與部份金屬矽化之該 源極/汲極；以及 進行第二金屬矽化製程以完全金屬矽化該閘極。 2. 如申請專利範圍第1項所述之完全金屬矽化閘極 與無金屬矽化電阻之製備方法，其中形成該第二介電層 之前，更包括： 形成一層間介電層覆蓋該電阻、該源極/汲極、以及 閘極；以及 移除部份該層間介電層與部份該第一介電層，直至 露出該電阻與該閘極。 3. 如申請專利範圍第1項所述之完全金屬矽化閘極 與無金屬矽化電阻之製備方法，其中該半導體基板為一 基體基板。 4. 如申請專利範圍第1項所述之完全金屬矽化閘極 與無金屬矽化電阻之製備方法，其中該半導體基板為一 絕緣層上半導體基板。 0503-A30970丁 WF!/hsuhuche 15 丄 第95聊52號申請專利範圍修正本 修正日期：99.5.3 與無金屬矽化電阻之制、所述之完全金屬矽化閘極 料包括石夕，錯，或石夕^ =法’其中該半導體基板之材 前，更包括形成—二:備/法’其中在形成該問極之 7如申：U極介電層於半導體基板上。 “人/明專範圍第6項所述之完全全屬碎化門極 與無金屬石夕化電阻之製借h 金屬夕化閘極 成包括氧化石夕，含氮之μ、’其中該閘極介電層之組 何材料。 乳化石夕’或介電常數大於4之任 8‘如申請專利範圍第 與無金屬魏電阻之製 、β之完全金屬耗閘極 於半導體基板中。、、’更包括形成-絕緣結構 9.如申請專利節圍笛2 = 盥盔全屬t 項所述之完全金屬矽化閘極 緣結構上。 ’其中該電阻設置於該絕 ]〇.如申請專利範圍筮s 與無金屬石夕化電阻之製備、斤^完全金屬石夕化問極 導體基板上。 ，其中该閘極設置於該半 與無電專所述之完全金屬·極 多晶梦，非晶石夕其中該半導趙材料包括 12.如申請專利節 與無金屬發化電阻之製備方法所==屬:夕化閘極 疋更包括形成一個以上之 0503-A30970TWF 丨/hsuhuche 第95108952號申請專利範圍修正本 間隔物，覆蓋該閘修正曰期U 这電阻之側壁。 13. 如申請專利範 土 極盥益金屬;固弟12項所述之完全金屬矽化閘 包括氧化石夕或含氮介電材料。其中該間隔物之組成 14. 如申請專利範圚 與無金屬石夕化電阻之製備方^述之'全金屬魏閘極 矽化製程更包括嘹置—全其中該第-或第二金屬 製程形成金屬魏層極上；進行一高温 極乂5.:::C第14項所述之完全金屬梦化閘 鎳m錯、鈦:二今；中：金屬層包括 义上述金屬之合金。 16.如巾請專·圍第^ 與無金屬矽化電阻之製備方法廿疋王金屬石夕化閘極 層包括氧化石夕。衣備其中該第一或第二介電 極盘申請專利範圍第1項所述之完全金屬石夕化間 勺把入―人 衣備方法’其中該第-或第二介 包層包括含氮介電材料。 二-種完全金屬石夕化閉極與無金屬石夕化電阻，包括： 矽化； 基板上，其中該電阻無金屬 -源極/汲極，置於—半導體基板上， 汲極部份金屬矽化；以及 中該源極/ 一厚度大於500埃之間搞，里从 完全金屬魏。^之閘極’以―半導體基板上且 Ϊ7 〇503-A30970TWFl/hsuhuch, 1326899 第95108952號申請專利範圍修正本 修正日期：99.5.3 19.如申請專利範圍第18項所述之完全金屬石夕 極無金屬矽化電阻，其中該半 甲 0Λ ,, 牛導體基板係一基體基板。 .申請專利範圍第18項所述之完全金屬石夕化 極與無金屬矽化電阻，豆中竽本 1 上丰骞辦其k > 八中導體基板包括一絕緣層 +導體,，該閘極設置於該絕緣層上半導體基板上。 翻關第18項所狀完全金屬梦化鬧 極與無金屬石夕化電阻，1中今 屬，化鬧 錯，切/錯合金。，、中料導體基板組成包括石夕， 極:二利範圍第21項所述之完全金她閘 於閘極與半導體基板之間。 电曰。又置 «^ I3Γ+ ：； ：：：：； ：： ^ --- 石夕，含氮氧化石夕，或介電常數大於4之任何材^括氧化 24. 如申請專利範圍第18項所述之 極與盔金眉石々仆雷肪^ ^ ^ 凡王金屬石夕化閘 一屬矽化電阻’更包括至少一間隔物 極或該電阻之側壁。 復ι这閘 25. 如申請專利範圍帛24項 26. 如申請專利範圍第18項所述之 極與盔今屬切/μ + ^ ^ 王I屬石夕化閘 …、金屬矽化電阻’其中該半體體之材料 夕，非晶矽，或矽/鍺合金。 曰曰 U如申請專利範圍第18項所述之完全金屬石夕化問 〇503-A30970TWl/hsuhuche 18 13268,99 第95108952號申請專利範圍修正本 修正日期：99.5.3 * . 極與無金屬矽化電阻，其中該金屬矽化閘極包括鎳，鈷， m 僞，始，錯，或鈦之金屬石夕化物。 28. 如申請專利範圍第18項所述之完全金屬矽化閘 極與無金屬矽化電阻，其中該金屬矽化閘極包括鍺矽化 物。 29. 如申請專利範圍第18項所述之完全金屬矽化閘 極與無金屬矽化電阻，更包括形成一絕緣結構於半導體 基板中，該電阻形成於該半導體基板中之絕緣結構上。 0503-A30970TWF1 /hsuhuche 19
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