WO2011061969A1 - 部分多層配線基板及びその製造方法 - Google Patents
部分多層配線基板及びその製造方法 Download PDFInfo
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- WO2011061969A1 WO2011061969A1 PCT/JP2010/062612 JP2010062612W WO2011061969A1 WO 2011061969 A1 WO2011061969 A1 WO 2011061969A1 JP 2010062612 W JP2010062612 W JP 2010062612W WO 2011061969 A1 WO2011061969 A1 WO 2011061969A1
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- main surface
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
- H05K3/4694—Partitioned multilayer circuits having adjacent regions with different properties, e.g. by adding or inserting locally circuit layers having a higher circuit density
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09972—Partitioned, e.g. portions of a PCB dedicated to different functions; Boundary lines therefore; Portions of a PCB being processed separately or differently
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive
Definitions
- the present invention relates to a partial multilayer wiring board that is used for a mobile phone or the like and has a partially different number of stacked layers, and a manufacturing method thereof.
- Partial multilayer wiring boards with different number of layers especially rigid flex printed wiring boards that include rigid and flex parts.
- a method for manufacturing a multilayer wiring board is known in which a cover layer is formed by opening a bonding portion of a substrate with a wiring circuit before and after the bonding step (Patent Document 1).
- the problem to be solved by the present invention is to provide a partial multilayer wiring board in which a circuit board with a wiring circuit is partially laminated while keeping the circuit of the wiring board in a state that can be protected without performing a protective treatment such as gold plating. Is to provide.
- the present invention includes a first insulating base material having a first conductive circuit pattern formed on one main surface, and a first conductive material layer laminated on one main surface side of the first insulating base material, and the first conductive material.
- a partial multilayer wiring board having a second insulating substrate having a second conductive circuit pattern formed on one main surface smaller than a region where the conductive circuit pattern is formed, the first conductive circuit pattern is The said subject is solved by making it cover with the other main surface of a said 2nd insulating base material.
- the second insulating substrate further includes a third insulating substrate laminated on one main surface side and having a third conductive circuit pattern formed on one main surface, and the second insulating substrate.
- the third insulating substrate can be laminated on the second insulating substrate so that the other main surface of the third insulating substrate is in contact with one main surface of the insulating substrate. .
- the fourth conductive circuit pattern formed on the other main surface of the first insulating base material and the other main surface side of the first insulating base material are laminated, and the fourth conductive property is laminated.
- a sixth insulating substrate having a sixth conductive circuit pattern formed on the other main surface, and the fourth conductive circuit pattern is covered by one main surface of the fifth insulating substrate.
- the fifth conductive circuit pattern can be configured to be covered with one main surface of the sixth insulating substrate.
- the first sheet in which the first conductive layer is laminated on one main surface of the first insulating substrate, and the second conductive layer on one main surface of the second insulating substrate. Is prepared, and a predetermined portion of the first conductive layer of the first sheet is removed to form a first conductive circuit pattern on one main surface of the first insulating substrate.
- the second sheet is attached so as to cover the first conductive circuit pattern with the other main surface of the second insulating substrate, and a predetermined portion of the second conductive layer of the attached second sheet is formed.
- the method further includes a step of preparing a third sheet in which a third conductive layer is laminated on one main surface of the third insulating substrate, and after the second conductive circuit pattern is formed, The third sheet is pasted so that the other main surface of the third insulating substrate is in contact with the second conductive circuit pattern, and a predetermined portion of the third conductive layer of the pasted third sheet is removed.
- a third conductive circuit pattern can be formed on one main surface of the third insulating substrate.
- a protective layer covering the conductive circuit pattern of the insulating base material can be formed on the uppermost layer.
- the second conductive circuit pattern is formed on the entire first conductive circuit pattern. It can be protected by an insulating substrate. As a result, a separate protection process such as gold plating becomes unnecessary, and the process can be simplified.
- the partial multilayer wiring board according to the present invention does not require a separate cover layer for covering the conductive circuit pattern other than the part where the multilayer part is provided, the thickness of the partial multilayer wiring board can be reduced. it can. For this reason, according to the manufacturing method of the partial multilayer wiring board of this invention, material cost can be reduced compared with the conventional method, and a more flexible partial multilayer wiring board can be provided.
- FIG. 4 is a first process diagram for explaining a method of manufacturing the partial multilayer wiring board shown in FIGS. 1A and 1B.
- FIG. 6 is a second process diagram for explaining the method of manufacturing the partial multilayer wiring board shown in FIGS. 1A and 1B. It is the 1st process figure for explaining the manufacturing method of the partial multilayer wiring board concerning other embodiments of the present invention. It is a 2nd process figure for demonstrating the manufacturing method of the partial multilayer wiring board which concerns on other embodiment of this invention.
- FIG. 1A is a plan view of a partial multilayer wiring board according to the present embodiment
- FIG. 1B is a cross-sectional view taken along the line IB-IB shown in FIG. 1A.
- the partial multilayer wiring board 1 of this embodiment has a multilayer portion 2 having a different number of layers from other portions.
- a first conductive circuit pattern 21 is formed on one main surface 11A of the first insulating substrate 11.
- a second conductive circuit pattern 22 is formed on the main surface 12A of the second insulating base material 12 stacked on one main surface side of the first insulating base material 11.
- a third conductive circuit pattern 23 is formed on the third insulating substrate 13 laminated on the one main surface 12A side of the second insulating substrate 12.
- the area of the region where the second conductive circuit pattern 22 and the third conductive circuit pattern 23 are formed is such that the first conductive circuit pattern 21 is formed.
- a partial multilayer structure smaller than the area of the region.
- the partial multilayer wiring board 1 of the present embodiment includes the first insulating substrate 11, the first conductive circuit pattern 21, the second insulating substrate 12, the second conductive circuit pattern 22, The third insulating substrate 13, the third conductive circuit pattern 23, and the protective layer 40 are laminated in order or indirectly via the adhesive 30.
- the opening K through which the third conductive circuit pattern 23 is exposed serves as a mounting part for an electronic component.
- the multilayer part 2 can also be formed on the other main surface 11B side of the first insulating substrate 11.
- the first conductive circuit pattern 21 formed on one main surface 11A of the first insulating substrate 11 is covered with the other main surface 12B of the second insulating substrate 12. It has been broken. That is, the other main surface 12B of the second insulating substrate 12 is in contact with one main surface 11A of the first insulating substrate 11 with the first conductive circuit pattern 21 interposed therebetween. Incidentally, the other main surface 12B of the second insulating substrate 12 and the one main surface 11A of the first insulating substrate 11 are bonded by an adhesive.
- the third insulating base material 13 is such that the other main surface 13B of the third insulating base material 13 is in contact with one main surface 12A of the second insulating base material 12. 12 are laminated.
- the partial multilayer wiring board 1 of the present embodiment has a conductive circuit pattern 20 in the lower layer by the other main surface (back surface) of the insulating base material 10 of the wiring board laminated on the upper layer side. Therefore, it is not necessary to provide a cover layer on the conductive circuit pattern 20 other than the portion where the multilayer portion 2 is provided.
- the opening of the protective layer in the multilayer part needs to be provided with a sufficient clearance so that the multilayer part can be laminated, but if this is done, there will be a gap between the multilayer part and the cover layer. Therefore, it is necessary to separately perform a protective treatment such as gold plating.
- a protective treatment such as gold plating.
- the manufacturing process can be simplified as will be described later.
- the partial multilayer wiring board 1 of the present embodiment does not require a separate cover layer for covering the conductive circuit pattern 20 other than the part where the multilayer part 2 is provided. Can be made thinner.
- the material cost can be reduced as compared with the conventional method, and a more flexible partial multilayer wiring board can be provided. .
- FIG. 2A shows a step of forming the second conductive circuit pattern 22
- FIG. 2B shows a step of forming the third conductive circuit pattern 23 and the protective layer 40 covering the third conductive circuit pattern 23.
- seat 51 by which the 1st conductive layer 21P was affixed on one main surface 11A of the 1st insulating base material 11 as shown to FIG. 2A (a) is prepared.
- the first sheet 51 has flexibility such as polyimide (PI) and has a metal sheet such as copper on one main surface of a resin sheet (first insulating substrate 11) having a thickness of 10 ⁇ m to 75 ⁇ m. Is a sheet formed.
- PI polyimide
- first insulating substrate 11 As the first insulating substrate 11, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or the like can be used.
- an etching process is performed using cupric chloride or an alkaline etchant to remove a predetermined portion of the first conductive layer 21P, and as shown in FIG.
- a first conductive circuit pattern 21 is formed on the main surface 11A.
- the first insulating circuit 11 has a first insulating surface in a region where the first conductive circuit pattern 21 is not formed on one main surface 11A.
- the roughened surface of the conductive substrate 11 appears.
- at least the surface roughness of the region where the first conductive circuit pattern 21 is not formed on one main surface 11A of the first insulating substrate 11 is the other surface of the first insulating substrate 11. It is larger than the surface roughness of the main surface 11B.
- the first sheet 51 of the present embodiment is configured by bonding the first insulating substrate 11 and the first conductive layer 21 ⁇ / b> P.
- the adhesive surface of the first conductive layer 21P is roughened.
- the first conductive layer 21P is bonded to the one main surface 11A of the first insulating substrate 11.
- the uneven shape formed on the surface is transferred, and unevenness is formed on one main surface 11A of the first insulating substrate 11.
- the surface of the roughened region has irregularities, and the surface roughness such as the centerline average roughness (Ra), the maximum height (Rmax), and the ten-point average height (Rz) is in a predetermined value range. It is in a state belonging to.
- a second sheet 52 in which the second conductive layer 22P is laminated on one main surface 12A of the second insulating substrate 12 is prepared.
- a sheet having the same quality as the first sheet 51 is used as the second sheet 52 in order to suppress the influence of shrinkage due to heat.
- the prepared first sheet 52 on which the first conductive circuit pattern 21 produced in the step (b) of the second sheet 52 is formed through the epoxy adhesive 30 is formed. Is attached to one main surface 11A side. The gaps between the concave and convex portions of the circuit of the first conductive circuit pattern 21 are filled with the adhesive 30.
- the second sheet 52 is pressed from both main surfaces with a pressing die, and one main surface 11A of the first insulating substrate 11 is pressed. Paste to the side.
- (E) of the figure shows the second sheet 52 and the first insulating substrate 11 which are released from the pressing die and integrated.
- an etching process is performed using cupric chloride or an alkaline etchant solution, and a predetermined portion of the second conductive layer 22P is removed. As shown in FIG. A second conductive circuit pattern 22 is formed on the main surface 12A. As described above, since a predetermined portion of the second conductive layer 22P is removed by the etching process, one main surface 12A of the second insulating substrate 12 on which the second conductive circuit pattern 22 is not formed is a rough surface. It has become. For this reason, the adhesiveness of one main surface 12A of the 2nd insulating base material 12 and the other main surface 13B of the 3rd insulating base material 13 mentioned later can be improved.
- a third sheet 53 in which a third conductive layer 23P is laminated on one main surface 13A of the third insulating base 13 is prepared.
- the third sheet 53 is formed smaller than the first sheet 51.
- a sheet having the same quality as the first sheet 51 is used as the third sheet 53 in order to suppress the influence of shrinkage due to heat.
- the prepared third sheet 53 is attached to the one main surface 12A side of the second insulating substrate 12 on which the already produced second conductive circuit pattern 22 is formed via the adhesive 30.
- FIG. 4B shows the third sheet 53, the second insulating base material 12, and the first insulating base material 11 which are released from a pressing die (not shown) and integrated.
- an etching process is performed using cupric chloride or an alkaline etchant to remove a predetermined portion of the third conductive layer 23P.
- a third conductive circuit pattern 23 is formed on the main surface 13 ⁇ / b> A of 13.
- a predetermined portion of the third conductive layer 23P is removed by the etching process, and one main surface 13A of the third insulating substrate 13 on which the third conductive circuit pattern 23 is not formed is roughened. ing.
- region in which the 3rd conductive circuit pattern 23 is not formed, and the protective layer 40 mentioned later can be improved.
- the adhesiveness of 3rd insulating base materials 13 can also be improved.
- the insulating substrate located in the uppermost layer in this example, the third insulating substrate 13
- a protective layer 40 is laminated thereon, and the third conductive circuit pattern 23 is covered with the protective layer 40.
- the aspect of the protective layer 40 is not particularly limited. You may form by apply
- the second conductive circuit pattern 22 is formed after the second sheet 52 is laminated on the first conductive circuit pattern 21, the first insulation is performed.
- the first conductive circuit pattern 21 can be covered with the other main surface 12B of the second insulating substrate 12 by the conductive circuit pattern 20 on the conductive substrate 11 side (lower layer side). For this reason, it is not necessary to provide a separate cover layer on the conductive circuit pattern 20 other than the portion where the multilayer portion 2 is provided, and the manufacturing process can be simplified.
- the conductive circuit in the region other than the multilayer portion is exposed, so that the region other than the multilayer portion is covered. It is necessary to form a layer.
- the other main surface of the second insulating substrate 12 on which the second conductive circuit pattern 22 to be the multilayer portion 2 is formed is the first conductive circuit pattern. 21 is covered, it is not necessary to form a separate cover layer. As a result, the manufacturing process can be simplified.
- the manufacturing method of the present embodiment since it is not necessary to provide a separate cover layer in the manufacturing method of the present embodiment, there is no gap between the multilayer portion 2 and the cover layer, so there is no need to perform gold plating or the like to fill the gap. . In this respect as well, the manufacturing process can be simplified. For this reason, according to the manufacturing method of the partial multilayer wiring board of this embodiment, material cost can be reduced compared with the conventional method, and a more flexible partial multilayer wiring board can be provided.
- the partial multilayer wiring board 1 of the present embodiment has a multilayer portion 2 formed on both main surfaces of the first insulating base material 11.
- 3A shows a process of forming the second conductive circuit pattern 22 and the fifth conductive circuit pattern 25
- FIG. 3B shows a process of forming the sixth conductive circuit pattern 23 and the protective layer 40 covering the sixth conductive circuit pattern 23. .
- the first sheet 51 ′ is prepared. As shown in FIG. 3A (a), the first sheet 51 ′ is made of a resinous sheet (first insulating base material 11) having a thickness of 10 ⁇ m to 75 ⁇ m and having flexibility such as polyimide (PI). It is a sheet in which a metal foil such as copper is formed on both main surfaces. Specifically, the first conductive layer 21P is attached to one main surface 11A of the first insulating substrate 11, and the fourth conductive layer 24P is attached to the other main surface 11B.
- first conductive layer 21P is attached to one main surface 11A of the first insulating substrate 11, and the fourth conductive layer 24P is attached to the other main surface 11B.
- an etching process is performed using cupric chloride or an alkaline etchant to remove a predetermined portion of the first conductive layer 21P and a predetermined portion of the fourth conductive layer 24P.
- the first conductive circuit pattern 21 is formed on one main surface 11A of the first insulating base material 11, and the other main surface 11B of the first insulating base material 11 is formed.
- a fourth conductive circuit pattern 24 is formed. The surface of the area
- a fifth sheet 55 having a second conductive layer 25P formed on the other main surface 15B of the base material 15 is prepared. In the present embodiment, it is desirable that the second sheet 52 and the fifth sheet 55 are the same quality as the first sheet 51.
- seat 55 is made into the 1st electroconductive circuit pattern 21 and the 4th electroconductivity produced by the process of the figure (b) through the adhesive agent 30.
- the first insulating base material 11 on which the circuit pattern 24 is formed is laminated on both main surfaces 11A and 11B.
- both main surfaces 11A of the first insulating substrate 11 are pressed by pressing the second sheet 52 and the fifth sheet 55 from both main surfaces with a pressing die. , 11B.
- FIG. 4D shows the second sheet 52, the fifth sheet, and the first insulating substrate 11 which are released from the pressing mold and integrated.
- an etching process is performed using cupric chloride or an alkali etchant to remove a predetermined portion of the second conductive layer 22P and a predetermined portion of the fifth conductive layer 25P.
- the second conductive circuit pattern 22 is formed on one main surface 12A of the second insulating substrate 12, and the other main surface of the fifth insulating substrate 15 is formed.
- a fifth conductive circuit pattern 25 is formed on 15B.
- the second conductive circuit pattern 22 and the fifth conductive circuit pattern 25 are not formed by removing predetermined portions of the second conductive layer 22P and the fifth conductive layer 25P by the etching process.
- One main surface 12A of the 2 insulating substrate 12 and the other main surface 15B of the fifth insulating substrate 15 are roughened. For this reason, one main surface 12A of the second insulating substrate 12, the other main surface 13B of the third insulating substrate 13 described later, and the other main surface 15B of the fifth insulating substrate 15 are described later. Adhesiveness with one main surface 16A of the 6th insulating base material 16 can be improved.
- a sixth sheet 56 having a sixth conductive layer 26P formed on the main surface 16B is prepared.
- the third sheet 53 and the sixth sheet 56 are formed smaller than the first sheet 51.
- it is desirable that the third sheet 53 and the sixth sheet 56 are sheets of the same quality as the first sheet 51.
- the prepared third sheet 53 is laminated on the one main surface 12A side of the second insulating substrate 12 on which the second conductive circuit pattern 22 is formed, with the adhesive 30 interposed therebetween.
- the sixth sheet 56 is laminated on the other main surface 15B side of the fifth insulating substrate 15 on which the fifth conductive circuit pattern 25 is formed, with the adhesive 30 interposed therebetween.
- the pressing sheet Under a predetermined heating / pressurizing environment, the pressing sheet is pressed from both main surfaces, the third sheet 53 is placed on one main surface 12A side of the second insulating substrate 12, and the sixth sheet 56 is insulated by the fifth. Affixed to the other main surface 15B side of the conductive substrate 15.
- FIG. 5B shows a third sheet 53, a second insulating substrate 12, a first insulating substrate 11, a fifth insulating substrate 15, and a first sheet that are released from a pressing mold (not shown) and integrated. 6 sheets 56 are shown.
- the predetermined portion of the third conductive layer 23P and the predetermined portion of the sixth conductive layer 26P are removed by an etching process, and as shown in FIG.
- the third conductive circuit pattern 23 is formed, and the sixth conductive circuit pattern 26 is formed on the other main surface 16B of the sixth insulating substrate 16.
- the other main surface 16B of the insulating substrate 16 is roughened. For this reason, like the above-mentioned example, the adhesiveness of laminated layers, such as the protective layer 40 mentioned later, improves.
- a through hole 60 penetrating the partial multilayer wiring board 1 in the vertical direction is formed using a drill or a laser. Copper plating is performed on the inner side surface of the through hole 60 using a general electroless copper plating method or electrolytic copper plating method to form a plating layer 61.
- the plating layer 61 may be formed of a conductive material such as another metal.
- the insulating base material in this example, the first base material
- the protective layer 40 is laminated on the third insulating substrate 13 and the sixth insulating substrate 16), and the third conductive circuit pattern 23 and the sixth conductive circuit pattern 26 are respectively covered with the protective layer 40.
- the second sheet 52 and / or the second conductive circuit pattern 24 is added to the first conductive circuit pattern 21 and / or the fourth conductive circuit pattern 24. Since the second conductive circuit pattern 22 and / or the fifth conductive circuit pattern 25 is formed after the five sheets 55 are laminated, the conductive circuit patterns 21 and 24 of the first insulating base material 11 The other main surface 12B of the insulating base 12 and the one main surface 15A of the fifth insulating base 15 can be covered. For this reason, it is not necessary to provide a separate cover layer on the conductive circuit pattern 20 other than the portion where the multilayer portion 2 is provided, and the manufacturing process can be simplified.
- the conductive circuit in the region other than the multilayer portion is exposed, so that the region other than the multilayer portion is covered. It is necessary to form a layer.
- the other main surface 12B of the second insulating substrate 12 on which the second conductive circuit pattern 22 to be the multilayer portion 2 is formed is the first conductive circuit. Since one main surface 15A of the fifth insulating base material 15 covering the pattern 21 and having the fifth conductive circuit pattern 25 formed thereon covers the fourth conductive circuit pattern 24, it is necessary to separately form a cover layer. There is no. As a result, the manufacturing process can be simplified.
- the manufacturing method of the present embodiment since it is not necessary to provide a separate cover layer in the manufacturing method of the present embodiment, there is no gap between the multilayer portion 2 and the cover layer, so there is no need to perform gold plating or the like to fill the gap. . In this respect as well, the manufacturing process can be simplified. For this reason, according to the manufacturing method of the partial multilayer wiring board of this embodiment, material cost can be reduced compared with the conventional method, and a more flexible partial multilayer wiring board can be provided.
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Abstract
Description
以下、図面に基づいて、本発明に係る第1実施形態の部分多層配線基板1について説明する。
以下、図3A及び図3Bに基づいて、本発明の第2実施形態に係る部分多層配線基板1の他の製造方法について説明する。本実施形態の部分多層配線基板1は、第1絶縁性基材11の両主面に多層部分2が形成されたものである。図3Aは、第2導電性回路パターン22及び第5導電性回路パターン25を形成する工程を示し、図3Bは、第6導電性回路パターン23及びこれを覆う保護層40を形成する工程を示す。
2…多層部分
10…絶縁性基材
11…第1絶縁性基材,12…第2絶縁性基材,13…第3絶縁性基材
15…第5絶縁性基材,16…第6絶縁性基材
20…導電性回路パターン
21…第1導電性回路パターン,22…第2導電性回路パターン
23…第3導電性回路パターン,24…第4導電性回路パターン
25…第5導電性回路パターン,26…第6導電性回路パターン
30…接着剤
40…保護層
51…第1シート,52…第2シート,53…第3シート
60…スルーホール
61…めっき層
Claims (7)
- 一方の主面に第1導電性回路パターンが形成された第1絶縁性基材と、
前記第1絶縁性基材の一方の主面側に積層されるとともに、前記第1導電性回路パターンが形成された領域よりも小さい第2導電性回路パターンが一方の主面に形成された第2絶縁性基材と、を有する部分多層配線基板において、
前記第1導電性回路パターンが前記第2絶縁性基材の他方の主面により覆われていることを特徴とする部分多層配線基板。 - 前記第1絶縁性基材の一方の主面のうち前記第1導電性回路パターンが形成されていない領域及び/又は前記第2絶縁性基材の一方の主面のうち前記第2導電性回路パターンが形成されていない領域は粗面化されていることを特徴とする請求項1に記載の部分多層配線基板。
- 前記第2絶縁性基材の一方の主面側に積層され、第3導電性回路パターンが一方の主面に形成された第3絶縁性基材をさらに備え、
前記第2絶縁性基材の一方の主面に前記第3絶縁性基材の他方の主面が接するように、前記第3絶縁性基材が前記第2絶縁性基材に積層されていることを特徴とする請求項1又は2に記載の部分多層配線基板。 - 前記第1絶縁性基材の他方の主面に形成された第4導電性回路パターンと、
前記第1絶縁性基材の他方の主面側に積層され、前記第4導電性回路パターンが形成された領域よりも小さい第5導電性回路パターンが他方の主面に形成された第5絶縁性基材と、
前記第5絶縁性基材の他方の主面側に積層され、第6導電性回路パターンが他方の主面に形成された第6絶縁性基材と、を有し、
前記第4導電性回路パターンは前記第5絶縁性基材の一方の主面により覆われており、前記第5導電性回路パターンは前記第6絶縁性基材の一方の主面により覆われていることを特徴とする請求項1~3の何れか一項に記載の部分多層配線基板。 - 第1絶縁性基材の一方の主面に第1導電層が積層された第1シートと、第2絶縁性基材の一方の主面に第2導電層が積層された第2シートとを準備し、
前記第1シートの第1導電層の所定部を除去して前記第1絶縁性基材の一方の主面に第1導電性回路パターンを形成し、
前記第1導電性回路パターンを前記第2絶縁性基材の他方の主面で覆うように、前記第2シートを貼り付け、
前記貼り付けられた第2シートの第2導電層の所定部を除去して前記第2絶縁性基材の一方の主面に第2導電性回路パターンを形成する部分多層配線基板の製造方法。 - 第3絶縁性基材の一方の主面に第3導電層が積層された第3シートを準備する工程をさらに有し、
前記第2導電性回路パターンが形成された後、前記第2導電性回路パターンに前記第3絶縁性基材の他方の主面が接するように、前記第3シートを貼り付け、
前記貼り付けられた第3シートの第3導電層の所定部を除去して前記第3絶縁性基材の一方の主面に第3導電性回路パターンを形成する請求項5に記載の部分多層配線基板の製造方法。 - 最上層に位置する絶縁性基材の導電性回路パターンを覆う保護層を形成する請求項5又は6に記載の部分多層配線基板の製造方法。
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CN2010800394234A CN102484952A (zh) | 2009-11-18 | 2010-07-27 | 部分多层配线基板及其制造方法 |
JP2011541833A JPWO2011061969A1 (ja) | 2009-11-18 | 2010-07-27 | 部分多層配線基板及びその製造方法 |
US13/474,423 US20120222887A1 (en) | 2009-11-18 | 2012-05-17 | Partially multilayered wiring board and method of manufacturing partially multilayered wiring board |
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JP2009-262599 | 2009-11-18 |
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US13/474,423 Continuation US20120222887A1 (en) | 2009-11-18 | 2012-05-17 | Partially multilayered wiring board and method of manufacturing partially multilayered wiring board |
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JP (1) | JPWO2011061969A1 (ja) |
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Citations (2)
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JPH11238965A (ja) * | 1998-02-20 | 1999-08-31 | Hitachi Chem Co Ltd | 多層プリント配線板の製造方法 |
JP2004228165A (ja) * | 2003-01-20 | 2004-08-12 | Fujikura Ltd | 多層配線板およびその製造方法 |
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JP2000223835A (ja) * | 1999-01-29 | 2000-08-11 | Canon Inc | 多層配線板 |
TW512653B (en) * | 1999-11-26 | 2002-12-01 | Ibiden Co Ltd | Multilayer circuit board and semiconductor device |
CN1264391C (zh) * | 2001-06-27 | 2006-07-12 | 日本特殊陶业株式会社 | 布线基板的制造方法 |
EP1357773A3 (en) * | 2002-04-25 | 2005-11-30 | Matsushita Electric Industrial Co., Ltd. | Wiring transfer sheet and method for producing the same, and wiring board and method for producing the same |
JP2005045150A (ja) * | 2003-07-25 | 2005-02-17 | Matsushita Electric Ind Co Ltd | 中間接続用配線基材および多層配線基板、ならびにこれらの製造方法 |
US8178789B2 (en) * | 2007-07-17 | 2012-05-15 | Ibiden Co., Ltd. | Wiring board and method of manufacturing wiring board |
JP2009064909A (ja) * | 2007-09-05 | 2009-03-26 | Alps Electric Co Ltd | 多層セラミック配線板およびその製造方法 |
US8519270B2 (en) * | 2010-05-19 | 2013-08-27 | Unimicron Technology Corp. | Circuit board and manufacturing method thereof |
-
2010
- 2010-07-27 CN CN2010800394234A patent/CN102484952A/zh active Pending
- 2010-07-27 JP JP2011541833A patent/JPWO2011061969A1/ja active Pending
- 2010-07-27 WO PCT/JP2010/062612 patent/WO2011061969A1/ja active Application Filing
- 2010-08-03 TW TW099125726A patent/TW201119540A/zh unknown
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2012
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Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11238965A (ja) * | 1998-02-20 | 1999-08-31 | Hitachi Chem Co Ltd | 多層プリント配線板の製造方法 |
JP2004228165A (ja) * | 2003-01-20 | 2004-08-12 | Fujikura Ltd | 多層配線板およびその製造方法 |
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JPWO2011061969A1 (ja) | 2013-04-04 |
US20120222887A1 (en) | 2012-09-06 |
CN102484952A (zh) | 2012-05-30 |
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