WO2011058647A1 - アクティブマトリクス型モジュール及びその駆動方法 - Google Patents
アクティブマトリクス型モジュール及びその駆動方法 Download PDFInfo
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- WO2011058647A1 WO2011058647A1 PCT/JP2009/069368 JP2009069368W WO2011058647A1 WO 2011058647 A1 WO2011058647 A1 WO 2011058647A1 JP 2009069368 W JP2009069368 W JP 2009069368W WO 2011058647 A1 WO2011058647 A1 WO 2011058647A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
Definitions
- the present invention relates to an active matrix module in which a large number of capacitive memory cells incorporating active elements made of transistors are arranged at intersections of scanning lines and data lines arranged in a matrix, and a driving method thereof.
- an active matrix type module in which a large number of capacitive memory cells are arranged at intersections of scanning lines and data lines arranged in a matrix
- an active matrix type display panel such as a liquid crystal or an organic EL (electroluminescence), an electronic paper, etc.
- a memory element for example, a memory element.
- a capacitive memory cell included in an organic EL panel which is one of active matrix modules includes an organic EL element which is a light emitting element, a transistor as an active element, and a capacitive element.
- the transistor includes two transistors, a scanning transistor and a driving transistor.
- the gate electrode of the scanning transistor is connected to the scanning line, and the source electrode is connected to the data line.
- the source electrode of the driving transistor is connected to a power supply line that supplies a constant power supply voltage, and the gate electrode is connected to the drain electrode of the scanning transistor.
- the capacitor element is connected between the gate electrode and the source electrode of the driving transistor.
- the anode of the light emitting element is connected to the drain of the driving transistor, and the cathode is grounded.
- a capacitive parasitic element is formed between the gate and source electrodes of the transistor or between the gate and drain electrodes.
- the transistor has a structure in which the gate electrode and the channel electrode overlap each other with the gate insulating film interposed therebetween, and the overlapping portion forms a capacitor.
- the area of the overlapping portion tends to become smaller due to the progress of the manufacturing process, it is difficult to make the overlapping area zero in a coating-type semiconductor using a printing process that has been attracting attention in recent years. Therefore, if a scan pulse is supplied in a state where the parasitic element is formed in the driving transistor, the charge accumulated in the capacitor element is drawn due to the feed-through effect at the moment of pulse-off, resulting in an error in the data voltage. is there.
- the problems to be solved by the present invention include the above-mentioned problems as an example.
- the invention according to claim 1 is an active matrix module in which a large number of capacitive memory cells are arranged at intersections of scanning lines and data lines arranged in a matrix.
- the capacitive memory cell includes a first transistor having a gate electrode connected to the scan line and a source electrode connected to the data line, and a first terminal on one side connected to the drain electrode of the first transistor.
- a capacitive element that accumulates electric charge according to a data voltage supplied from the data line through the source electrode and the drain electrode when a scan pulse is supplied from the scan line to the gate electrode.
- the correction memory having a polarity opposite to that of the scan pulse is applied to the capacitive memory cell at a timing corresponding to a supply timing of the scan pulse. It provided a correction pulse supply unit for supplying.
- the invention according to claim 12 is characterized in that a first transistor having a gate electrode connected to a scanning line and a source electrode connected to a data line, and a first terminal on one side are said first terminals.
- a scan pulse is connected to the drain electrode of one transistor and a scan pulse is supplied from the scan line to the gate electrode, a charge is charged according to a data voltage supplied from the data line through the source electrode and the drain electrode.
- FIG. 10 is a diagram illustrating an example of a circuit of a pixel portion of a display panel in a modification in which a correction pulse is supplied from a power supply line to a capacitor.
- FIG. 11 is a diagram illustrating an example of a circuit of a pixel portion of a display panel in a modification in which a correction pulse is supplied from a power supply line to a driving transistor. It is a figure which shows an example of the circuit of the pixel part at the time of applying to a memory element, an electronic paper, and an LCD active matrix type display panel.
- FIG. 1 is a block diagram illustrating an example of functions of a display device 10A using an active matrix display panel 11 (hereinafter simply referred to as “display panel 11”) as an active matrix module of the present embodiment.
- the display device 10A includes a display panel 11, a scanning driver 12, a data driver 13, a correction pulse applying circuit 14, a controller 15, and a light emitting element driving power source 16 (hereinafter simply referred to as “power source 16”). ing.
- the pixel portions PL 1,1 to PL n, m (capacitive memory cells) are arranged at intersections of the data lines X1 to Xm and the scanning lines Y1 to Yn arranged in a matrix, and all have the same configuration. ing.
- the pixel portions PL 1,1 to PL n, m are connected to the power supply line Z.
- a drive voltage (positive voltage Vdc) is supplied to the power supply line Z from the power supply 16.
- signal lines W1 to Wn corresponding to the scanning lines Y1 to Yn are provided.
- the signal lines W1 to Wn are provided in parallel with the scanning lines so as to correspond to the scanning lines Y1 to Yn in the same number as the scanning lines Y1 to Yn.
- a correction pulse CP having a predetermined magnitude is supplied from the correction pulse applying circuit 14 to the signal lines W1 to Wn at a predetermined timing for each signal line.
- the correction pulse applying circuit 14 and the signal lines W1 to Wn constitute a correction pulse supply unit described in the claims.
- the pixel portion PL j, i includes two scanning transistors 21 (first transistor) and a driving transistor 22 (second transistor), a capacitor 24 (capacitance element), and a light emitting element 25.
- the light emitting element 25 for example, an organic EL (electroluminescence) element can be adopted.
- the transistors 21 and 22 for example, P-channel organic thin film transistors can be employed.
- the light emitting element and the transistor using an organic material are not limited, and a light emitting element based on amorphous silicon or another semiconductor, a bipolar transistor, or another transistor may be used.
- the drain electrode of the scanning transistor 21 is connected to the gate electrode of the driving transistor 22.
- the source electrode of the drive transistor 22 is connected to the power supply line Z, and the drive voltage Vdc is supplied from the power supply 16.
- the gate electrode of the drive transistor 22 is connected to the drain electrode of the scanning transistor 21 and to the first terminal 24 a on one side of the capacitor 24.
- the drain electrode of the drive transistor 22 is connected to the anode of the light emitting element 25.
- the cathode of the light emitting element 25 is grounded.
- the correction pulse application circuit 14 applies a correction pulse CP having a polarity opposite to that of the scanning pulse SP to the pixel unit PL j, i, that is, the capacitor 24 at a timing according to the supply timing of the scanning pulse SP. Supply.
- a method for calculating the amplitude of the correction pulse CP will be described.
- FIG. 3 is a conceptual diagram showing an example of a layer structure of a general organic thin film transistor formed by a wet process such as printing.
- This organic thin film transistor is formed by laminating a gate electrode 2, a gate insulating film 3, a source electrode 4, a drain electrode 5, and an organic semiconductor 6 (organic semiconductor layer) in this order on a substrate 1 such as glass.
- the gate electrode 2 and the channel electrodes 4 and 5 overlap with each other in the layer direction via the gate insulating film 3, the overlapping portion forms a capacitance, and the gate / source electrode of the transistor
- a capacitive parasitic element 7 is formed between the gate electrode and the drain electrode.
- the scanning transistor 21 and the driving transistor 22 in this embodiment also have the same structure as described above. Therefore, if the scan pulse SP is supplied in a state where this parasitic element is formed in the scan transistor 21, feedthrough in which the charge accumulated in the capacitor 24 is extracted at the moment of pulse-off occurs.
- the amplitude of the correction pulse CP is V CP
- the amplitude of the scanning pulse SP is V SP
- the capacitance of the capacitor 24 is CS
- the sum of all capacitances viewed from the gate line of the driving transistor 22 is C ALL
- the feedthrough voltage ⁇ V1 generated at the moment when the scanning transistor 21 is turned off is expressed by the following equation.
- ⁇ V1 V SP ⁇ C SCAN / (C ALL ⁇ C SCAN ) (1)
- the feedthrough voltage ⁇ V2 generated by turning off the correction pulse CP at the same timing is expressed by the following equation.
- the coefficient k is controlled by the controller 15 (pulse amplitude adjusting means) based on an input from an external input means (not shown). That is, the display panel 11 is configured so that the amplitude V CP of the correction pulse CP can be adjusted from the outside.
- FIG. 4 shows the supply timing of the scan pulse SP supplied to the scan line Yj of the display panel 11 and the correction pulse CP supplied to the signal line Wj corresponding to the scan line Yj, and the gate voltage Vg of the drive transistor 22. It is a time chart showing the relationship.
- the controller 15 generates a correction pulse CP having a polarity opposite to that of the scan pulse SP by logically inverting the phase of the scan pulse SP.
- the correction pulse applying circuit 14 applies the correction pulse CP to the signal line Wj so that the ON / OFF timing of the correction pulse CP is almost the same as the ON / OFF timing of the scanning pulse SP. Supply.
- the gate voltage Vg can be converged to the data voltage Vdata in the data writing period T, and can be prevented from being affected by the above-described feedthrough effect.
- this detailed content is demonstrated, using a comparative example.
- FIG. 5 is a diagram illustrating an example of a circuit of the pixel unit PL j, i ′ as a comparative example.
- the circuit of the pixel portion PL j, i ′ differs from the circuit of PL j, i of the present embodiment in that the signal lines W1 to Wn for supplying the correction pulse CP are not provided, and the second of the capacitor 24 The terminal 24b is connected to the power supply line Z. Accordingly, the drive voltage Vdc is supplied from the power supply 16 to the second terminal 24 b of the capacitor 24 together with the drain electrode of the drive transistor 22.
- Other configurations are the same as those of PL j, i described above.
- FIG. 6 shows the relationship between the supply timing of the scan pulse SP supplied to the scan line Yj of the display panel 11 having the pixel portion PL j, i ′ as the comparative example and the gate voltage Vg of the drive transistor 22. It is a time chart.
- the correction pulse CP having the opposite polarity to the scanning pulse SP is supplied to the signal line Wj so as to be almost simultaneously with the on / off timing of the scanning pulse SP.
- the correction effect of the error Gp of the data voltage Vdata will be described with reference to FIG.
- FIG. 7 is a time chart showing the relationship between the supply timing of the scan pulse SP and the correction pulse CP and the gate voltage Vg of the drive transistor 22, and corresponds to the above-described FIG. In order to show the movement, the on / off timings of the scanning pulse SP and the correction pulse CP are slightly shifted.
- the second terminal 24b of the capacitor 24 is supplied with the correction voltage V CP by the correction pulse CP, since the first terminal 24a in a state where the data voltage Vdata is supplied, the capacitor 24 voltage V CP - Charge corresponding to Vdata is accumulated. Thereby, the gate voltage Vg converges to Vdata (section t2).
- the scan pulse SP When the scan pulse SP is turned off, the charge accumulated in the capacitor 24 is extracted by the feedthrough effect based on the parasitic capacitance formed between the gate and drain electrodes of the scan transistor 21 at the moment of the pulse off, and the gate voltage Vg Changes in the positive direction by the feedthrough voltage ⁇ V1 described above. Thereafter, when the correction pulse CP is turned off, charge is replenished to the capacitor 24 by the feed-through effect due to the pulse-off, and the gate voltage Vg changes in the negative direction by the feed-through voltage ⁇ V2 generated by turning off the correction pulse CP.
- the amplitude VCP of the correction pulse CP is set so that the sum of the feedthrough voltage ⁇ V1 and the feedthrough voltage ⁇ V2 becomes 0, the feedthrough is canceled and the gate voltage Vg is equal to Vdata. Become.
- the time chart as shown in FIG. 4 is obtained. .
- the on / off timing of the correction pulse CP and the on / off timing of the scanning pulse SP are simultaneously, and the actual deviation from the scanning pulse SP as shown in FIG.
- the correction pulse may be supplied at the timing.
- the ON timing of the correction pulse SP is greatly delayed from the ON timing of the CP, it is difficult to secure a data writing time (corresponding to the section t2). It must be within the range that can be secured.
- the OFF timing of the correction pulse SP is earlier than the OFF timing of the scanning pulse SP, the data voltage fluctuates due to feedthrough after correction, so the OFF timing of the correction pulse SP is the same as that of the scanning pulse SP. It is necessary to be after the off timing.
- the off timing of the correction pulse SP is greatly delayed from the off timing of the CP, the data voltage has an error during that time. Therefore, it is preferable that the delay of the off timing is as small as possible.
- the procedure in which the controller 15 controls the scan driver 12 to supply the scan pulse SP to the gate electrode of the scan transistor 21 via the scan line Yj corresponds to the scan pulse supply procedure described in the claims.
- the procedure in which the controller 15 controls the correction pulse applying circuit 14 to supply the correction pulse CP to the capacitor 24 via the signal line Wj corresponds to the correction pulse supply procedure.
- the display panel 11 of the present embodiment has a large number of pixel portions PL j, i arranged at intersections of the scanning lines Yj and the data lines Xi arranged in a matrix, and each pixel portion PL j, i is scanned.
- Each has a transistor 21 and a capacitor 24.
- the scanning pulse SP is supplied from the scanning line Yj to the gate electrode of the scanning transistor 21, the source and drain electrodes of the scanning transistor 21 are brought into conduction.
- the data voltage is supplied from the data line Xi via the source / drain electrodes of the scanning transistor 21, and charges corresponding to the data voltage are accumulated in the capacitor 24.
- the correction pulse application circuit 14 applies a correction pulse CP having a polarity opposite to that of the scanning pulse SP to the capacitor of each pixel unit PL j, i via the signal line Wj at a timing corresponding to the supply timing of the scanning pulse SP. 24 is supplied.
- charge can be replenished to the capacitor 24, and the decrease in charge in the capacitor 24 due to the feedthrough effect can be suppressed.
- an error in the data voltage due to the feedthrough effect can be corrected without increasing the number of transistors in each pixel portion PL j, i . Therefore, it is possible to prevent a decrease in the yield of the display panel 11 and a decrease in the aperture ratio.
- the pixel unit PL j, i has a configuration including the drive transistor 22. That is, when the scan pulse SP is supplied from the scan line Yj to the gate electrode of the scan transistor 21, the data voltage accumulated in the capacitor 24 is supplied between the gate and source electrodes of the drive transistor 22, and the data voltage corresponds to the data voltage.
- the drain current flows between the drain and source electrodes of the driving transistor 22 and is supplied to the light emitting element 25.
- the display panel 11 of the above embodiment further includes a second terminal 24b in addition to the first terminal 24a connected to the drain electrode of the scanning transistor 21.
- the pulse applying circuit 14 supplies a correction pulse CP to the capacitor 24 through the signal line Wj and the second terminal 24b.
- the display panel 11 is further connected to the second terminals 24b of the capacitors 24 related to the plurality of pixel portions PL j, i arranged along the scanning line Yj.
- the signal lines Wj are arranged substantially in parallel with the scanning lines Yj and are provided in the same number as the scanning lines Yj so as to correspond to the scanning lines Yj on a one-to-one basis.
- the correction pulse CP is supplied from the signal line Wj to the capacitor 24 via the second terminal 24b.
- the correction pulse CP can be supplied independently of the power supply system of the drive transistor 22.
- the correction pulse applying circuit 14 applies the correction pulse CP to the capacitor 24 so that the OFF timing of the correction pulse CP is after the OFF timing of the scanning pulse SP.
- Supply against That is, when the OFF timing of the correction pulse CP is earlier than the OFF timing of the scan pulse SP, the scan pulse SP is turned off after the correction pulse ends, and an error occurs in the data voltage due to the feedthrough effect when the pulse is off. Therefore, by making the OFF timing of the correction pulse CP coincide with or after the OFF timing of the scanning pulse SP as in this embodiment, it is possible to reliably correct the data voltage error due to the feedthrough effect.
- the correction pulse CP is generated by logically inverting the scanning pulse SP, and the correction pulse applying circuit 14 includes the correction pulse CP.
- the correction pulse CP is supplied to the capacitor 24 so that the on / off timing is substantially the same as the on / off timing of the scanning pulse SP. Accordingly, it is reasonable that both the scan pulse SP and the correction pulse CP are generated by processing based on the same logic signal.
- the ON timing of the correction pulse CP is simultaneously with the ON timing of the scan pulse SP, a sufficient charging time for the capacitor 24 after the scan pulse is ON can be secured, and the OFF timing of the correction pulse CP is scanned. Since it is simultaneously with the off timing of the pulse SP, it is possible to reliably correct the data voltage error due to the feedthrough effect as described above.
- the controller 15 is configured to be able to adjust the pulse amplitude of the correction pulse CP.
- the controller 15 is configured to be able to adjust the pulse amplitude of the correction pulse CP.
- the gate electrode, the source electrode, and the drain electrode of the scanning transistor 21 and the drive transistor 22 are formed by a wet process such as printing.
- a wet process such as printing.
- an active matrix module having a large area can be manufactured more easily and cheaply than when a dry process is used.
- a transistor is manufactured by a printing process, it is difficult to prevent the gate electrode and the channel electrode from overlapping in the layer direction via the gate insulating film, so that a feedthrough effect due to a parasitic element occurs. It will be. Therefore, it is suitable as an application target of the configuration of the present embodiment that can reduce the feedthrough effect.
- an organic thin film transistor having the organic semiconductor 6 is employed as the scanning transistor 21 and the driving transistor 22.
- it can be formed softer than a silicon-based semiconductor and can be manufactured by a low-temperature process.
- a large-area active matrix module can be produced at low cost.
- the correction pulse supply signal line Wj is provided, and the correction pulse CP is supplied to the capacitor 24 via the signal line Wj.
- the present invention is not limited to this, and the correction pulse CP may be supplied via the power supply line Z that supplies the drive voltage to the drive transistor 22.
- FIG. 8 is a diagram illustrating an example of a circuit of the pixel unit PL j, i according to the present modification.
- the source electrode of the drive transistor 22 and the second terminal 24b of the capacitor 24 are connected to the power supply line Z ′.
- the correction pulse applying circuit 14 supplies the correction pulse CP to the capacitor 24 through the power supply line Z ′.
- the power supply 16 is not necessary.
- the capacitor 24 can be replenished with charge, and the decrease in charge in the capacitor 24 due to the feedthrough effect can be suppressed.
- the correction pulse CP is supplied using the power supply line Z ′ of the driving transistor 22 as described above, a new signal line for supplying the correction pulse is not required as in the above-described embodiment, and the number of wirings is reduced. Can be minimized. Furthermore, there is an effect that the amplitude V CP of the correction pulse CP can be reduced as compared with the case where the correction pulse CP is supplied to the capacitor 24 through a dedicated signal line.
- the correction pulse CP is supplied from the power supply line Z ′ to the capacitor 24.
- the correction pulse CP may be supplied to the driving transistor 22 from the line Z ′.
- FIG. 9 is a diagram illustrating an example of a circuit of the pixel unit PL j, i of the present modification.
- the source electrode of the drive transistor 22 is connected to the power supply line Z ′.
- the second terminal 24 b of the capacitor 24 is connected to a power supply line Z to which a power supply voltage (positive voltage Vdc) is supplied from the power supply 16.
- the correction pulse applying circuit 14 supplies the correction pulse CP to the drive transistor 22 through the power supply line Z ′.
- the correction pulse CP can be supplied to the parasitic capacitance formed between the gate and source electrodes of the drive transistor 22.
- charge can be replenished to the parasitic capacitance, so that a decrease in charge in the capacitor 24 due to the feedthrough effect can be suppressed.
- the power supply line Z ′ is connected to the correction pulse CP as in the modified examples (1) and (2).
- the same number of power supply lines Z ′ as the scanning lines Yj are provided.
- at this time for example, in the case of a full color panel, at least three color pixel portions PL j, i are generally arranged on the same scanning line.
- the power supply line Z ′ is used as the supply line for the correction pulse CP, it is necessary to devise such as driving the power supply line Z ′ of the drive transistor 22 in common for each color.
- an active matrix display panel using an organic EL as an example of an active matrix module has been described.
- the present invention is not limited to this.
- an LCD active matrix using liquid crystal You may apply to a type
- the present invention is not limited to a display panel, and can be applied to other modules as long as they have a large number of high-density capacitive memory cells, such as electronic paper, memory elements, and image sensors.
- FIG. 10 is a diagram illustrating an example of a circuit of the pixel portion PL j, i when applied to a memory element, electronic paper, or an LCD active matrix display panel.
- the pixel portion PL j, i of this modification has one scanning transistor 21 (first transistor) and a capacitor 24 (capacitance element).
- the correction pulse applying circuit 14 outputs a correction pulse CP having a polarity opposite to that of the scanning pulse SP based on the control of the controller 15 at a timing corresponding to the supply timing of the scanning pulse SP.
- the voltage is supplied to the capacitor 24 via the line Wj and the second terminal 24b.
- the display panel having the pixel portions PL j, i including the transistors 21 and 22 formed by the wet process has been described as an example.
- the present invention is not limited to this, and the processing is more precise than the wet process.
- This is also effective for a module including a transistor formed by a silicon-based process that can be used. That is, even when formed by a silicon-based process, if the pixel portion PL j, i is reduced and the transistor size is reduced, the influence of the parasitic capacitance is increased. Even a binary signal “Hi” or “Lo” is used. Input may be difficult.
- the influence of parasitic capacitance can be offset, and as a result, transistor design specifications are relaxed, resulting in higher display definition, higher memory density, and improved panel yield. Can be planned.
- Organic semiconductor organic semiconductor layer
- Display panel active matrix module
- Correction pulse application circuit correction pulse supply unit
- Controller Pulse amplitude adjusting means
- Scanning transistor first transistor
- Capacitor 24a 1st terminal 24b 2nd terminal
- CP correction pulse SP scanning pulse
- Vdata data voltage Wj signal line (correction pulse supply unit)
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Abstract
Description
ΔV1=VSP×CSCAN/(CALL-CSCAN)・・・(1)
また、同じタイミングで補正パルスCPのオフにより発生させるフィードスルー電圧ΔV2は次式で表される。
ΔV2=VCP×CS/(CALL-CS)・・・(2)
ΔV1とΔV2との和が0になればフィードスルーが相殺されるので、
ΔV1+ΔV2=0・・・(3)
以上の式(1)~(3)により、
VCP=-VSP×{CSCAN(CALL-CS)}/{CS(CALL-CSCAN)}
となる。ここで、
{CSCAN(CALL-CS)}/{CS(CALL-CSCAN)}=kとすると、
VCP=-k×VSP(k:係数)
で表される。
上記実施形態では、補正パルス供給用の信号線Wjを設け、当該信号線Wjを介してキャパシタ24に補正パルスCPを供給するようにしたが、これに限らず、駆動トランジスタ22に駆動電圧を供給する電源線Zを介して補正パルスCPを供給するようにしてもよい。
上記変形例(1)では、電源線Z′からキャパシタ24に対して補正パルスCPを供給するようにしたが、これに限らず、電源線Z′から駆動トランジスタ22に対して補正パルスCPを供給するようにしてもよい。
上記実施形態は、アクティブマトリクス型モジュールの一例として有機ELを用いたアクティブマトリクス型表示パネルを説明したが、これに限らず、例えば液晶を用いたLCDアクティブマトリクス型表示パネルに適用してもよい。さらには表示パネルに限らず、例えば電子ペーパやメモリ素子、撮像素子等、高密度な容量性メモリセルを多数有するものであればその他のモジュールにも適用可能である。
上記実施形態は、ウェットプロセスにより形成したトランジスタ21,22を備えた画素部PLj,iを有する表示パネルを一例として説明したが、これに限らず、ウェットプロセスよりも精密な加工が可能なシリコン系プロセスで形成したトランジスタを備えたモジュールに対しても有効である。すなわち、シリコン系プロセスで形成した場合でも、画素部PLj,iが小さくなりトランジスタのサイズが薄く小さくなると、寄生容量の影響が大きくなり、たとえ「Hi」か「Lo」かの2値信号でも入力困難になる場合がある。このようなモジュールに適用することで、寄生容量の影響を相殺することができ、その結果、トランジスタの設計仕様が緩やかとなり、表示の高精細化、メモリの高密度化、パネルの歩留まりの向上を図ることができる。
11 表示パネル(アクティブマトリクス型モジュール)
14 補正パルス印加回路(補正パルス供給部)
15 コントローラ(パルス振幅調整手段)
21 走査トランジスタ(第1トランジスタ)
24 キャパシタ(容量素子)
24a 第1端子
24b 第2端子
25 発光素子
PLj,i 画素部(容量性メモリセル)
CP 補正パルス
SP 走査パルス
Vdata データ電圧
Wj 信号線(補正パルス供給部)
Xi データ線
Yj 走査線
Z′ 電源線
Claims (12)
- マトリクス状に配置された走査線及びデータ線の交差位置に多数の容量性メモリセルが配置されたアクティブマトリクス型モジュールであって、
前記容量性メモリセルは、
前記走査線に接続されたゲート電極、及び前記データ線に接続されたソース電極を有する第1トランジスタと、
一方側の第1端子が前記第1トランジスタのドレイン電極に接続され、前記走査線より前記ゲート電極に走査パルスが供給された際に、前記データ線より前記ソース電極及び前記ドレイン電極を介して供給されるデータ電圧に応じて電荷を蓄積する容量素子と、を有しており、
前記走査パルスとは逆極性である補正パルスを、前記走査パルスの供給タイミングに応じたタイミングで前記容量性メモリセルに供給する補正パルス供給部を設けた
ことを特徴とするアクティブマトリクス型モジュール。 - 請求項1記載のアクティブマトリクス型モジュールにおいて、
前記容量性メモリセルは、
前記第1トランジスタのドレイン電極に接続されると共に、前記容量素子の前記第1端子に接続されたゲート電極を有する第2トランジスタと、
前記第2トランジスタのドレイン電極にアノードが接続された発光素子と、を有している
ことを特徴とするアクティブマトリクス型モジュール。 - 請求項1又は請求項2記載のアクティブマトリクス型モジュールにおいて、
前記容量素子は、
他方側の第2端子を有しており、
前記補正パルス供給部は、
前記第2端子を介し前記容量素子に対して前記補正パルスを供給する
ことを特徴とするアクティブマトリクス型モジュール。 - 請求項3記載のアクティブマトリクス型モジュールにおいて、
前記補正パルス供給部は、
前記走査線に沿って配置された複数の前記容量性メモリセルに係る前記容量素子の前記第2端子に接続されると共に、前記走査線とほぼ平行に配置され、前記走査線と1対1に対応するように当該走査線と同数設けられた信号線を有している
ことを特徴とするアクティブマトリクス型モジュール。 - 請求項2又は請求項3記載のアクティブマトリクス型モジュールにおいて、
前記補正パルス供給部は、
前記第2トランジスタのソース電極に接続された電源線を有しており、
当該電源線を介し、前記容量素子または前記第2トランジスタに対して前記補正パルスを供給する
ことを特徴とするアクティブマトリクス型モジュール。 - 請求項1乃至請求項5のいずれかに記載のアクティブマトリクス型モジュールにおいて、
前記補正パルス供給部は、
前記補正パルスのオフタイミングが、前記走査パルスのオフタイミング以後となるように、前記補正パルスを前記容量素子に対して供給する
ことを特徴とするアクティブマトリクス型モジュール。 - 請求項1乃至請求項6のいずれかに記載のアクティブマトリクス型モジュールにおいて、
前記補正パルスは、前記走査パルスを論理的に位相反転することにより生成されており、
前記補正パルス供給部は、
前記補正パルスのオン・オフタイミングが、前記走査パルスのオン・オフタイミングと同時となるように、前記補正パルスを前記容量素子に対して供給する
ことを特徴とするアクティブマトリクス型モジュール。 - 請求項1乃至請求項7のいずれかに記載のアクティブマトリクス型モジュールにおいて、
前記補正パルスの振幅を調整可能なパルス振幅調整手段を有する
ことを特徴とするアクティブマトリクス型モジュール。 - 請求項1乃至請求項8のいずれかに記載のアクティブマトリクス型モジュールにおいて、
前記第1トランジスタ及び前記第2トランジスタの前記ゲート電極、前記ソース電極、及び前記ドレイン電極は、ウェットプロセスにより形成されている
ことを特徴とするアクティブマトリクス型モジュール。 - 請求項1乃至請求項9のいずれかに記載のアクティブマトリクス型モジュールにおいて、
前記第1トランジスタ及び前記第2トランジスタは、有機半導体層を有する有機薄膜トランジスタである
ことを特徴とするアクティブマトリクス型モジュール。 - 請求項1乃至請求項10のいずれかに記載のアクティブマトリクス型モジュールにおいて、
アクティブマトリクス型表示パネルである
ことを特徴とするアクティブマトリクス型モジュール。 - 走査線に接続されたゲート電極、及びデータ線に接続されたソース電極を有する第1トランジスタと、一方側の第1端子が前記第1トランジスタのドレイン電極に接続され、前記走査線より前記ゲート電極に走査パルスが供給された際に、前記データ線より前記ソース電極及び前記ドレイン電極を介して供給されるデータ電圧に応じて電荷を蓄積する容量素子と、を有する多数の容量性メモリセルを、マトリクス状に配置した前記走査線及び前記データ線の交差位置に配置したアクティブマトリクス型モジュールの駆動方法であって、
前記走査線より前記ゲート電極に前記走査パルスを供給する走査パルス供給手順と、
前記走査パルスとは逆極性である補正パルスを、前記走査パルスの供給タイミングに応じたタイミングで前記容量性メモリセルに供給する補正パルス供給手順と、を有する
ことを特徴とするアクティブマトリクス型モジュールの駆動方法。
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US13/509,706 US20120274615A1 (en) | 2009-11-13 | 2009-11-13 | Active matrix type module and driving method of active matrix type module |
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Cited By (3)
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TWI455105B (zh) * | 2012-01-16 | 2014-10-01 | Innocom Tech Shenzhen Co Ltd | 顯示面板 |
JP2018159885A (ja) * | 2017-03-24 | 2018-10-11 | シナプティクス インコーポレイテッド | 電流駆動表示パネル及びパネル表示装置 |
JP2023503149A (ja) * | 2020-10-12 | 2023-01-26 | 北京集創北方科技股▲ふん▼有限公司 | 駆動装置及び電子機器 |
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JP5779656B2 (ja) * | 2011-10-14 | 2015-09-16 | 株式会社Joled | 画像表示装置 |
CN108777130A (zh) * | 2018-06-21 | 2018-11-09 | 京东方科技集团股份有限公司 | 像素电路及显示装置 |
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