WO2011050623A1 - 图案化方法 - Google Patents

图案化方法 Download PDF

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Publication number
WO2011050623A1
WO2011050623A1 PCT/CN2010/074592 CN2010074592W WO2011050623A1 WO 2011050623 A1 WO2011050623 A1 WO 2011050623A1 CN 2010074592 W CN2010074592 W CN 2010074592W WO 2011050623 A1 WO2011050623 A1 WO 2011050623A1
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Prior art keywords
film
photoresist
mask
photoresist mask
etching
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PCT/CN2010/074592
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English (en)
French (fr)
Inventor
徐秋霞
周华杰
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中国科学院微电子研究所
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Priority to US12/922,944 priority Critical patent/US8338084B2/en
Publication of WO2011050623A1 publication Critical patent/WO2011050623A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

Definitions

  • the present invention is a patterning method for nanoscale semiconductor device fabrication, and more particularly to a patterning method in which a positive electron beam photoresist is used.
  • An object of the present invention is to provide a patterning method using a photoresist to overcome the problem that a positive electron beam resist such as Zep 520 cannot be subjected to fluorine-based reactive ion etching.
  • the present invention provides a patterning method comprising the following steps:
  • the invention can make the fine pattern prepared by the electronic germanium direct writing lithography Zep 520 glue can be retained in the medium, firstly forming the p 520 glue on the a-Si, so that a chlorine (C1) based plasma engraving can be used.
  • Eclipse a-Si The Zep 520 glue pattern is first transferred to the a-Si, then the Zep 520 glue is removed, the medium is masked with the ot-Si pattern, and the dielectric etching is performed in the fluorine-based reactive ion etching to obtain a nano-scale groove pattern, and finally wet.
  • the method or dry method can remove ⁇ -Si.
  • oc-Si is used as the intermediate transition layer, and the chlorine-based plasma etching is used.
  • the pattern of the photoresist mask is transferred to the a-Si. Because a-Si is easily etched by chlorine-based plasma, and the etching precision is high.
  • the high-resolution a-Si pattern is transferred into the medium by reactive ion etching in a fluorine-based layer, because in the fluorine-based reactive ion etching, the dielectric film has a very large a-Si film.
  • a high etching selectivity ratio ensures the preparation of fine patterns.
  • the removal of the a-Si film, whether wet or dry, has a very low rate of corrosion to the medium and does not cause damage to the dielectric pattern.
  • Figure 1 shows a SEM cross-section of a Zep 520 electron beam positive photoresist after etching a medium in a fluorine-based plasma. Zep 520 plastically flows and destroys, and the medium cannot continue etching.
  • Figure 2 shows a cross-sectional photograph of a fluorine-based reactive ion etching medium using a-Si as a mask.
  • the dielectric groove pattern is intact and the three layers of dielectric are etched.
  • the invention overcomes the method that the electron beam positive photoresist Zep 520 cannot mask the dielectric etching.
  • the process steps as an example are as follows:
  • a layer of a-Si film is deposited on the medium to be processed.
  • the a-Si film has a thickness of 120-150 nm and a deposition temperature of 520-550 o C.
  • the ⁇ -Si film was etched by using a chlorine-based plasma with Zep 520 as a mask pattern, and the Zep 520 glue pattern was transferred to the ⁇ -Si film with high fidelity.
  • a chlorine-based plasma is a mixed gas source of Cl 2 /He, Cl 2 /Ar, or Cl 2 /0 2
  • the dielectric layer is etched in the fluorine-based reactive ion, and the a-Si pattern is transferred to the medium with high fidelity.
  • the fluorine-based reactive ionomer is CF 4 , CHF 3 , C 3 F 8 , C 4 F 8 , NF 3 or a mixed gas source thereof, for example, a CF 4 /CHF 3 mixed gas.
  • the ex-Si is removed, and the fine pattern of the nano-scale grooves in the medium is processed.
  • a-Si is removed by a dry method using a chlorine-based plasma or a wet method using an aqueous solution of NH 4 OH.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)

Description

图案化方法 技术领域
本发明属于图案化方法， 用于纳米尺度的半导体器件制备， 具体涉及其中使用正 性电子束光刻胶的图案化方法。 技术背景
在亚 50纳米 CMOS集成技术进一步等比例缩小的发展中，为克服平面体硅 CMOS 固有的越来越严重的短沟道效应和大的漏电流问题，新器件结构层出不穷，如 FinFET, 多栅 /环栅 CMOS FET， 纳米线等， 在这些新结构器件的制备过程中， 必然会遇到要在 介质中刻蚀出较深的纳米尺度的凹槽图案。 要得到这么窄的凹槽， 首先需要有高分辨 率的电子朿光刻胶。 Zep520正性电子束光刻胶（可购自 Nippon Zeon Co. Ltd)是首选， 采用这种胶的电子束直写光刻可以得到高分辨的纳米尺度的光刻胶掩膜图案。 但采用 这种胶其在常规的介质刻蚀工艺中抗刻蚀性能很差， 它很快地与氟（F )基等离子体反 应， 而发生塑性流动， 使凹槽胶图案严重毁坏。 发明内容
本发明的目的在于提供一种使用光刻胶的图案化方法， 以克服例如 Zep 520的正 性电子束光刻胶不能经受氟基反应离子刻蚀的问题。
为实现上述目的， 本发明提供一种图案化方法， 包括以下步骤：
1 ) 在需要加工的介质上沉积一层 α-Si薄膜；
2 ) 在 α-Si薄膜上形成含有图案的光刻胶掩膜；
3 ) 利用光刻胶掩膜， 采用氯基等离子体刻蚀 α-Si 膜， 使光刻胶掩膜的图案转移 到 α-Si膜上；
4 ) 去除光刻胶掩膜；
5 ) 以 a- Si薄膜作为硬掩膜， 在氟基反应离子体中刻蚀介质层， 使 ot-Si薄膜的图 案转移到介质中；
6 ) 去除 a-Si薄膜。
本发明为使电子朿直写光刻 Zep 520胶制备的精细图案能在介质中保留下来， 首 先让 p 520胶成形在 a-Si上， 这样就可以采用一种 氯 ( C1 ) 基等离子体刻蚀 a-Si， 使 Zep 520胶图案首先转移到 a- Si上， 然后去掉 Zep 520胶， 用 ot-Si图案掩蔽介质， 在氟基反应离子刻蚀中完成介质刻蚀， 得到纳米尺度凹槽图案， 最后用湿法或干法去 掉 α-Si即可。
本发明的效果在于：
为克服例如 Zep 520的光刻胶掩膜不抗氟基刻蚀的问题， 根据光刻胶掩膜耐氣基 刻蚀的特性， 利用 oc-Si作为中间过渡层， 用氯基等离子刻蚀将光刻胶掩膜的图案转移 到 a- Si上。 因为 a- Si容易被氯基等离子体刻蚀， 而且刻蚀精度高。
利用 c -Si作为硬掩膜，采用氟基中反应离子刻蚀将高分辨率的 a-Si图案转移到介 质中， 因为在氟基反应离子刻蚀中， 介质膜对 a-Si膜有很高的刻蚀选择比， 这样就能 保证精细图案的制备。
a-Si膜的去除不论是湿法还是干法， 对介质的腐蚀速率极低， 不会对介质图案造 成损伤。
这种方法由于与常规的 CMOS工艺完全兼容， 方便可靠， 而且能获得精细的纳米 尺度凹槽图案， 解决了新结构 CMOS器件制备中的一大难题。 附图说明
图 1 给出了 Zep 520电子束正性光刻胶在氟基等离子体中刻蚀介质后的 SEM剖面 照片， Zep 520胶塑性流动并毁坏， 介质没法继续刻蚀下去。
图 2 给出了以 a-Si为掩膜用氟基反应离子刻蚀介质后剖面照片，介质凹槽图案完 好， 三层介质已刻蚀净。
图 1中： 1 Zep 520 子束正胶； 2—介质膜； 3—硅衬底。
图 2中：： 〗— a-SU ; 2—介质膜； 3 硅衬底。 具体实施方式
本发明一种克服电子束正性光刻胶 Zep 520不能掩蔽介质刻蚀的方法， 作为示例 的工艺步骤如下：
在需要加工的介质上沉积一层 a-Si薄膜， a-Si 膜厚度 120— 150纳米， 沉积温度 520— 550oC。
清洗， 甩千， 并在 N2保护下 800度高温炉口烘 30分钟。
旋涂 Zep 520电子朿正性光刻胶， 胶厚度 400— 600纳米。 在烘箱内烘烤， 度 170— 180°C， 20— 40分钟， 需要缓慢升降温。
电子束直写曝光并显影后， 得到高分辨率 Zep 520胶纳米尺度凹槽图案。
烘烤 130— 140°C， 30-50分钟。
采用氯基等离子体， 以 Zep 520胶为掩膜图案， 刻蚀 α-Si膜， 使 Zep 520胶图案 高保真度地转移到 α-Si膜上。 例如， 氯基等离子体为 Cl2/He、 Cl2/Ar、 或 Cl2/02的混 合气体源
去除 Zep 520 正性电子朿胶。 例如， 采用使用 02等离子体的千法、 或使用 H2S04:H202=3: 1 -5:3的溶液的湿法去除光刻胶掩膜。
以 a-Si膜为掩膜图案， 在氟基反应离子体中刻蚀介质层， 使 a-Si图案高保真度地 转移到介质中。 氟基反应离子体为 CF4、 CHF3、 C3F8、 C4F8、 NF3或其混合气源， 例如 CF4/CHF3混合气体。
去除 ex-Si, 完成了介质中纳米尺度凹槽精细图案的加工。 例如， 采用使用氯基等 离子体的干法， 或使用 NH4OH的水溶液的湿法去除 a-Si。

Claims

权 利 要 求
1、 一种图案化方法， 包括以下歩骤：
1 ) 在需要加工的介质上沉积一层 ot-Si薄膜；
2 ) 在 α-Si薄膜上形成含有图案的光刻胶掩膜；
3 ) 利用光刻胶掩膜， 采用氯基等离子体刻蚀（x-Si 膜， 使光刻胶掩膜的图案转移 到 α-Si膜上；
4) 去除光刻胶掩膜；
5 ) 以 a-Si薄膜作为硬掩膜， 在氟基反应离子体中刻蚀介质层， 使 ot-Si薄膜的图 案转移到介质中；
6) 去除 ot-Si薄膜。
2、 根据权利要求 1所述的方法， 其中在步骤 1 ) 中， 沉积温度为 520— 550° C。
3、 根据权利要求 1所述的方法， 其中步骤 2) 包括
a) 在 ot-Si薄膜上旋涂光刻胶层；
b) 在 170— 180° C烘烤光刻胶层达 20— 40分钟；
c) 对光刻胶层进行电子束直写曝光；
d) 对光刻胶层进行显影， 以得到含有图案的光刻胶掩膜；
e) 在 130— 140 ° C烘烤光刻胶掩膜达 30— 50分钟。
4、 根据权利要求 1所述的方法， 其中所述光刻胶为正性电子束光刻胶 Zep 520。
5、 根据权利要求 1所述的方法， 其中， 在步骤 1 ) 中， （X- Si膜厚度根据被刻蚀的 介质膜的厚度和膜质在 70— 200纳米之间选择。
6、 根据权利要求 1所述的方法， 其中， 在步骤 2) 中， 光刻胶掩膜的膜厚度根据 α-Si膜厚度在 200— 600纳米之间选择。
7、 根据权利要求 1所述的方法， 其中， 在步骤 3 ) 中， 氯基等离子体为 Cl2/He、 Cl2/Ar、 或 Cl2/02的混合气体源。
8、 根据权利耍求 1所述的方法， 其中， 在步骤 4) 中， 采用使用 02等离子体的 干法、 或使用 H2S04:H202=3:1— 5:3溶液的湿法去除光刻胶掩膜。
9、 根据权利要求 1所述的方法， 其中， 在步骤 5 ) 中， '弗 (基反应离子体为 CF4、 CHF3、 C3F8、 C4F8、 NF3或其混合气源。
10、 根据权利要求 1所述的方法， 其中， 在步骤 6) 中， 采用使用氯基等离子体 的干法， 或使用 NH4OH水溶液的湿法去除 α-Si薄膜。
PCT/CN2010/074592 2009-10-28 2010-06-28 图案化方法 WO2011050623A1 (zh)

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CN2009102367194A CN102054668B (zh) 2009-10-28 2009-10-28 电子束正性光刻胶Zep 520掩蔽介质刻蚀的方法

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CN104037061B (zh) * 2014-06-07 2016-08-03 北京工业大学 湿环境下电子束直接纳米刻蚀或印刷的方法

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US20110200947A1 (en) 2011-08-18
US8338084B2 (en) 2012-12-25
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