WO2011048847A1 - 液晶表示装置 - Google Patents
液晶表示装置 Download PDFInfo
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- WO2011048847A1 WO2011048847A1 PCT/JP2010/060556 JP2010060556W WO2011048847A1 WO 2011048847 A1 WO2011048847 A1 WO 2011048847A1 JP 2010060556 W JP2010060556 W JP 2010060556W WO 2011048847 A1 WO2011048847 A1 WO 2011048847A1
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- liquid crystal
- auxiliary capacitance
- crystal display
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
- G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
- G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133391—Constructional arrangement for sub-divided displays
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/04—Maintaining the quality of display appearance
- G09G2320/041—Temperature compensation
Definitions
- the present invention relates to a liquid crystal display device that applies a voltage to an auxiliary capacitance line connected to an auxiliary capacitance in a pixel.
- a large liquid crystal display panel represented by a liquid crystal display panel for a liquid crystal TV manufacturing variations such as line width and film thickness of the TFT substrate may occur in one liquid crystal display panel.
- manufacturing variations such as line width and film thickness of the TFT substrate may occur in one liquid crystal display panel.
- gradation variations caused by variations in the electrical characteristics and capacitance of the TFTs may occur with a distribution in the plane of the liquid crystal display panel.
- the generated gradation variation is visually recognized as a partial luminance difference in the plane of the liquid crystal display panel as shown in FIG.
- Patent Document 1 discloses a technique for reducing gradation variation by adjusting a voltage applied to an auxiliary capacitor by an adjustment circuit (power supply circuit 9). This point will be described with reference to FIG.
- FIG. 10 shows the liquid crystal display device of FIG.
- a two-terminal element 5 capable of changing the conduction / non-conduction state from the outside
- the power supply circuit 9 has a pixel electrode and a counter electrode according to the conduction / non-conduction state of the two-terminal element 5.
- the voltage applied to the liquid crystal layer can be easily adjusted. Flicker can be reduced when the voltage Vcom applied to the counter electrode is adjusted according to the state of the two-terminal element 5, and gradation variation can be reduced when the voltage Vcs applied to the auxiliary capacitor is adjusted.
- Patent Document 1 a case where the technique of Patent Document 1 is applied to a liquid crystal display device having a general configuration will be described with reference to FIG.
- FIG. 11 is a block diagram of a conventional liquid crystal display device 101.
- the liquid crystal display device 101 includes a liquid crystal display panel 102, signal lines S1, S2,... S (n-1), a signal line driving circuit 103 for driving Sn, and scanning lines G1, G2,. , Gm, the scanning line driving circuit 104, the control circuit 106, and the auxiliary capacitance lines CSH1, CSH2,... CSH (p ⁇ 1), CSHp and the auxiliary capacitance line CSL1 connected to the auxiliary capacitance in the pixel PIX. , CSL2,... CSL (q-1), storage capacitor line driving circuit 107 for driving CSLq.
- the signal line driver circuit 103, the scanning line driver circuit 104, and the control circuit 106 constitute a display driver.
- the signal lines S1, S2,... S (n-1), Sn have one signal for each pixel column including a plurality of pixels PIX provided in the column direction when the extending direction of the signal line is the column direction.
- a line is arranged.
- one scanning line G1, G2,... G (m ⁇ 1), Gm is provided for each pixel row including a plurality of pixels PIX provided in the row direction when the extending direction of the scan line is the row direction. Scanning lines are arranged.
- the pixel PIX has a TFT (not shown) and two subpixels.
- the gates of the TFTs are connected to the scanning lines G1, G2,... G (m-1), Gm, and the sources of the TFTs are connected to the signal lines S1, S2, ... S (n-1), Sn.
- one subpixel is connected to the drain of the TFT, and the one subpixel and the other subpixel are connected via a coupling capacitor.
- the auxiliary capacitance lines CSH1, CSH2,... CSH (p-1), CSHp correspond to the one sub-pixel, and the auxiliary capacitance lines CSL1, CSL2, ... CSL (q-1), CSLq It corresponds to the sub-pixel.
- each pixel PIX is provided with two subpixels. However, one or three or more subpixels may be provided, and one auxiliary capacitance line corresponding to the subpixel may be provided. Three or more may be sufficient.
- the auxiliary capacitance line drive circuit 107 applies voltages to the auxiliary capacitance lines CSH1, CSH2,... CSH (p ⁇ 1), CSHp, and the auxiliary capacitance lines CSL1, CSL2,. By adjusting the voltage applied to (q-1) and CSLq, gradation variation can be reduced.
- Japanese Patent Publication Japanese Patent Laid-Open No. 2006-235593 (published on September 7, 2006)
- Patent Document 1 the prior art disclosed in Patent Document 1 is difficult to apply to a split drive type liquid crystal display device that divides the liquid crystal display panel surface into a plurality of regions and drives each region.
- the panel characteristics TFT electrical characteristics, capacitance, etc.
- Luminance unevenness which is a partial luminance difference in the plane, is visually recognized.
- the single voltage Vcs applied to the auxiliary capacitor is adjusted as shown in Patent Document 1 in such a state where the luminance unevenness is visually recognized, only the gradation is shifted in the entire liquid crystal display panel. . Therefore, in the technique of Patent Document 1, in the split drive type liquid crystal display device, the effect of reducing the gradation variation occurring in the plane of the liquid crystal display panel cannot be sufficiently obtained, and the visibility of luminance unevenness cannot be prevented. .
- the present invention has been made in view of the above-described problems, and an object of the present invention is to eliminate luminance unevenness due to gradation variations generated in the plane of the liquid crystal display panel even in a split drive type liquid crystal display panel. An object of the present invention is to provide a liquid crystal display device that can be used.
- the liquid crystal display device of the present invention is an active matrix liquid crystal display device including a storage electrode that forms a capacitor and a pixel electrode included in a pixel.
- the storage capacitor line is divided into a plurality of adjacent storage capacitor lines for each display region, and the storage capacitor voltage applied to the storage capacitor line is individually set for each display region. It is characterized by being.
- the storage capacitor voltage applied to the storage capacitor line is individually set for each display area. That is, the auxiliary capacitance voltage applied to the auxiliary capacitance line can be increased or decreased (finely adjusted) for each display area.
- the effective voltage applied to the liquid crystal capacitance can be made uniform, and variations in the amount of charge charged in the liquid crystal capacitance can be eliminated.
- the display area is divided in accordance with gradation variations displayed on the display panel when the signal potentials supplied to all the pixel electrodes are the same.
- the liquid crystal display device of the present invention forms a plurality of display areas obtained by dividing the display screen, and the auxiliary capacity line is divided into a plurality of adjacent auxiliary capacity lines for each display area.
- the auxiliary capacitance voltage applied to the line is set individually for each display area.
- 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.
- 1 is a block diagram of a storage capacitor line driving circuit according to an embodiment of the present invention. It is a graph which shows the measurement result of the upper CSH voltage and the lower CSH voltage. It is explanatory drawing that the brightness nonuniformity is eliminated in the liquid crystal display device which concerns on the Example of this invention, (a) is a figure which shows that the brightness nonuniformity has arisen in the conventional liquid crystal display device, (b) ) Is a diagram showing that luminance unevenness is eliminated in the liquid crystal display device according to the embodiment of the present invention. It is a block diagram of the liquid crystal display device which concerns on the other Example of this invention.
- FIG. 4 is an explanatory diagram showing that uneven brightness occurs due to gradation variations in the liquid crystal display panel surface.
- FIGS. 4A to 4E are brightness unevenness caused by gradation variations in the liquid crystal display panel surface.
- FIG. 1 is a block diagram of the liquid crystal display device 1 according to the first embodiment.
- the liquid crystal display device 1 includes a liquid crystal display panel 2, a signal line (source line, each signal line) S1, S2,... S (n-1), Sn, a signal line drive circuit 3 (signal line drive unit), , Scanning lines (gate lines, scanning lines, first scanning lines, second scanning lines, scanning lines) G1, G2,... G (m ⁇ 1), Gm, scanning line driving circuit 4 (scanning lines) Drive capacitor), control circuit 6, and auxiliary capacitance lines CSH1, CSH2,... CSH (p-1), CSHp and auxiliary capacitance lines CSL1, CSL2,. -1), and auxiliary capacitance line drive circuits (auxiliary capacitance line drive units) A and B for driving CSLq.
- the signal line driving circuit 3, the scanning line driving circuit 4, and the control circuit 6 constitute a display driver.
- the signal lines S1, S2,... S (n-1), Sn have one signal for each pixel column including a plurality of pixels PIX provided in the column direction when the extending direction of the signal line is the column direction.
- a line is arranged.
- one scanning line G1, G2,... G (m ⁇ 1), Gm is provided for each pixel row including a plurality of pixels PIX provided in the row direction when the extending direction of the scan line is the row direction. Scanning lines are arranged.
- a liquid crystal display panel 2 which is an active matrix type liquid crystal display panel provided with a pixel electrode included in the pixel PIX and an auxiliary capacitance line that forms a capacitance, has pixels (liquid crystal cells) PIX arranged in a matrix and has an upper screen MU. (Display area, first display area) and lower screen MD (display area, second display area).
- the pixel PIX has a TFT (not shown) and two subpixels.
- the gates of the TFTs are connected to scanning lines (gate lines) G1, G2,... G (m ⁇ 1), Gm extending so as to pass through the upper screen MU or the lower screen MD.
- one subpixel is connected to the drain of the TFT, and the one subpixel and the other subpixel are connected via a coupling capacitor.
- the auxiliary capacitance lines CSH1, CSH2,... CSH (p-1), CSHp correspond to the one sub-pixel, and the auxiliary capacitance lines CSL1, CSL2, ...
- CSL (q-1), CSLq It corresponds to the sub-pixel. Therefore, uneven brightness can be eliminated in the liquid crystal display panel 2 in which the pixel PIX has two subpixels.
- the auxiliary capacitance lines CSH1, CSH2,... CSH (p-1), CSHp and the auxiliary capacitance lines CSL1, CSL2,... CSL (q-1), CSLq extend so as to pass through the upper screen MU or the lower screen MD.
- auxiliary capacitance lines are arranged on the pixel PIX having two subpixels.
- one or three or more auxiliary capacitance lines may be connected to the pixel PIX having one or three or more subpixels.
- the signal line drive circuit 3 is a circuit that supplies image data to the pixels PIX to which image data is to be supplied through the signal lines S1, S2,... S (n-1), Sn.
- the scanning line driving circuit 4 selects the pixels PIX to which image data is to be supplied through the scanning lines G1, G2,... G (m ⁇ 1), Gm.
- the control circuit 6 generates various signals to be supplied to the signal line driving circuit 3 and the scanning line driving circuit 4.
- the wiring inside the liquid crystal display panel 2 is not divided on the way. Specifically, the nth signal line Sn can be supplied to the pixel PIXn farthest from the signal line driving circuit 3 without being divided in the middle. Similarly, the mth scanning line Gm can be selected up to the pixel PIXn farthest from the scanning line driving circuit 4 without being divided in the middle.
- the liquid crystal display panel 2 is referred to as a liquid crystal display panel that is not divided and driven.
- the liquid crystal display device 1 includes a plurality of storage capacitor line drive circuits.
- the liquid crystal display device 1 includes two storage capacitor line drive circuits A and B, but may include three or more storage capacitor line drive circuits.
- the terminal ends of the auxiliary capacitance lines CSH1, CSH2,... CSH (p-1), CSHp are open.
- the ends of the auxiliary capacitance lines CSL1, CSL2,... CSL (q-1), CSLq are open.
- a gradation variation boundary appears prominently before the auxiliary capacitance voltage is set. Therefore, it becomes easy to specify the auxiliary capacitance line for which the auxiliary capacitance voltage is to be set, and the effect of adjustment by increasing or decreasing the auxiliary capacitance voltage is enhanced.
- the terminal ends of the auxiliary capacitance lines CSH1, CSH2,... CSH (p ⁇ 1), CSHp are connected to each other inside the liquid crystal display panel 2. Also good.
- the terminal ends of the auxiliary capacitance lines CSL 1, CSL 2,... CSL (q ⁇ 1), CSLq may be connected to each other inside the liquid crystal display panel 2.
- the auxiliary capacity line drive circuits A and B are configured such that the other output voltage can be finely adjusted (increased or decreased) based on one output voltage.
- the output voltage of the auxiliary capacitance line drive circuit B (the other auxiliary capacitance line drive unit) is finely set with reference to the output voltage of the auxiliary capacitance line drive circuit A (one auxiliary capacitance line drive unit). You can adjust.
- the output voltage of the auxiliary capacitance line driving circuit A can be finely adjusted based on the output voltage of the auxiliary capacitance line driving circuit B.
- the liquid crystal display device 1 is, for example, a 37/46/52/65 type liquid crystal TV and the liquid crystal display panel 2 has a large area, capacitance generated by wiring inside the liquid crystal display panel 2 and wiring resistance inside the liquid crystal display panel 2 Etc. are not uniform and distributed within the liquid crystal display panel 2. For this reason, when the halftone solid screen display on the low gradation side is performed, the gradation variation may be visually recognized as luminance unevenness.
- the cause of the uneven brightness is thought to be due to variations in the amount of charge charged to the liquid crystal capacitor.Therefore, the voltage applied to the auxiliary capacitor line is finely adjusted to align the effective voltage applied to the liquid crystal capacitor. The above-described variation in the charge amount is eliminated.
- auxiliary capacitance line drive circuits In order to finely adjust the voltage applied to the auxiliary capacitance line, a plurality of auxiliary capacitance line drive circuits are provided as shown in FIG. 1, and each of the auxiliary capacitance line drive circuits outputs a different voltage value to the corresponding auxiliary capacitance line. Make it possible. Since the adjustment value of the voltage applied to the auxiliary capacitance line is very small, adjustment is easy if the circuit configuration is such that one of the voltages applied to the two auxiliary capacitance lines is relatively finely adjusted with respect to the other. .
- the internal wiring of the liquid crystal display panel 2 has a resistance value of about several tens to several k ⁇ , but the terminal ends of the auxiliary capacitance lines in the liquid crystal display panel 2 may be connected to each other. According to this configuration, since the wiring resistance of each auxiliary capacitance line can be made uniform, the gradation variation near the boundary between the upper screen MU and the lower screen MD can be further reduced.
- auxiliary capacitance line in which one auxiliary capacitance line is arranged corresponding to one pixel PIX, all the auxiliary capacitance lines are connected to each other, and two auxiliary capacitance lines are arranged corresponding to one pixel PIX.
- the auxiliary capacitance lines to which the High side potential is supplied are connected to each other, and the auxiliary capacitance lines to which the Low side potential is supplied are connected to each other.
- the potential output from the auxiliary capacity line driving circuit B is also supplied to the auxiliary capacity lines of the upper screen MU.
- the auxiliary capacitance of the pixel and the pixel potential partially vary.
- the internal wiring of the liquid crystal display panel 2 has a resistance value of about several tens to several k ⁇ , and the resistance value of the internal wiring is different for each pixel PIX. Therefore, even if the terminal ends of the auxiliary capacitance lines in the liquid crystal display panel 2 are connected to each other, the auxiliary capacitance lines are not at the same potential.
- the internal wiring of the liquid crystal display panel 2 has a resistance value of about several tens to several k ⁇ . Therefore, the potential of each pixel PIX has a gradient in the plane of the liquid crystal display panel 2.
- the potential of each pixel PIX is balanced and stable with the above gradient. The same applies to the case where a rectangular wave is applied to the storage capacitor line, and the potential of each pixel PIX in a stable state has the above-described gradient.
- FIG. 2 is a block diagram of the auxiliary capacitance line driving circuits A and B according to the first embodiment.
- the upper and lower two screens MU and MD may be equally divided in a direction perpendicular to the extending direction of the auxiliary capacity line.
- the boundary between the two continuous upper and lower screens MU and MD is evenly arranged in parallel with the extending direction of the auxiliary capacity line.
- the display screen of the liquid crystal display panel 2 may be equally divided as long as it is equally divided in the direction perpendicular to the extending direction of the auxiliary capacitance line.
- the display screen of the liquid crystal display panel 2 is equally divided into five in the direction perpendicular to the extending direction of the auxiliary capacitance line, five auxiliary capacitance line driving circuits may be provided.
- the voltages VCSH1 to VCSH12 (auxiliary capacitance voltages) output from the auxiliary capacitance lines CSH1 to CSH12 corresponding to the upper screen MU are referred to as upper CSH voltages.
- the voltages VCSH13 to VCSH24 (auxiliary capacitance voltage) output from the auxiliary capacitance lines CSH13 to CSH24 corresponding to the lower screen MD are referred to as lower CSH voltages.
- voltages VCSL1 to VCSL12 (auxiliary capacitance voltages) output from the auxiliary capacitance lines CSL1 to CSL12 corresponding to the upper screen MU are referred to as upper CSL voltages.
- the voltages VCSL13 to VCSL24 (auxiliary capacitance voltage) output from the auxiliary capacitance lines CSL13 to CSL24 corresponding to the lower screen MD are referred to as lower CSL voltages.
- the value of the upper CSH voltage and the value of the lower CSH voltage are different, and the value of the upper CSL voltage and the value of the lower CSL voltage are different.
- the differential amplifier circuit ACSL ' In the differential amplifier circuit ACSL ', the upper CSL voltage is input to the non-inverting input terminal and the lower CSL voltage is output. The output of the differential amplifier circuit ACSL 'is connected to the inverting input terminal of the differential amplifier circuit ACSL'. As a result, the fixed lower CSL voltage is output to each auxiliary capacitance line.
- the lower CSH voltage adjustment circuit 7 includes resistors R1, R3, R4, a resistance value adjustment unit R2, a differential amplifier circuit 8, a reference voltage circuit 10, a temperature correction circuit 11, and an addition circuit 12.
- the resistance value at both ends of the resistance value adjusting unit R2 is R-DCP.
- the reference voltage circuit 10 includes a resistor R5 and a resistor R6.
- the adder circuit 12 includes a differential amplifier circuit Adiff.
- the resistance value adjusting unit R2 only needs to be capable of adjusting the voltage by adjusting the resistance value.
- a semi-fixed resistor, a variable resistor, or a digital potentiometer can be used. Note that the digital potentiometer need not be a digital IC.
- the power supply voltage VLS is applied to one end of the resistor R1.
- the power supply voltage VLS is 15.6V, for example.
- the other end of the resistor R1, one end of the resistor R3, and one end of the resistance value adjusting unit R2 are connected to the node bar RH.
- the other end of the resistor R3, the other end of the resistance value adjustment unit R2, one end of the resistor R4, and the inverting input terminal of the differential amplifier circuit 8 are connected to the node bar RL.
- the output of the differential amplifier circuit 8 is connected to the node bar RL via the feedback resistor Rf.
- the other end of the resistor R4 is electrically grounded.
- the non-inverting input terminal of the differential amplifier circuit 8 is connected to the control input (node bar RW) of the resistance value adjustment unit R2.
- the signal source resistance Rs is set to 30 k ⁇ , for example, and the feedback resistance Rf is set to 3 k ⁇ , for example.
- the upper CSH voltage is applied to one end of the resistor R5.
- the other end of the resistor R5 is connected to one end of the resistor R6, the output of the differential amplifier circuit 8, and the non-inverting input terminal of the differential amplifier circuit Adiff.
- the other end of the resistor R6 is connected to one end of the temperature correction circuit 11, and the other end of the temperature correction circuit 11 is electrically grounded.
- the temperature correction circuit 11 is, for example, a 0 ⁇ resistor.
- the output of the differential amplifier circuit Adiff is connected to the inverting input terminal of the differential amplifier circuit Adiff through the feedback resistor Rf ′, and the inverting input terminal of the differential amplifier circuit Adiff is electrically grounded. .
- the input resistance Ri and the feedback resistance Rf ' are set to 10 k ⁇ , for example.
- the adding circuit 12 includes a reference voltage Vref obtained by dividing the upper CSH voltage by the resistors R5 and R6, and a minute voltage Vm output from the differential amplifier circuit 8. Is added to generate the lower CSH voltage.
- Vref a reference voltage obtained by dividing the upper CSH voltage by the resistors R5 and R6, and a minute voltage Vm output from the differential amplifier circuit 8. Is added to generate the lower CSH voltage.
- the auxiliary capacitance line drive circuits A and B can finely adjust (increase / decrease) the other output voltage with reference to one output voltage.
- a subtracting circuit may be used.
- the minute voltage Vm is preferably about ⁇ 0.025% when the reference voltage Vref is 100%. As an example, if the reference voltage Vref is about 8V, the minute voltage Vm is preferably about 2 mV. This is because the variation in gradation within the surface of the liquid crystal display panel 2 is very small.
- FIG. 3 is a graph showing measurement results of the upper CSH voltage and the lower CSH voltage.
- the vertical axis of the graph represents voltage, and the unit is volts.
- the horizontal axis of the graph indicates the number of steps of the digital potentiometer when the resistance value adjustment unit R2 is a 128-step digital potentiometer (device).
- the graph of FIG. 3 shows the result of measuring the upper CSH voltage and the lower CSH voltage every 10 steps, and the lower CSH voltage is increased or decreased with a resolution of 128 steps (within range).
- the value of the upper CSH voltage and the value of the lower CSH voltage are equal at the location indicated by (1).
- the voltage indicated by (2) in the graph of FIG. 3 indicates a voltage at which luminance unevenness does not occur when the liquid crystal display device 1 performs halftone solid screen display on the low gradation side.
- the difference between the value of the upper CSH voltage and the value of the lower CSH voltage after adjustment by the auxiliary capacitance line driving circuits A and B is about several mV to several tens mV.
- the auxiliary capacitance line driving circuits A and B illustrated in FIG. 2 use only the lower CSH voltage as the adjustment voltage, but the present invention is not limited to this.
- the lower CSH voltage may be fixed and the lower CSL voltage may be adjusted.
- the upper CSH voltage is input to the non-inverting input terminal and the lower CSH voltage is output.
- the lower CSH voltage adjusting circuit 7 may be used as the lower CSL voltage adjusting circuit by inputting the upper CSL voltage to the reference voltage circuit 10 of the lower CSH voltage adjusting circuit 7 instead of inputting the upper CSH voltage.
- one more lower CSH voltage adjusting circuit 7 may be provided as a lower CSL voltage adjusting circuit to adjust both the upper CSH voltage and the upper CSL voltage.
- the lower CSH voltage and the lower CSL voltage may be fixed, and the upper CSH voltage, the upper CSL voltage, or both the upper CSH voltage and the upper CSL voltage may be adjusted.
- the lower CSH voltage adjusting circuit 7 may be used as the upper CSH voltage adjusting circuit or the upper CSL voltage adjusting circuit by inputting the lower CSH voltage or the lower CSL voltage to the upper CSL voltage adjusting circuit.
- the display screen is divided into two upper and lower screens MU and MD.
- the display screen is divided into three or more screens, adjustment with higher accuracy is possible. It is also possible to divide the display screen into left and right or to divide it into a grid.
- FIG. 4 is an explanatory diagram showing that luminance unevenness is eliminated in the liquid crystal display device 1 of the first embodiment.
- FIG. 4A is a diagram showing that uneven luminance occurs in the conventional liquid crystal display device
- FIG. 4B shows that the uneven luminance is eliminated in the liquid crystal display device 1 of the first embodiment.
- FIG. In the liquid crystal display device 1, the voltage applied to the auxiliary capacitance line is finely adjusted to align the effective voltage applied to the liquid crystal capacitance, thereby eliminating luminance unevenness and improving display characteristics.
- the pixel PIX has two subpixels, and one auxiliary capacitance line is used for each subpixel, but the present invention is not limited to this.
- the pixel PIX does not have a sub-pixel, and one auxiliary capacitance line may be used for the pixel PIX.
- the upper screen MU of FIG. 2 there is one differential amplifier circuit connected to the control circuit 6 for one auxiliary capacitance line, and in the lower screen MD, only the lower CSH voltage adjustment circuit 7 is provided. May be used.
- screens MU and MD are formed by dividing the display screen, and auxiliary capacitance lines CSH1, CSH2,... CSH (p-1), CSHp and CSL1 , CSL2,... CSL (q-1), CSLq are divided into a plurality of adjacent auxiliary capacitance lines for each of the upper screen MU or the lower screen MD, and the auxiliary capacitance lines CSH1, CSH2, ... CSH (p-1),
- the auxiliary capacitance voltage applied to CSHp and CSL1, CSL2, ... CSL (q-1), CSLq is set individually for each upper screen MU or lower screen MD. It is.
- the liquid crystal display device 1 is provided with auxiliary capacitance line driving circuits A and B corresponding to the upper screen MU or the lower screen MD (each display area), and one auxiliary capacitance line driving circuit (for example, The auxiliary capacitance voltage output from another auxiliary capacitance line drive circuit (for example, the auxiliary capacitance line drive circuit B) is increased or decreased with reference to the auxiliary capacitance voltage output from the auxiliary capacitance line drive circuit A).
- the upper screen MU and the lower screen MD are divided according to the gradation variation displayed on the liquid crystal display panel 2 when the signal potential supplied to all the pixel electrodes is the same potential. Is done.
- Example 2 The following will describe another embodiment of the present invention with reference to FIGS.
- the configuration other than that described in the second embodiment is the same as that of the first embodiment.
- members having the same functions as those shown in the drawings of the first embodiment are given the same reference numerals, and explanation thereof is omitted.
- FIG. 5 is a block diagram of the liquid crystal display device 21 according to the second embodiment.
- a first difference between the liquid crystal display device 21 and the liquid crystal display device 1 of the first embodiment is a signal line driving circuit and a scanning line driving circuit.
- the signal line driving circuit 3 and the scanning line driving circuit 4 of the liquid crystal display device 1 are common to the upper screen MU and the lower screen MD.
- the liquid crystal display device 21 is provided with a signal line driving circuit 3A (first signal line driving unit) and a scanning line driving circuit 4A (first scanning line driving unit) for the upper screen MU, and the lower screen.
- a signal line driving circuit 3B (second signal line driving unit) and a scanning line driving circuit 4B (second scanning line driving unit) are provided for the MD.
- the signal line driving circuit 3 ⁇ / b> A and the signal line driving circuit 3 ⁇ / b> B are provided on both sides of the liquid crystal display panel 2 ′ of the liquid crystal display device 21.
- the signal line driving circuit 3A and the scanning line driving circuit 4A, and the signal line driving circuit 3B and the scanning line driving circuit 4B are supplied with various signals from the control circuit 6.
- the liquid crystal display panel 2 ' is referred to as a liquid crystal display panel that is divided and driven.
- a second difference between the liquid crystal display device 21 and the liquid crystal display device 1 of the first embodiment is a signal line (source line).
- the signal lines (source lines) S1, S2,... S (n-1), Sn of the liquid crystal display device 1 are common to the upper screen MU and the lower screen MD.
- the signal lines (source lines, first lines) are separated from the upper screen MU by dividing the signal lines (source lines) S1, S2,... S (n-1), Sn.
- Signal lines SA1, SA2,... SA (n-1), SAn are provided, and signal lines (source lines, second signal lines) SB1, SB2, ... SB (n-1), SBn are provided for the lower screen MD. Is provided.
- the signal lines SA1, SA2,... SA (n-1), SAn are driven by the signal line drive circuit 3A, and the signal lines SB1, SB2,... SB (n-1), SBn are driven by the signal line drive circuit 3B. .
- the liquid crystal display device 21 Since the liquid crystal display device 21 has the configuration described in the first difference and the second difference, the luminance unevenness also occurs in the liquid crystal display panel 2 ′ that is divided and driven for each of the upper screen MU and the lower screen MD. Can be eliminated.
- the ends of the auxiliary capacitance lines CSH1, CSH2,... CSH (p-1), CSHp are opened, and the auxiliary capacitance lines CSL1, CSL2,. (Q-1), the end of CSLq is open.
- the terminal ends of all the auxiliary capacitance lines are opened, a gradation variation boundary appears prominently before the auxiliary capacitance voltage is set. Therefore, it becomes easy to specify the auxiliary capacitance line for which the auxiliary capacitance voltage is to be set, and the effect of adjustment by increasing or decreasing the auxiliary capacitance voltage is enhanced.
- the liquid crystal display panel 2 ′ is divided and driven unlike the liquid crystal display panel 2 of the first embodiment. The reason why the output voltage is adjusted by the circuits A and B will be described.
- the capacitance generated by the wiring inside the liquid crystal display panel 2 ′, the wiring resistance inside the liquid crystal display panel 2 ′, etc. are not uniformly distributed inside the liquid crystal display panel 2 ′. Have. For this reason, a variation in gradation may be visually recognized as luminance unevenness when a halftone solid screen display on the low gradation side is performed.
- the cause of the uneven brightness is thought to be due to variations in the amount of charge charged to the liquid crystal capacitor.Therefore, the voltage applied to the auxiliary capacitor line is finely adjusted to align the effective voltage applied to the liquid crystal capacitor. The above-described variation in the charge amount is eliminated.
- auxiliary capacitance line drive circuits In order to finely adjust the voltage applied to the auxiliary capacitance line, a plurality of auxiliary capacitance line drive circuits are provided as shown in FIG. 5, and each of the auxiliary capacitance line drive circuits outputs a different voltage value to the corresponding auxiliary capacitance line. Make it possible. Since the adjustment value of the voltage applied to the auxiliary capacitance line is very small, adjustment is easy if the circuit configuration is such that one of the voltages applied to the two auxiliary capacitance lines is relatively finely adjusted with respect to the other. .
- the driving of the auxiliary capacitance line driving circuits A and B in the liquid crystal display device 21 of the second embodiment is the same as the driving of the auxiliary capacitance line driving circuits A and B in the liquid crystal display device 1 of the first embodiment. Description is omitted.
- FIG. 6 is an explanatory diagram showing that luminance unevenness is eliminated in the liquid crystal display device 21 of the second embodiment.
- FIG. 6A is a diagram showing that uneven luminance occurs in a conventional divided drive panel that divides the liquid crystal display panel surface into two upper and lower regions and drives each region
- FIG. (B) is a figure which shows that the brightness nonuniformity is eliminated in the liquid crystal display device 21 of the second embodiment.
- the voltage applied to the auxiliary capacitance line is finely adjusted to align the effective voltage applied to the liquid crystal capacitance, thereby eliminating luminance unevenness and improving display characteristics.
- FIG. 7 are diagrams showing that luminance unevenness occurs due to gradation variations in the liquid crystal display panel surface.
- the screen may be divided into two or three in the vertical direction.
- the screen may be divided into left and right instead of up and down.
- the screen may be divided into left and right, and the left screen and the right screen may be divided into two vertically.
- the screen is appropriately divided, and a storage capacitor line driving circuit may be provided for each divided screen.
- the voltage applied to the auxiliary capacitance line can be finely adjusted so that the effective voltage applied to the liquid crystal capacitance can be made uniform, and uneven brightness can be eliminated.
- the display screen when the extending direction of the signal lines S1, S2,... S (n-1), Sn is the column direction, the display screen is in the column direction.
- the signal lines S1, S2,... S (n-1), Sn are divided into the upper screen MU and the lower screen MD, and the signal lines SA1, SA2,... SA (n-1), SAn arranged on the upper screen MU.
- Are divided into signal lines SB1, SB2,... SB (n-1), SBn arranged on the lower screen MD, and signal lines SA1, SA2,... SA are connected to the pixel electrodes of the pixels provided on the upper screen MU.
- the signal lines SB1, SB2,... SB (n-1), SBn are connected to the signal line driving circuit 3A for supplying image data via (n-1), SAn and the pixel electrodes of the pixels provided on the lower screen MD.
- a signal line driving circuit 3B for supplying image data via the.
- the scanning lines G1, G2,... G (m ⁇ 1), Gm is the row direction
- the scanning lines G1, G2,. 1) and Gm are divided into a first scanning line arranged on the upper screen MU and a second scanning line arranged on the lower screen MD, and the pixels provided on the upper screen MU are changed to the first scanning line.
- the terminal ends of the auxiliary capacitance lines in the liquid crystal display panel 2 ′ may be connected to each other. That is, the terminal of auxiliary capacitance lines CSH1, CSH2,... CSH ⁇ (auxiliary capacitance lines extending through the first region) corresponding to the upper screen MU is connected and the auxiliary capacitance lines corresponding to the upper screen MU.
- the terminal ends of CSL1, CSL2,... CSL ⁇ (auxiliary capacitance lines extending through the first region) are connected, and auxiliary capacitance lines CSH ( ⁇ + 1), CSH ( ⁇ + 2),.
- the terminal of the (auxiliary capacitance line extending so as to pass through the second region) is connected, and the auxiliary capacitance lines CSL ( ⁇ + 1), CSL ( ⁇ + 2),... CSLq (second region corresponding to the lower screen MD)
- the terminal of the auxiliary capacity line extending so as to pass through may be connected.
- ⁇ p / 2
- ⁇ q / 2 (p and q are positive even numbers).
- auxiliary capacitance line in which one auxiliary capacitance line is arranged corresponding to one pixel PIX, all the auxiliary capacitance lines are connected to each other, and two auxiliary capacitance lines are arranged corresponding to one pixel PIX.
- the auxiliary capacitance lines to which the High side potential is supplied are connected to each other, and the auxiliary capacitance lines to which the Low side potential is supplied are connected to each other.
- the storage capacitor voltage according to this embodiment may be a signal waveform (not limited to a binary value) that switches to a high-side potential or a low-side potential depending on the polarity of the signal potential written to the pixel electrode.
- the signal waveform may be a constant potential for each display area.
- the upper screen MU and the lower screen MD are connected to the auxiliary capacitance lines CSH 1, CSH 2,... CSH (p ⁇ 1), CSHp, CSL 1, CSL 2, CSL (q ⁇ 1), CSLq It may be equally divided in a direction perpendicular to the stretching direction.
- the continuous upper screen MU and lower screen MD are parallel to the extension direction of the auxiliary capacitance lines CSH1, CSH2,... CSH (p-1), CSHp, CSL1, CSL2, ... CSL (q-1), CSLq. Evenly arranged.
- auxiliary capacitance line driving circuits A and B are provided corresponding to the upper screen MU and the lower screen MD, and the auxiliary capacitance voltage output from one auxiliary capacitance line driving circuit is used as a reference.
- the auxiliary capacitance voltage output from another auxiliary capacitance line driving circuit may be increased or decreased.
- the effective voltage applied to the liquid crystal capacitance can be made uniform by increasing / decreasing (fine-tuning) the auxiliary capacitance voltage applied from another auxiliary capacitance line driving circuit, and as a result, luminance unevenness can be eliminated.
- two auxiliary capacitance lines may be arranged corresponding to one pixel PIX.
- one signal line driving circuit 3 for driving the signal lines S1, S2,... S, Sn is provided, and the extending direction of the signal lines S1, S2,.
- one signal line may be provided for each pixel column including a plurality of pixels PIX provided in the column direction.
- the signal lines S1, S2,... S, Sn can supply image data to the pixel PIX farthest from the signal line driving circuit 3 without being divided in the middle.
- one scanning line driving circuit 4 for driving the scanning lines G1, G2,... G, Gm is provided, and the extending direction of the scanning lines G1, G2,.
- one scanning line may be provided for each pixel row including a plurality of pixels PIX provided in the row direction. Accordingly, the scanning lines G1, G2,... G, Gm can be selected up to the farthest pixel from the scanning line driving circuit 4 without being divided in the middle.
- each auxiliary capacitance line since the wiring resistance of each auxiliary capacitance line can be made uniform, the gradation variation for each display region can be further reduced.
- all the auxiliary capacitance lines are connected to each other, and two auxiliary capacitance lines are arranged corresponding to one pixel PIX.
- the auxiliary capacitance lines to which the High side potential is supplied are connected to each other, and the auxiliary capacitance lines to which the Low side potential is supplied are connected to each other.
- the display screen is divided into an upper screen MU and a lower screen MD in the column direction.
- the signal lines S1, S2,... S (n-1), Sn are arranged on the signal lines SA1, SA2,... SA (n-1), SAn arranged on the upper screen MU and the lower screen MD.
- Signal lines SB1, SB2,... SB (n-1), SBn are divided into signal lines SA1, SA2,... SA (n-1), SAn to the pixel electrodes of the pixels PIX provided on the upper screen MU.
- the image data is supplied via the signal lines SB1, SB2,... SB (n ⁇ 1), SBn to the signal line driving circuit 3A for supplying the image data via the signal line SB1, SB2,. And a signal line driver circuit 3B.
- the scanning lines G1, G2,... G (m-1), Gm is the row direction
- the pixel PIX provided on the upper screen MU is divided into a first scanning line arranged on the upper screen MU and a second scanning line arranged on the lower screen MD.
- a scanning line driving circuit 4A for selecting via the second scanning line may be provided, and a scanning line driving circuit 4B for selecting the pixel PIX provided on the lower screen MD via the second scanning line.
- the auxiliary capacitance lines CSH1, CSH2,... CSH ⁇ , CSL1, CSL2,... CSL ⁇ corresponding to the pixels PIX provided on the upper screen MU are connected to each other and provided on the lower screen MD.
- the auxiliary capacitance lines CSH ( ⁇ + 1), CSH ( ⁇ + 2),... CSHp, CSL ( ⁇ + 1), CSL ( ⁇ + 2),... CSLq corresponding to the pixel PIX may be connected to each other.
- one auxiliary capacitance line is arranged corresponding to one pixel PIX
- all the auxiliary capacitance lines are connected to each other, and two auxiliary capacitance lines are arranged corresponding to one pixel PIX.
- the auxiliary capacitance lines to which the High side potential is supplied are connected to each other, and the auxiliary capacitance lines to which the Low side potential is supplied are connected to each other.
- the end of CSLq may be opened.
- a gradation variation boundary appears prominently before the auxiliary capacitance voltage is set. Therefore, it becomes easy to specify the auxiliary capacitance line for which the auxiliary capacitance voltage is to be set, and the effect of adjustment by increasing or decreasing the auxiliary capacitance voltage is enhanced.
- the liquid crystal display device of the present invention is suitable for a large-sized liquid crystal display panel because it can eliminate luminance unevenness due to gradation variations occurring in the plane of the liquid crystal display panel even in a split drive type liquid crystal display panel. Can be used.
- G Gm scanning line (scanning line, first scanning line, second scanning line) MD lower screen (display area, second display area) MU upper screen (display area, first display area) PIX, PIXn Pixel R1, R3 to R6 Resistor R2 Resistance adjustment section Bar RH, Bar RL, Bar RW Node Rf, Rf 'Feedback resistance Ri Input resistance Rs Signal source resistance S1, S2,... S, Sn Signal lines SA1, SA2 ,... SA, SAn signal line (first signal line) SB1, SB2,...
- SB, SBn Signal line (second signal line) VCSH1 to VCSH12, VCSH13 to VCSH24, VCSL1 to VCSL12, VCSL13 to VCSL24 Voltage (auxiliary capacity voltage) VLS Power supply voltage Vm Minute voltage Vref Reference voltage
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Abstract
Description
図1は、本実施例1に係る液晶表示装置1のブロック図である。液晶表示装置1は、液晶表示パネル2と、信号線(ソース線、各信号線)S1,S2,…S(n-1),Snを駆動する信号線駆動回路3(信号線駆動部)と、走査線(ゲート線、走査線、第1の走査線、第2の走査線、各走査線)G1,G2,…G(m-1),Gmを駆動する走査線駆動回路4(走査線駆動部)と、制御回路6と、画素PIX内の補助容量に接続されている、補助容量線CSH1,CSH2,…CSH(p-1),CSHpおよび補助容量線CSL1,CSL2,…CSL(q-1),CSLqを駆動する補助容量線駆動回路(補助容量線駆動部)A,Bとを備えている。信号線駆動回路3、走査線駆動回路4、および制御回路6は、表示ドライバを構成している。
本発明の他の実施例について図5および図6に基づいて説明すれば、以下の通りである。なお、本実施例2において説明すること以外の構成は、前記実施例1と同じである。また、説明の便宜上、前記実施例1の図面に示した部材と同一の機能を有する部材については、同一の符号を付し、その説明を省略する。
液晶表示装置1,1’,21では、上画面MUおよび下画面MDは、補助容量線CSH1,CSH2,…CSH(p-1),CSHp,CSL1,CSL2,…CSL(q-1),CSLqの延伸方向と垂直な方向に等分されていてもよい。
2,2’ 液晶表示パネル
3 信号線駆動回路(信号線駆動部)
3A 信号線駆動回路(第1の信号線駆動部)
3B 信号線駆動回路(第2の信号線駆動部)
4 走査線駆動回路(走査線駆動部)
4A 走査線駆動回路(第1の走査線駆動部)
4B 走査線駆動回路(第2の走査線駆動部)
6 制御回路
7 下CSH電圧調整回路
8,ACSH,ACSL,Adiff 差動増幅回路
10 基準電圧回路
11 温度補正回路
12 加算回路
A,B 補助容量線駆動回路
CSH1,CSH2,…CSH(p-1),CSHp 補助容量線
CSL1,CSL2,…CSL(q-1),CSLq 補助容量線
CSH1~CSH12 補助容量線
CSH13~CSH24 補助容量線
CSL1~CSL12 補助容量線
CSL13~CSL24 補助容量線
CSH1,CSH2,…CSHα 補助容量線
CSL1,CSL2,…CSLβ 補助容量線
CSH(α+1),CSH(α+2),…CSHp 補助容量線
CSL(β+1),CSL(β+2),…CSLq 補助容量線
G1,G2,…G,Gm 走査線(走査線、第1の走査線、第2の走査線)
MD 下画面(表示領域、第2の表示領域)
MU 上画面(表示領域、第1の表示領域)
PIX,PIXn 画素
R1,R3~R6 抵抗
R2 抵抗値調整部
バーRH,バーRL,バーRW ノード
Rf,Rf’ 帰還抵抗
Ri 入力抵抗
Rs 信号源抵抗
S1,S2,…S,Sn 信号線
SA1,SA2,…SA,SAn 信号線(第1の信号線)
SB1,SB2,…SB,SBn 信号線(第2の信号線)
VCSH1~VCSH12,VCSH13~VCSH24,VCSL1~VCSL12,VCSL13~VCSL24 電圧(補助容量電圧)
VLS 電源電圧
Vm 微小電圧
Vref 基準電圧
Claims (12)
- 画素に含まれる画素電極と容量を形成する補助容量線を備えるアクティブマトリックス型の液晶表示装置において、
表示画面を分割した複数の表示領域を形成し、
上記補助容量線は、上記表示領域ごとに、隣り合う複数の補助容量線に分割され、
上記補助容量線に印加される補助容量電圧は、上記表示領域ごとに個別に設定されていることを特徴とする液晶表示装置。 - 上記複数の表示領域は、上記補助容量線の延伸方向と垂直な方向に等分されていることを特徴とする請求項1に記載の液晶表示装置。
- 各表示領域に対応して複数の補助容量線駆動部が設けられ、
1つの補助容量線駆動部から出力される補助容量電圧を基準として、他の補助容量線駆動部から出力される補助容量電圧を増減することを特徴とする請求項1または2に記載の液晶表示装置。 - 1つの画素に対応して、2本の補助容量線が配されていることを特徴とする請求項1~3のいずれか1項に記載の液晶表示装置。
- 各信号線を駆動する信号線駆動部が1つ設けられ、
信号線の延伸方向を列方向とした場合に、列方向に設けられた複数の画素を含む画素列ごとに1本の信号線が配されていることを特徴とする請求項1~4のいずれか1項に記載の液晶表示装置。 - 各走査線を駆動する走査線駆動部が1つ設けられ、
走査線の延伸方向を行方向とした場合に、行方向に設けられた複数の画素を含む画素行ごとに1本の走査線が配されていることを特徴とする請求項1~5のいずれか1項に記載の液晶表示装置。 - 補助容量線の終端は、互いに接続されていることを特徴とする請求項6に記載の液晶表示装置。
- 全ての補助容量線の終端は、開放されていることを特徴とする請求項6に記載の液晶表示装置。
- 信号線の延伸方向を列方向とした場合に、
上記表示画面は、列方向に第1及び第2の表示領域に分割され、
上記信号線は、上記第1の表示領域に配された第1の信号線と、上記第2の表示領域に配された第2の信号線とに分割され、
上記第1の表示領域に設けられた画素の画素電極に、上記第1の信号線を介して画像データを供給する第1の信号線駆動部と、
上記第2の表示領域に設けられた画素の画素電極に、上記第2の信号線を介して画像データを供給する第2の信号線駆動部とを備えることを特徴とする請求項1~4のいずれか1項に記載の液晶表示装置。 - 走査線の延伸方向を行方向とした場合に、
上記走査線は、上記第1の表示領域に配された第1の走査線と、上記第2の表示領域に配された第2の走査線とに分割され、
上記第1の表示領域に設けられた画素を、上記第1の走査線を介して選択する第1の走査線駆動部と、
上記第2の表示領域に設けられた画素を、上記第2の走査線を介して選択する第2の走査線駆動部とを備えることを特徴とする請求項9に記載の液晶表示装置。 - 上記第1の表示領域に設けられた画素に対応する補助容量線は、互いに接続されているとともに、上記第2の表示領域に設けられた画素に対応する補助容量線は、互いに接続されていることを特徴とする請求項10に記載の液晶表示装置。
- 全ての補助容量線の終端は、開放されていることを特徴とする請求項10に記載の液晶表示装置。
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RU2012120478/08A RU2012120478A (ru) | 2009-10-21 | 2010-06-22 | Жидкокристаллическое дисплейное устройство |
US13/502,416 US20120200558A1 (en) | 2009-10-21 | 2010-06-22 | Lcd device |
JP2011537166A JP5412524B2 (ja) | 2009-10-21 | 2010-06-22 | 液晶表示装置 |
CN201080046987.0A CN102576519B (zh) | 2009-10-21 | 2010-06-22 | 液晶显示装置 |
EP10824699.2A EP2515289A4 (en) | 2009-10-21 | 2010-06-22 | LCD DEVICE |
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EP (1) | EP2515289A4 (ja) |
JP (1) | JP5412524B2 (ja) |
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WO2016117390A1 (ja) * | 2015-01-20 | 2016-07-28 | シャープ株式会社 | 液晶表示装置、液晶表示装置の製造方法 |
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KR102060788B1 (ko) | 2012-12-31 | 2019-12-31 | 삼성디스플레이 주식회사 | 표시 장치 및 그 구동 방법 |
GB2516637A (en) * | 2013-07-26 | 2015-02-04 | Sharp Kk | Display device and method of driving same |
US10497333B2 (en) * | 2015-05-22 | 2019-12-03 | Sharp Kabushiki Kaisha | Liquid crystal display |
KR102455327B1 (ko) * | 2015-06-15 | 2022-10-18 | 삼성디스플레이 주식회사 | 표시 장치 및 이의 구동 방법 |
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JP2001255851A (ja) * | 2000-03-09 | 2001-09-21 | Matsushita Electric Ind Co Ltd | 液晶表示装置 |
JP2006235593A (ja) | 2005-01-27 | 2006-09-07 | Toshiba Matsushita Display Technology Co Ltd | 液晶表示装置 |
JP2007219200A (ja) * | 2006-02-17 | 2007-08-30 | Nec Electronics Corp | 表示装置、データドライバ、及び表示パネル駆動方法 |
JP2008164852A (ja) * | 2006-12-27 | 2008-07-17 | Lg Display Co Ltd | 液晶表示装置 |
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JP3536006B2 (ja) * | 2000-03-15 | 2004-06-07 | シャープ株式会社 | アクティブマトリクス型表示装置およびその駆動方法 |
JP2005049849A (ja) * | 2003-07-11 | 2005-02-24 | Toshiba Matsushita Display Technology Co Ltd | 表示装置 |
JP4265788B2 (ja) * | 2003-12-05 | 2009-05-20 | シャープ株式会社 | 液晶表示装置 |
TWI335559B (en) * | 2006-01-13 | 2011-01-01 | Chimei Innolux Corp | Liquid crystal display |
JP4932823B2 (ja) * | 2006-03-06 | 2012-05-16 | シャープ株式会社 | アクティブマトリクス基板、表示装置及びテレビジョン受像機 |
US20080252804A1 (en) * | 2007-04-13 | 2008-10-16 | Toshiba Matsushita Display Technology Co., Ltd. | Liquid crystal display device |
US8542228B2 (en) * | 2007-12-27 | 2013-09-24 | Sharp Kabushiki Kaisha | Liquid crystal display, liquid crystal display driving method, and television receiver utilizing a preliminary potential |
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2010
- 2010-06-22 RU RU2012120478/08A patent/RU2012120478A/ru not_active Application Discontinuation
- 2010-06-22 EP EP10824699.2A patent/EP2515289A4/en not_active Withdrawn
- 2010-06-22 WO PCT/JP2010/060556 patent/WO2011048847A1/ja active Application Filing
- 2010-06-22 US US13/502,416 patent/US20120200558A1/en not_active Abandoned
- 2010-06-22 JP JP2011537166A patent/JP5412524B2/ja not_active Expired - Fee Related
- 2010-06-22 CN CN201080046987.0A patent/CN102576519B/zh not_active Expired - Fee Related
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JP2001255851A (ja) * | 2000-03-09 | 2001-09-21 | Matsushita Electric Ind Co Ltd | 液晶表示装置 |
JP2006235593A (ja) | 2005-01-27 | 2006-09-07 | Toshiba Matsushita Display Technology Co Ltd | 液晶表示装置 |
JP2007219200A (ja) * | 2006-02-17 | 2007-08-30 | Nec Electronics Corp | 表示装置、データドライバ、及び表示パネル駆動方法 |
JP2008164852A (ja) * | 2006-12-27 | 2008-07-17 | Lg Display Co Ltd | 液晶表示装置 |
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WO2016117390A1 (ja) * | 2015-01-20 | 2016-07-28 | シャープ株式会社 | 液晶表示装置、液晶表示装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US20120200558A1 (en) | 2012-08-09 |
JPWO2011048847A1 (ja) | 2013-03-07 |
JP5412524B2 (ja) | 2014-02-12 |
EP2515289A4 (en) | 2014-03-12 |
EP2515289A1 (en) | 2012-10-24 |
CN102576519B (zh) | 2014-10-01 |
CN102576519A (zh) | 2012-07-11 |
RU2012120478A (ru) | 2013-11-27 |
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