WO2011018862A1 - Multilayer flexible printed circuit board, and method for fabricating the same - Google Patents

Multilayer flexible printed circuit board, and method for fabricating the same Download PDF

Info

Publication number
WO2011018862A1
WO2011018862A1 PCT/JP2010/001358 JP2010001358W WO2011018862A1 WO 2011018862 A1 WO2011018862 A1 WO 2011018862A1 JP 2010001358 W JP2010001358 W JP 2010001358W WO 2011018862 A1 WO2011018862 A1 WO 2011018862A1
Authority
WO
WIPO (PCT)
Prior art keywords
double
printed circuit
circuit board
flexible printed
interconnection layer
Prior art date
Application number
PCT/JP2010/001358
Other languages
English (en)
French (fr)
Inventor
Kazuhiro Hashimoto
Syohei Morimoto
Yoshinori Kawakami
Norihiro Yamaguchi
Original Assignee
Tatsuta Electric Wire & Cable Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tatsuta Electric Wire & Cable Co., Ltd. filed Critical Tatsuta Electric Wire & Cable Co., Ltd.
Priority to CN201080035312.6A priority Critical patent/CN102474985B/zh
Publication of WO2011018862A1 publication Critical patent/WO2011018862A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H05K3/4691—Rigid-flexible multilayer circuits comprising rigid and flexible layers, e.g. having in the bending regions only flexible layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09109—Locally detached layers, e.g. in multilayer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards

Definitions

  • the present invention relates to a multilayer flexible printed circuit board for use in a mobile phone, a small-scale mobile terminal or the like, and a method for fabricating the same.
  • FPC Flexible printed circuit boards
  • FPCs are thin bendable circuit boards to be used in a variety of electronic apparatuses.
  • FPCs With a recent tendency toward size reduction and higher performance of the electronic apparatuses, particularly, mobile phones, small-scale mobile terminals, digital cameras and the like, FPCs to be mounted in these electronic apparatuses are increasingly required to include minute interconnections and have a higher interconnection density and a reduced thickness.
  • a multilayer FPC which is produced by laminating two double-sided FPCs, two single-sided FPCs, or a single-sided FPC and a double-sided FPC.
  • Patent Document 1 proposes that printed circuit boards are laminated via a prepreg (sheet material) for fabrication of a multilayer printed circuit board.
  • a prepreg sheet material
  • through-holes are preliminarily formed in the prepreg and filled with an electrically conductive paste, and the printed circuit boards are laminated via the prepreg.
  • the use of the prepreg simultaneously achieves the bonding of the printed circuit boards and the formation of inner via-holes (IVH).
  • Patent Document 2 discloses an adhesive sheet to be used for laminating FPCs.
  • the adhesive sheet is composed of a base of a woven or nonwoven fabric and a resin composition, and has a configuration suitable for laminating the FPCs with the adhesive sheet being interposed between the FPCs.
  • Patent Document 3 discloses a resin adhesive sheet to be used for laminating FPCs.
  • the adhesive sheet has through-holes, which are filled with an electrically conductive paste.
  • Patent Document 4 discloses a bonding sheet to be used for a multilayer FPC.
  • the bonding sheet disclosed in Patent Document 4 is a multilayer FPC bonding sheet of a prepreg which is prepared by impregnating a woven or nonwoven fabric base with an epoxy resin composition and serves to enhance the rigidity of the multilayer FPC.
  • Patent Document 5 proposes a multilayer FPC including an adhesive sheet (bonding sheet) formed with a hollow portion for connecting FPCs to each other.
  • the multilayer flexible printed circuit board (hereinafter referred to as "multilayer FPC" in this section) should satisfy the requirements for the higher interconnection density and the reduced thickness.
  • a connection sheet i.e., a connection sheet having through-holes filled with an electrically conductive paste
  • the multilayer FPC obtained by laminating the FPCs advantageously has a reduced thickness, and ensures proper electrical connection between interconnection layers provided on opposite sides of the connection sheet.
  • the interconnection density of the multilayer FPC is not sufficiently increased, leaving room for improvement. More specifically, electronic components and electronic devices are mounted on an interconnection layer exposed in a front surface of the multilayer FPC. Therefore, unless the front surface interconnection layer has a minute circuit configuration, it is difficult to mount the electronic components and the like at a higher density.
  • the front surface interconnection layer has blind via-holes (BVHs) and through-via-holes (TVHs) extending from the front surface, and inner peripheral surfaces of the BVHs and the TVHs as well as the front surface interconnection layer are plated. This increases the thickness of the front surface interconnection layer, thereby preventing provision of a minute circuit configuration in the front surface interconnection layer.
  • the provision of the BVHs and the TVHs in the front surface layer (in an electronic component mounting surface) reduces the size of component mounting areas, thereby preventing the higher density mounting. Therefore, the multilayer FPC is desirably improved to permit the higher density mounting.
  • a multilayer flexible printed circuit board including: a bonding sheet (2); a first double-sided flexible printed circuit board (3) provided on one of opposite surfaces of the bonding sheet; and a second double-sided flexible printed circuit board (4) provided on the other surface of the bonding sheet; the bonding sheet (2) having a through-hole (7, 8, 9, 10) which is provided at a predetermined position as extending therethrough from the one surface to the other surface and filled with an electrically conductive paste (11) to electrically connect the first double-sided flexible printed circuit board (3) and the second double-sided flexible printed circuit board (4) by the electrically conductive paste (11); the first double-sided flexible printed circuit board (3) and the second double-sided flexible printed circuit board (4) each including an insulating film (13, 21), and an inner surface interconnection layer (L2, L3) and an outer surface interconnection layer (L1, L4) respectively provided on opposite surfaces of the insulating film (13, 21); the outer surface interconnection layer (L1, L4) being located away from the bonding sheet (2)
  • the multilayer flexible printed circuit board of claim 1 further includes a hollow portion (12) through which the first double-sided flexible printed circuit board (3) and the second double-sided flexible printed circuit board (4) are partly opposed to each other in the absence of the bonding sheet (2).
  • the inner surface interconnection layer is absent from a part of the first double-sided flexible printed circuit board and a part of the second double-sided flexible printed circuit board opposed to each other through the hollow portion (12) in the multilayer flexible printed circuit board of claim 2.
  • the part of the first double-sided flexible printed circuit board and the part of the second double-sided flexible printed circuit board opposed to each other through the hollow portion (12) have different lengths in the multilayer flexible printed circuit board of claim 2 or 3.
  • the multilayer flexible printed circuit board of claim 1 includes a laminate portion (53) including the first double-sided flexible printed circuit board (3) provided on the one surface of the bonding sheet (2) and the second double-sided flexible printed circuit board (4) provided on the other surface of the bonding sheet (2), and a non-laminate portion (54, 55) including only an extension of the first double-sided flexible printed circuit board (3) or the second double-sided flexible printed circuit board (4) and in the absence of the bonding sheet (2) and the second double-sided flexible printed circuit board (4) or the first double-sided flexible printed circuit board (3).
  • a multilayer flexible printed circuit board including: a first double-sided flexible printed circuit board (3) having an insulating film (13), and an inner surface interconnection layer (L2) and an outer surface interconnection layer (L1) respectively provided on opposite surfaces of the insulating film (13), the outer surface interconnection layer (L1) serving as an interconnection layer on which an electronic device is mounted, the inner surface interconnection layer (L2) having an opening formed at a predetermined position, the insulating film (13) having an inner layer via-hole (16) extending therethrough as communicating with the opening and facing the outer surface interconnection layer for electrical connection between the inner surface interconnection layer and the outer surface interconnection layer; a second double-sided flexible printed circuit board (4) having an insulating film (21), and an inner surface interconnection layer (L5) and an outer surface interconnection layer (L6) respectively provided on opposite surfaces of the insulating film (21), the outer surface interconnection layer (L6) serving as an interconnection layer on which an electronic device is mounted, the inner surface interconnection layer (L
  • the multilayer flexible printed circuit board of claim 6 includes a hollow portion (12) through which the first double-sided flexible printed circuit board and the second double-sided flexible printed circuit board are partly opposed to each other in the absence of the multilayer structure.
  • the double-sided printed circuit boards (92) of the multilayer structure (911) each include a double-sided flexible printed circuit board, a double-sided rigid printed circuit board, or a multilayer structure including a double-sided flexible printed circuit board and a double-sided rigid printed circuit board in combination.
  • the inner surface interconnection layer is absent from a part of the first double-sided flexible printed circuit board and a part of the second double-sided flexible printed circuit board opposed to each other through the hollow portion (12) in the multilayer flexible printed circuit board of claim 7 or 8.
  • the part of the first double-sided flexible printed circuit board and the part of the second double-sided flexible printed circuit board opposed to each other through the hollow portion (12) have different lengths in the multilayer flexible printed circuit board of any of claims 7 to 9.
  • a method for fabricating a multilayer flexible printed circuit board by laminating a first double-sided flexible printed circuit board and a second double-sided flexible printed circuit board via a bonding sheet with the first double-sided flexible printed circuit board stacked on one of opposite surfaces of the bonding sheet and with the second double-sided flexible printed circuit board stacked on the other surface of the bonding sheet, the method comprising the steps of: prior to the laminating of the first double-sided flexible printed circuit board and the second double-sided flexible printed circuit board via the bonding sheet, forming an opening at a predetermined position in an inner surface interconnection layer of the first double-sided flexible printed circuit board to be brought into contact with the bonding sheet, and forming an inner layer via-hole extending through an insulating film of the first double-sided flexible printed circuit board as communicating with the opening of the inner surface interconnection layer of the first double-sided flexible printed circuit board and facing an outer surface interconnection layer of the first double-sided flexible printed circuit board to electrically connect the inner surface interconnection
  • the multilayer flexible printed circuit board fabricating method of claim 11 further includes the steps of: prior to the collective laminating step, forming a hole extending through the bonding sheet from the one surface to the other surface of the bonding sheet at a predetermined position in the bonding sheet; and filling the hole of the bonding sheet with an electrically conductive paste.
  • the first double-sided flexible printed circuit board and the second double-sided flexible printed circuit board each have the inner layer via-hole, and the inner surface interconnection layer and the outer surface interconnection layer are electrically connected to each other via the inner layer via-hole.
  • an inner peripheral surface of the inner layer via-hole is plated, for example, with copper.
  • the outer surface interconnection layer is not covered with the plating. This ensures provision of a minute circuit configuration in the outer surface interconnection layer, which would otherwise be hampered when the thickness of the outer surface interconnection layer is increased by the plating of the outer surface interconnection layer.
  • the size of component mounting areas of the outer surface interconnection layer on which electronic devices and electronic components are to be mounted is not reduced. This ensures the higher density mounting on the outer surface interconnection layer.
  • the first double-sided flexible printed circuit board and the second double-sided flexible printed circuit board are laminated via the bonding sheet having the hole filled with the electrically conductive paste. Therefore, the multilayer flexible printed circuit board has a reduced thickness. Thus, the thickness reduction is achieved.
  • the first double-sided flexible printed circuit board and the second double-sided flexible printed circuit board are laminated with their inner surface interconnection layers kept in direct contact with the surfaces of the bonding sheet and embedded in the bonding sheet from the surfaces of the bonding sheet. This arrangement is particularly effective for thickness reduction of the multilayer flexible printed circuit board.
  • the multilayer flexible printed circuit board has the hollow portion in which the bonding sheet is absent.
  • the hollow portion imparts the multilayer flexible printed circuit board with excellent folding endurance, so that the multilayer flexible printed circuit board is suitable for use in a foldable mobile phone or the like.
  • the inner surface interconnection layer is absent in the hollow portion. This improves the bendability around the hollow portion.
  • the part of the first double-sided flexible printed circuit board and the part of the second double-sided flexible printed circuit board opposed to each other through the hollow portion have different lengths. Therefore, the multilayer flexible printed circuit board has excellent folding endurance around the hollow portion.
  • the multilayer flexible printed circuit board may have a partial multilayer structure as required. Therefore, the multilayer flexible printed circuit board can be properly accommodated in a smaller space in an apparatus in which the multilayer flexible printed circuit board is mounted without needlessly taking up much space in the apparatus.
  • the multilayer flexible printed circuit board which includes six or more interconnection layers, has a reduced thickness, and permits provision of minute circuit configurations in the surface interconnection layers and higher density mounting of components.
  • the multilayer flexible printed circuit board includes the hollow portion, and has excellent bendability around the hollow portion.
  • the fabrication method of claims 11 and 12 makes it possible to fabricate the multilayer flexible printed circuit board by a relatively small number of process steps in a shorter period of time.
  • Fig. 1 is a schematic sectional view illustrating three structural block layers of a multilayer flexible printed circuit board according to one embodiment of the present invention ("flexible printed circuit board” will hereinafter be abbreviated as "FPC" in this section).
  • Fig. 2 is a schematic sectional view of a laminate structure of the multilayer FPC 1 of the embodiment fabricated by laminating a first double-sided FPC 3 and a second double-sided FPC 4 in contact with opposite surfaces of a bonding sheet 2 by heat and pressure.
  • Fig. 3 is a schematic sectional view of the multilayer FPC 1 as a finished product.
  • Fig. 4A is a schematic sectional view showing the construction of a prior-art multilayer FPC fabricated by a prior-art process, and Fig.
  • FIG. 4B is a schematic sectional view of the multilayer FPC 1 of the embodiment of the present invention fabricated by an inventive process.
  • Fig. 5A is a diagram showing the prior-art process for fabricating the prior-art multilayer FPC
  • Fig. 5B is a diagram showing the inventive process for fabricating the multilayer FPC 1 according to the embodiment of the present invention.
  • Fig. 6 is a schematic sectional view showing the construction of a multilayer FPC 51 according to another embodiment of the present invention.
  • Fig. 7 is a schematic sectional view showing the construction of a multilayer FPC 71 according to further another embodiment of the present invention.
  • Fig. 8 is a schematic diagram for explaining a difference in length between an outer FPC and an inner FPC when a multilayer FPC is folded.
  • Fig. 9 is a schematic sectional view showing the construction of a multilayer FPC 91 according to still another embodiment of the present invention.
  • Fig. 1 is a schematic sectional view illustrating three structural block layers of a multilayer flexible printed circuit board (hereinafter referred to as "multilayer FPC" in this section) according to one embodiment of the present invention.
  • the multilayer FPC 1 includes, as the structural block layers (structural components), a bonding sheet 2, a first double-sided FPC 3 provided on one of opposite surfaces of the bonding sheet 2, and a second double-sided FPC 4 provided on the other surface of the bonding sheet 2.
  • Exemplary sheet materials for the bonding sheet 2 include a prepreg prepared by impregnating a glass fiber sheet with an epoxy resin, a sheet material prepared by applying an adhesive such as of an epoxy resin on opposite surfaces of a core film (e.g., a polyimide film), and a coreless thermosetting resin film.
  • a prepreg prepared by impregnating a glass fiber sheet with an epoxy resin
  • a sheet material prepared by applying an adhesive such as of an epoxy resin on opposite surfaces of a core film (e.g., a polyimide film)
  • a coreless thermosetting resin film e.g., a coreless thermosetting resin film
  • the bonding sheet 2 thus serves as an insulating layer and an adhesive layer, the multilayer FPC 1 has a reduced thickness.
  • the bonding sheet 2 has a thickness of about 100 to about 150 micrometer.
  • the bonding sheet 2 has holes 7, 8, 9, 10 formed at predetermined positions as each extending therethrough from the one surface 5 to the other surface 6 thereof.
  • the holes 7 to 10 are filled with an electrically conductive paste 11.
  • the electrically conductive paste is an electrically conductive paste containing an electrically conductive filler (of silver or copper, or silver-coated copper powder or the like) in combination with an epoxy resin, for example, an electrically conductive paste disclosed in JP-4109156.
  • an electrically conductive paste containing a lower melting point metal and a higher melting point metal as an electrically conductive filler in combination with an epoxy resin for example, an electrically conductive paste disclosed in JP-4191678, may be used.
  • the holes 7 to 10 formed in the bonding sheet 2 and the electrically conductive paste filled in the holes 7 to 10 serve as via-holes, which electrically connect an inner layer circuit (second interconnection layer L2) of the first double-sided FPC 3 and an inner layer circuit (third interconnection layer L3) of the second double-sided FPC 4 as will be described later.
  • the bonding sheet 2 has a bonding sheet absent portion 12 located at a laterally intermediate portion.
  • the bonding sheet absent portion 12 is a hollow portion through which the first double-sided FPC 3 and the second double-sided FPC 4 are partly opposed to each other as will be described later.
  • the first double-sided FPC 3 is such that a first interconnection layer L1 and a second interconnection layer L2 are respectively formed on an outer surface and an inner surface of a polyimide insulating base film 13 through a subtractive method by processing a copper clad laminate (CCL) including copper foils provided on the opposite surfaces of the polyimide insulating base film 13.
  • CCL copper clad laminate
  • the formation of the first interconnection layer L1 and the second interconnection layer L2 may be achieved through a semi-additive method by forming seed layers having a thickness of several thousands angstroms on opposite surfaces of an insulating base film 13 by sputtering, and forming interconnection layer patterns on the seed layers by copper electrolytic plating.
  • a feature of the construction of the first double-sided FPC 3 is that the first double-sided FPC 3 has inner layer via-holes 16 formed therein as extending from the second interconnection layer L2 (inner surface interconnection layer) toward the first interconnection layer L1 (outer surface interconnection layer), and the first interconnection layer L1 (outer surface interconnection layer) and the second interconnection layer L2 (inner surface interconnection layer) are electrically connected to each other via the inner layer via-holes 16.
  • the inner layer via-holes 16 are formed from the side of the second interconnection layer L2 (inner surface interconnection layer), and do not extend through the first interconnection layer L1 (outer surface interconnection layer), thereby not serving as through-via-holes (TVHs).
  • the formation of the inner layer via-holes 16 may be achieved, for example, through a conformal method by etching away copper foil portions from opening formation regions of the second interconnection layer L2 (inner surface interconnection layer), and then forming openings in the insulating film 13 by laser processing.
  • the inner layer via-holes 16 do not extend through the first interconnection layer L1 (outer surface interconnection layer) because the inner layer via-holes 16 are formed from the side of the second interconnection layer L2 (inner surface interconnection layer) in the first double-sided FPC 3. Therefore, when inner peripheral surfaces of the inner layer via-holes 16 are plated for formation of interlayer conductive holes, the first interconnection layer L1 (outer surface interconnection layer) is not covered with the plating (i.e., the first interconnection layer L1 is not plated). This ensures provision of a minute circuit configuration, which would otherwise be hampered when the thickness of the first interconnection layer L1 finely processed is increased by the plating.
  • the inner layer via-holes 16 are not present in the first interconnection layer L1, the size of the component mounting areas on the first interconnection layer L1 is not reduced by the inner layer via-holes 16. This permits higher density mounting. Since the inner layer via-holes 16 are thus formed from the second interconnection layer L2 (inner surface interconnection layer) so as not to extend through the first interconnection layer L1 (outer surface interconnection layer), the first interconnection layer L1 (outer surface interconnection layer) is not influenced by the plating of the inner peripheral surfaces of the inner layer via-holes 16, and is free from the reduction in the size of the component mounting areas. This makes it possible to properly mount electronic devices and electronic components at a higher density on the first interconnection layer L1 finely processed.
  • the first double-sided FPC 3 has the second interconnection layer L2 provided as the inner surface interconnection layer on the inner side in opposed relation to the bonding sheet 2, and has the first interconnection layer L1 provided as the outer surface interconnection layer on the outer side in association with the second interconnection layer L2.
  • an inner surface 131 of the insulating film 13 faces the bonding sheet absent portion 12 in the absence of the second interconnection layer L2.
  • a first interconnection layer 14L is provided as a signal line on the outer side of the insulating film 13 in this region.
  • the second double-sided FPC 4 basically has the same construction as the first double-sided FPC 3, and is disposed symmetrically to the first double-sided FPC 3 with respect to the bonding sheet 2.
  • the second double-sided FPC 4 includes an insulating film 21, a third interconnection layer L3 as an inner surface interconnection layer, a fourth interconnection layer L4 as an outer surface interconnection layer, inner layer via-holes 24 formed from the side of the third interconnection layer L3, a signal line 22L provided in the fourth interconnection layer L4, an adhesive 20 and a cover layer 25, which correspond to the insulating film 13, the second interconnection layer L2, the first interconnection layer L1, the inner layer via-holes 16, the signal line layer 14L, the adhesive 19 and the cover layer 17, respectively, of the first double-sided FPC 3. Since these components each have the same constructions as the corresponding components, duplicate description will be omitted.
  • the fourth interconnection layer L4 (outer surface interconnection layer) is not covered with the plating in the second double-sided FPC 4. This ensures provision of a minute circuit configuration in the fourth interconnection layer L4. Since the inner layer via-holes 24 do not extend through the fourth interconnection layer L4, the size of component mounting areas on the fourth interconnection layer L4 is not reduced by the inner layer via-holes 24.
  • Fig. 2 is a schematic sectional view of a laminate structure of the multilayer FPC 1 of this embodiment fabricated by laminating the first double-sided FPC 3 and the second double-sided FPC 4 described with reference to Fig. 1 in contact with the opposite surfaces of the bonding sheet 2 by heat and pressure.
  • the laminating of the first double-sided FPC 3 and the second double-sided FPC 4 via the bonding sheet 2 is achieved through a batch laminating process by simultaneously and collectively subjecting the first double-sided FPC 3, the bonding sheet 2 and the second double-sided FPC 4 to a heat and pressure treatment.
  • the laminating process is performed at a heating temperature of about 170 degrees Celsius at a pressure of about 3 MPa for a processing period of about 30 minutes.
  • the first double-sided FPC 3 and the second double-sided FPC 4 are collectively laminated via the bonding sheet 2 by heat and pressure, whereby the electrically conductive paste 11 filled in the respective holes 7 to 10 of the bonding sheet 2 is electrically connected to a circuit of the second interconnection layer L2 of the first double-sided FPC 3 and to a circuit of the third interconnection layer L3 of the second double-sided FPC 4.
  • the holes 7 to 10 and the electrically conductive paste 11 serve as via-holes to electrically connect the second interconnection layer L2 (inner surface interconnection layer) of the first double-sided FPC 3 and the third interconnection layer L3 (inner surface interconnection layer) of the second double-sided FPC 4.
  • the first double-sided FPC 3 and the second double-sided FPC 4 are bonded to each other by the bonding sheet 2.
  • the first double-sided FPC 3 and the second double-sided FPC 4 are laminated with the second interconnection layer L2 and the third interconnection layer L3 thereof being embedded in the bonding sheet 2 from the surfaces of the bonding sheet 2. That is, the thicknesses of the second interconnection layer L2 and the third interconnection layer L3 are accommodated by the bonding sheet 2 in which the second interconnection layer L2 and the third interconnection layer L3 are embedded. Therefore, an interlayer distance between the first double-sided FPC 3 and the second double-sided FPC 4 of the multilayer FPC 1 is substantially equivalent to the thickness of the bonding sheet 2.
  • the multilayer FPC 1 has a reduced thickness.
  • Fig. 3 is a schematic sectional view of a finished product obtained by covering an outer surface of the multilayer FPC 1 of Fig. 2 with a cover coat for surface treatment, and then subjecting the multilayer FPC 1 to a preliminary processing step and an inspection step.
  • an upper surface portion of the first interconnection layer L1 except for the component mounting areas is coated with a cover coat 27 for protection of the first interconnection layer L1 with the cover coat 27.
  • a surface portion of the fourth interconnection layer L4 except for the component mounting areas is coated with a cover coat 28 for protection of the fourth interconnection layer L4 with the cover coat 28.
  • Figs. 4A and 4B are diagrams for comparison between the sectional configuration of a prior-art multilayer FPC and the sectional configuration of the multilayer FPC 1 according to the embodiment of the present invention.
  • the prior-art multilayer FPC of Fig. 4A is configured such that the second interconnection layer L2 is covered with a polyamide cover lay film 31 bonded to the surface thereof by an adhesive 36, and the third interconnection layer L3 is covered with a cover lay film 32 bonded to the surface thereof by an adhesive 38.
  • the second interconnection layer L2 and the third interconnection layer L3 are connected to each other via the cover lay films 31, 32 by a bonding sheet 33.
  • the second interconnection layer L2 and the third interconnection layer L3 are not embedded in the bonding sheet 33, so that the distance between the second interconnection layer L2 and the third interconnection layer L3 is the sum of the thicknesses of the cover lay film 31, the bonding sheet 33 and the cover layer film 32.
  • the first interconnection layer L1 and the second interconnection layer L2 are electrically connected to each other via so-called blind via-holes (BVHs) 34 extending from the outer layer to the inner layer.
  • the third interconnection layer L3 and the fourth interconnection layer L4 are electrically connected to each other via BVHs 34. Therefore, portions of the first interconnection layer L1 and the fourth interconnection layer L4 formed with the BVHs 34 cannot be used as component mounting areas. This reduces the size of the component mounting areas on the first interconnection layer L1 and the fourth interconnection layer L4.
  • the first interconnection layer L1, the second interconnection layer L2, the third interconnection layer L3 and the fourth interconnection layer L4 are electrically connected to each other via through-via-holes (TVHs) 35. Therefore, the presence of the TVHs 35 also reduces the size of the component mounting areas on the first interconnection layer L1 and the fourth interconnection layer L4.
  • the multilayer FPC 1 of Fig. 4B according to the embodiment of the present invention is configured such that the second interconnection layer L2 and the third interconnection layer L3 are directly connected to the bonding sheet 2 as being embedded in the bonding sheet 2. Therefore, the distance between the first double-sided FPC 3 and the second double-sided FPC 4 is substantially equivalent to the thickness of the bonding sheet 2.
  • the thickness reduction of the multilayer FPC 1 is achieved.
  • the second interconnection layer L2 and the third interconnection layer L3 are electrically connected to each other by the electrically conductive paste 11 filled in the holes preliminarily formed in the bonding sheet 2. This eliminates the need for the formation of the through-via-holes (TVHs).
  • Figs. 5A and 5B are diagrams for comparison between a fabrication process for the prior-art multilayer FPC of Fig. 4A and a fabrication process for the multilayer FPC 1 of Fig. 4B according to the embodiment of the present invention.
  • the prior-art multilayer FPC fabrication process of Fig. 5A includes ten steps for the fabrication of the prior-art multilayer FPC.
  • the multilayer FPC fabrication process of Fig. 5B according to the embodiment of the present invention includes eight steps for the fabrication of the multilayer FPC 1. That is, the number of the steps for the fabrication of the multilayer FPC 1 according to the embodiment of the present invention is smaller by two than that for the fabrication of the prior-art multilayer FPC. Thus, the fabrication time can be reduced.
  • a first double-sided FPC substrate (flexible copper clad laminate) and a second double-sided FPC substrate are prepared (Step A1), and inner layer circuits are formed on the respective double-sided FPC substrates (Step A2). Then, the inner layer circuits are covered with inner layer cover layers (Step A3). At the same time, a bonding sheet is prepared (Step A3). Then, a first double-sided FPC (which is herein defined as including the FPC substrate and a circuit formed on the FPC substrate) and a second double-sided FPC are laminated via the bonding sheet (Step A4).
  • blind via-holes are formed in the first double-sided FPC and the second double-sided FPC from outer sides by laser processing (Step A5), and through-via-holes (TVHs) are formed as extending through the first double-sided FPC, the bonding sheet and the second double-sided FPC by drilling (Step A6).
  • inner peripheral surfaces of the via-holes are plated with copper (Step A7), and outer layer circuits are formed on the first double-sided FPC and the second double-sided FPC (Step A8).
  • cover coat layers are formed on the first double-sided FPC and the second double-sided FPC (Step A9), and a surface treatment (gold plating or the like) is performed on the first double-sided FPC and the second double-sided FPC (Step A10).
  • a surface treatment gold plating or the like
  • the multilayer FPC 1 of the embodiment of the present invention is fabricated in the following manner.
  • a first double-sided FPC substrate and a second double-sided FPC substrate are prepared (Step B1), and inner layer via-holes are formed in a second interconnection layer L2 and a third interconnection layer L3 by laser processing (Step B2).
  • the inner layer via-holes are plated with copper (Step B3).
  • inner layer circuits and outer layer circuits are formed on the first double-sided FPC substrate and the second double-sided FPC substrate (Step B4) and, at the same time, a bonding sheet is prepared (Step B4).
  • Step B5 the outer layer circuits are covered with cover layers
  • Step B5 the outer layer circuits are covered with cover layers
  • Step B5 the outer layer circuits are covered with cover layers
  • Step B6 the resulting first double-sided FPC and the resulting second double-sided FPC are laminated via the bonding sheet
  • Step B7 cover coat layers are formed on the first double-sided FPC and the second double-sided FPC
  • a surface treatment gold plating or the like
  • Fig. 6 is a schematic sectional view showing the construction of a multilayer FPC 51 according to another embodiment of the present invention.
  • the multilayer FPC 51 shown in Fig. 6 is a so-called partial multilayer FPC which has a multilayer structure provided at a desired position. More specifically, a first double-sided FPC 52 includes a first interconnection layer L1 and second interconnection layers L2 provided on opposite surfaces of an insulating base film 13. In Fig. 6, the first double-sided FPC 52 has a double-sided circuit portion 53 provided on a left side, and a double-sided circuit portion 55 provided on a right side and connected to the double-sided circuit portion 53 via a signal line portion 54 which is a single-sided circuit portion.
  • the second interconnection layers L2 of the first double-sided FPC 52 have inner layer via-holes 16 formed at predetermined positions thereof, for example, by laser processing.
  • the inner peripheral surfaces of the inner layer via-holes 16 are, for example, plated with copper.
  • the first interconnection layer L1 is not covered with the copper plating, so that a minute circuit of the first interconnection layer L1 is not influenced by the plating.
  • the first interconnection layer L1 is free from reduction in the size of component mounting areas on which electronic components and the like are mounted.
  • the second double-sided FPC 60 is provided only on the second interconnection layer L2 present in the double-sided circuit portion 53 of the first double-sided FPC 52.
  • the second double-sided FPC 60 includes a third interconnection layer L3 and a fourth interconnection layer L4 provided on opposite surfaces of an insulating base film 21.
  • the third interconnection layer L3 has inner layer via-holes 24 through which the third interconnection layer L3 and the fourth interconnection layer L4 are electrically connected to each other.
  • the second double-sided FPC 60 and the double-sided circuit portion 53 of the first double-sided FPC 52 are laminated via a bonding sheet 2. Like the bonding sheet 2 previously described, this bonding sheet 2 has through-holes formed at predetermined positions and filled with an electrically conductive paste 11. The second interconnection layer L2 and the third interconnection layer L3 are electrically connected to each other by the electrically conductive paste 11.
  • the inventive multilayer FPC may be thus provided as the partial multilayer FPC 51 which has a multilayer structure provided at a desired position.
  • reference characters 27, 28 denote cover coat layers.
  • Fig. 7 is a schematic sectional view showing the construction of a multilayer FPC 71 according to further another embodiment of the present invention.
  • the multilayer FPC 71 shown in Fig. 7 has the same basic construction as the multilayer FPC 1 shown in Fig. 3, and like components will be denoted by like reference characters.
  • a feature of the multilayer FPC 71 shown in Fig. 7 is that a signal line portion 72 of a first double-sided FPC 3 and a signal line portion 73 of a second double-sided FPC 4 opposed to each other through a hollow portion 12 have slightly different lengths as measured laterally in Fig. 7.
  • the multilayer FPC 71 is a circuit board to be mounted in a foldable mobile phone, for example, the multilayer FPC 71 is frequently switched between a folded state in which the signal line portions 72, 73 are bent about 180 degrees and a straight state in which the signal line portions 72, 73 extend generally straight.
  • the multilayer FPC 71 is required to have folding endurance sufficient to endure the frequent switching between the folded state and the straight state with the signal line portions 72, 73 kept parallel to each other with the intervention of the hollow portion 12. Therefore, where the multilayer FPC 71 is folded with the signal line portion 72 located on an inner side and with the signal line portion 73 located on an outer side, for example, the multilayer FPC 71 is designed so that the signal line portion 72 located on the inner side has a smaller length than the signal line portion 73 located on the outer side.
  • the signal line portions 72 and 73 are less liable to receive compressive or tensile stresses during the folding of the multilayer FPC 71, so that the multilayer FPC 71 has an improved bendability during the folding.
  • the inner FPC 3 has a length M1
  • the outer FPC 4 has a length M2
  • the outer FPC 4 is bent as having a curvature radius r, and the hollow portion 12, the FPC 3 and the FPC 4 have thicknesses D, t3 and t4, respectively, as shown in Fig. 8.
  • M is the basic length of the FPC 3 and the FPC 4.
  • Fig. 9 is a schematic sectional view showing the construction of a multilayer FPC 91 according to still another embodiment of the present invention.
  • the multilayer FPC 91 shown in Fig. 9 is a multilayer FPC having a six-layer structure including six interconnection layers. More specifically, the multilayer FPC 91 includes a first double-sided FPC 3 having a first interconnection layer L1 and a second interconnection layer L2, and a second double-sided FPC 4 having a fifth interconnection layer L5 and a sixth interconnection layer L6. The multilayer FPC 91 further includes a multilayer structure 911 provided between the double-sided FPCs 3 and 4.
  • the multilayer structure 911 includes two upper and lower bonding sheets 2, and a single double-sided FPC, i.e., a third double-sided FPC 92, disposed between the two bonding sheets 2.
  • the third double-sided FPC 92 includes a third interconnection layer L3 and a fourth interconnection layer L4.
  • the first double-sided FPC 3 and the second double-sided FPC 4 respectively have substantially the same constructions as the first double-sided FPC 3 and the second double-sided FPC 4 described with reference to Fig. 1.
  • the multilayer structure 911 is divided into right and left parts as shown in Fig. 9 in the absence of its laterally intermediate portion, and the right part and the left part are spaced from each other by a hollow portion 12.
  • Right and left parts of the third double-sided FPC 92 each have via-holes 93 for electrical connection between the third interconnection layer L3 and the fourth interconnection layer L4.
  • the bonding sheets 2 each have through-holes filled with an electrically conductive paste 11, and are respectively provided between the first double-sided FPC 3 and the third double-sided FPC 92 and between the third double-sided FPC 92 and the second double-sided FPC 4.
  • the first double-sided FPC 3, the third double-sided FPC 92 and the second double-sided FPC 4 are laminated via the bonding sheets 2.
  • the multilayer structure 911 is configured such that N bonding sheets (N is a natural number and N is greater than or equal to 2) and N-1 double-sided FPCs are alternately stacked between the first double-sided FPC 3 and the second double-sided FPC 4 with outermost ones of the bonding sheets being located in outer surfaces (upper and lower surfaces in Fig. 9) of the multilayer structure 911, whereby the multilayer FPC 91 has a multilayer structure including six or more interconnection layers.
  • a double-sided rigid printed circuit board or a board prepared by laminating a double-sided FPC and a double-sided rigid circuit board may be used instead of the third double-sided FPC 92.
  • the resulting multilayer FPC 91 has a reduced thickness as in the first embodiment.
  • a single-sided FPC (having an outer layer circuit alone) may be employed instead of one of the double-sided FPCs.
  • a multilayer FPC is fabricated by laser-processing a base film, providing connection terminals on the base film for connection to the outer layer circuit, and connecting the connection terminals to electrically conductive paste plugs provided in the bonding sheet.
  • the embodiments of the present invention are mainly directed to the multilayer FPCs each having the hollow portion in which the bonding sheet is absent, the inventive multilayer FPC may have no hollow portion. It should be understood that the present invention be not limited to the embodiments described above, but various modifications may be made within the scope of the following claims.
  • Multilayer FPCs 2 Bonding sheet 3: First double-sided FPC 4: Second double-sided FPC 7, 8, 9, 10: Holes 11: Electrically conductive paste 12: Bonding sheet absent portion (hollow portion) 911: Multilayer structure L1: First interconnection layer (outer surface interconnection layer) L2: Second interconnection layer (inner surface interconnection layer) L3: Third interconnection layer (inner surface interconnection layer) L4: Fourth interconnection layer (outer surface interconnection layer)

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
PCT/JP2010/001358 2009-08-12 2010-03-01 Multilayer flexible printed circuit board, and method for fabricating the same WO2011018862A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201080035312.6A CN102474985B (zh) 2009-08-12 2010-03-01 多层柔性印刷电路板和用于制造该多层柔性印刷电路板的方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009187306A JP4768059B2 (ja) 2009-08-12 2009-08-12 多層フレキシブルプリント配線板
JP2009-187306 2009-08-12

Publications (1)

Publication Number Publication Date
WO2011018862A1 true WO2011018862A1 (en) 2011-02-17

Family

ID=42180882

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2010/001358 WO2011018862A1 (en) 2009-08-12 2010-03-01 Multilayer flexible printed circuit board, and method for fabricating the same

Country Status (5)

Country Link
JP (1) JP4768059B2 (zh)
KR (1) KR101580203B1 (zh)
CN (1) CN102474985B (zh)
TW (1) TWI474767B (zh)
WO (1) WO2011018862A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102752955A (zh) * 2011-04-20 2012-10-24 易鼎股份有限公司 具有局部分离区段的多层叠置电路排线

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8895864B2 (en) * 2012-03-30 2014-11-25 Nokia Corporation Deformable apparatus and method
CN103635036A (zh) * 2012-08-22 2014-03-12 富葵精密组件(深圳)有限公司 柔性多层电路板及其制作方法
EP2991460B1 (en) 2014-08-29 2018-11-21 Nokia Technologies OY An apparatus and associated methods for deformable electronics
CN105682354A (zh) * 2016-02-25 2016-06-15 广东欧珀移动通信有限公司 软硬结合板及终端
CN110959314A (zh) * 2017-08-04 2020-04-03 株式会社藤仓 多层印刷布线板的制造方法以及多层印刷布线板
CN107949152B (zh) * 2017-11-30 2024-04-09 广州兴森快捷电路科技有限公司 刚挠结合线路板的制作方法
KR20210020673A (ko) * 2019-08-16 2021-02-24 삼성전기주식회사 인쇄회로기판
CN110557894A (zh) * 2019-10-15 2019-12-10 深圳市华旭达精密电路科技有限公司 一种多层镂空软板开盖工艺

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0723388A1 (en) * 1995-01-20 1996-07-24 Matsushita Electric Industrial Co., Ltd Printed circuit board
JP2000036664A (ja) * 1998-05-14 2000-02-02 Matsushita Electric Ind Co Ltd 多層配線基板およびその製造方法
JP2005347414A (ja) 2004-06-01 2005-12-15 Hitachi Metals Ltd 接着シート及びそれを用いた両面プリント基板或いは多層プリント基板
JP2006179679A (ja) 2004-12-22 2006-07-06 Fujikura Ltd フレキシブルプリント配線板及びその製造方法
JP2006299209A (ja) 2005-04-25 2006-11-02 Matsushita Electric Works Ltd ボンディングシートとそれを用いた多層フレキシブルプリント配線板
WO2007046459A1 (ja) 2005-10-20 2007-04-26 Matsushita Electric Industrial Co., Ltd. 多層プリント配線基板及びその製造方法
JP4109156B2 (ja) 2002-05-31 2008-07-02 タツタ電線株式会社 導電性ペースト
JP4191678B2 (ja) 2002-05-31 2008-12-03 タツタ電線株式会社 導電性ペースト、これを用いた多層基板及びその製造方法
JP4237726B2 (ja) 2005-04-25 2009-03-11 パナソニック電工株式会社 フレキシブルプリント配線板用基材入り接着シート及びその製造方法、多層フレキシブルプリント配線板、フレックスリジッドプリント配線板

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06204664A (ja) * 1992-12-28 1994-07-22 Dai Ichi Kogyo Seiyaku Co Ltd 多層化基板
JPH10190158A (ja) * 1996-12-27 1998-07-21 Cmk Corp リジッド・フレックスプリント配線板およびその製造方法
SG86345A1 (en) * 1998-05-14 2002-02-19 Matsushita Electric Ind Co Ltd Circuit board and method of manufacturing the same
JP3744383B2 (ja) * 2000-06-09 2006-02-08 松下電器産業株式会社 複合配線基板及びその製造方法
JP2002232135A (ja) * 2001-01-30 2002-08-16 Matsushita Electric Ind Co Ltd 積層用両面回路基板とその製造方法及びそれを用いた多層プリント配線板
JP2003133734A (ja) * 2001-10-24 2003-05-09 Nippon Mektron Ltd ケーブル部を有するフレキシブルプリント基板
JP2003258426A (ja) * 2002-03-07 2003-09-12 Cmk Corp リジッド・フレックス多層基板
JP2004296481A (ja) * 2003-03-25 2004-10-21 Nitto Denko Corp 多層配線回路基板
JP2006066458A (ja) * 2004-08-24 2006-03-09 Sharp Corp 多層プリント配線板及び多層プリント配線板の製造方法
JP4481184B2 (ja) * 2005-02-07 2010-06-16 日本メクトロン株式会社 多層フレキシブル回路基板の製造方法
KR100651335B1 (ko) * 2005-02-25 2006-11-29 삼성전기주식회사 경연성 인쇄회로기판 및 그 제조 방법
JP2006324406A (ja) * 2005-05-18 2006-11-30 Sharp Corp フレックスリジッド多層配線板
JP2007059822A (ja) * 2005-08-26 2007-03-08 Nippon Steel Chem Co Ltd ヒンジ基板及びその製造方法
JP4817771B2 (ja) * 2005-09-09 2011-11-16 株式会社フジクラ 多層プリント配線板の製造方法
TWI336608B (en) * 2006-01-31 2011-01-21 Sony Corp Printed circuit board assembly and method of manufacturing the same

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0723388A1 (en) * 1995-01-20 1996-07-24 Matsushita Electric Industrial Co., Ltd Printed circuit board
JP2000036664A (ja) * 1998-05-14 2000-02-02 Matsushita Electric Ind Co Ltd 多層配線基板およびその製造方法
JP4109156B2 (ja) 2002-05-31 2008-07-02 タツタ電線株式会社 導電性ペースト
JP4191678B2 (ja) 2002-05-31 2008-12-03 タツタ電線株式会社 導電性ペースト、これを用いた多層基板及びその製造方法
JP2005347414A (ja) 2004-06-01 2005-12-15 Hitachi Metals Ltd 接着シート及びそれを用いた両面プリント基板或いは多層プリント基板
JP2006179679A (ja) 2004-12-22 2006-07-06 Fujikura Ltd フレキシブルプリント配線板及びその製造方法
JP2006299209A (ja) 2005-04-25 2006-11-02 Matsushita Electric Works Ltd ボンディングシートとそれを用いた多層フレキシブルプリント配線板
JP4237726B2 (ja) 2005-04-25 2009-03-11 パナソニック電工株式会社 フレキシブルプリント配線板用基材入り接着シート及びその製造方法、多層フレキシブルプリント配線板、フレックスリジッドプリント配線板
WO2007046459A1 (ja) 2005-10-20 2007-04-26 Matsushita Electric Industrial Co., Ltd. 多層プリント配線基板及びその製造方法
EP1814373A1 (en) * 2005-10-20 2007-08-01 Matsushita Electric Industrial Co., Ltd. Multilayer printed wiring board and its manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102752955A (zh) * 2011-04-20 2012-10-24 易鼎股份有限公司 具有局部分离区段的多层叠置电路排线
US20120267156A1 (en) * 2011-04-20 2012-10-25 Advanced Flexible Circuits Co., Ltd. Multilayer stacked circuit arrangement with localized separation section
US8513533B2 (en) * 2011-04-20 2013-08-20 Advanced Flexible Circuits Co., Ltd. Multilayer stacked circuit arrangement with localized separation section

Also Published As

Publication number Publication date
CN102474985A (zh) 2012-05-23
TWI474767B (zh) 2015-02-21
KR101580203B1 (ko) 2015-12-24
JP4768059B2 (ja) 2011-09-07
TW201117692A (en) 2011-05-16
CN102474985B (zh) 2015-11-25
KR20120071387A (ko) 2012-07-02
JP2011040607A (ja) 2011-02-24

Similar Documents

Publication Publication Date Title
WO2011018862A1 (en) Multilayer flexible printed circuit board, and method for fabricating the same
US8404978B2 (en) Flex-rigid wiring board and method for manufacturing the same
JP6426067B2 (ja) 多層フレキシブルプリント配線板およびその製造方法
KR100651535B1 (ko) 경연성 인쇄회로기판 및 그 제조방법
US11089674B2 (en) Wiring substrate and method for manufacturing wiring substrate
JP2017157792A (ja) 電子部品内蔵基板及びその製造方法
JP6880429B2 (ja) 素子内蔵型印刷回路基板及びその製造方法
JP4287733B2 (ja) 電子部品内蔵多層プリント配線板
US20110100698A1 (en) Wiring board and method for manufacturing the same
CN101257773B (zh) 多层印刷电路板的制造方法
KR20040061409A (ko) 비아홀이 필요없는 양면 인쇄회로기판 및 그 제조방법
KR20220072540A (ko) 플렉서블 인쇄회로기판 및 이를 포함하는 전자장치
JP5118238B2 (ja) 耐食性と歩留まりを向上させたプリント基板
JP2004349277A (ja) 多層配線基板及びその製造方法
US20060060377A1 (en) Method of forming a multi-layer printed circuit board and the product thereof
JP2009010266A (ja) プリント配線板の製造方法及びプリント配線板
JP5204871B2 (ja) 部分多層フレキシブルプリント配線板
JP2017157793A (ja) 電子部品内蔵基板
JP5931483B2 (ja) 部品内蔵多層プリント配線板の製造方法、および部品内蔵多層プリント配線板
KR100467844B1 (ko) 휴대폰용 리지드 플렉시블 인쇄회로기판 및 이의 제조방법
JP2011091312A (ja) リジッドフレックス回路板、リジッドフレックス回路板の製造方法および電子機器
TWI433630B (zh) Method for manufacturing multilayer flexible wiring board
JP2007288023A (ja) リジッドフレックス多層プリント配線板の製造方法
WO2015083216A1 (ja) 多層基板、及び、その製造方法
JP2021027167A (ja) 配線基板

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 201080035312.6

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10707364

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 20127006436

Country of ref document: KR

Kind code of ref document: A

122 Ep: pct application non-entry in european phase

Ref document number: 10707364

Country of ref document: EP

Kind code of ref document: A1