WO2011017843A1 - 一种高密度、高鲁棒性的亚阈值存储单元电路 - Google Patents

一种高密度、高鲁棒性的亚阈值存储单元电路 Download PDF

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Publication number
WO2011017843A1
WO2011017843A1 PCT/CN2009/073250 CN2009073250W WO2011017843A1 WO 2011017843 A1 WO2011017843 A1 WO 2011017843A1 CN 2009073250 W CN2009073250 W CN 2009073250W WO 2011017843 A1 WO2011017843 A1 WO 2011017843A1
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Prior art keywords
transistor
nmos
memory cell
nmos transistor
drain
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PCT/CN2009/073250
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English (en)
French (fr)
Inventor
杨军
柏娜
李�杰
胡晨
时龙兴
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东南大学
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Application filed by 东南大学 filed Critical 东南大学
Priority to EP09848173.2A priority Critical patent/EP2461327B1/en
Priority to PCT/CN2009/073250 priority patent/WO2011017843A1/zh
Priority to US13/322,859 priority patent/US8559213B2/en
Priority to KR1020117022769A priority patent/KR101252393B1/ko
Priority to JP2012524076A priority patent/JP5237504B2/ja
Publication of WO2011017843A1 publication Critical patent/WO2011017843A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Definitions

  • the present invention relates to memory cells in subthreshold working regions, and more particularly to a high density, highly robust subthreshold memory cell circuit. It can work at a power supply voltage of 200mV, combining high density, high robustness, and ultra-low power consumption. Background technique
  • Storage cell arrays are an important part of modern digital systems and are often the bottleneck of system design.
  • Subthreshold design is a hot topic in current ultra low power designs.
  • Vdd supply voltage
  • Vth threshold voltage
  • the read noise margin is minimal compared to maintaining the noise margin and the write noise margin. So it is a key design indicator for memory cell design.
  • Some people can add two NMOS tubes to the design of the traditional 6-tube memory cell, so that the internal information does not interfere with the information of the internal nodes during the readout process.
  • the read noise margin of the sub-threshold memory cell is equal to the hold noise margin of the cell.
  • this type of storage unit consumes 30% more area.
  • Another person has proposed a single-ended 6-tube sub-threshold memory unit. Although the single-ended structure makes the memory cell more robust during the read operation, the write capability of this structure is weak, and the assistance of the write assist unit is required during the write process.
  • the design in order to solve the problem that the subthreshold circuit characteristics are susceptible to process variations, the design generally adopts a larger size transistor. Thus, the density of the design will also be affected.
  • the sub-threshold design technique can reduce the system power consumption in a squared relationship.
  • the design of the sub-threshold memory circuit has confirmed that the dynamic power consumption of the memory cell and the static power consumption can be reduced as the power supply voltage decreases. This reduced power consumption will be significant considering the capacity of the memory cell array.
  • the circuit in the subthreshold region has its own unique circuit characteristics.
  • Conventional design In the value state, the method of adjusting the size of each transistor of the memory cell to achieve the trade-off of memory cell read capability, write capability and chip area consumption has been completely unable to meet the requirements of sub-threshold circuit design. Therefore, the high-density, highly robust sub-threshold memory cell design is the bottleneck that sub-threshold circuit design can really go to industrialization. Summary of the invention
  • the object of the present invention is to overcome the shortcomings of the prior art and provide a high-density, high-resistance sub-threshold memory cell circuit, in order to balance the various indexes of the memory cell to achieve optimal system performance.
  • the present invention designs a double-ended, single-ended read high-density, high-lust memory cell for the practical characteristics of a sub-threshold circuit. It can achieve the write noise margin, the read noise tolerance, and the noise margin while ensuring the ultra-low power consumption of the system.
  • the high-density design allows the memory cell array to consume the chip area which is the smallest of the currently known chips. This makes the sub-threshold storage unit industrialized and commercialized.
  • a high-density, highly robust sub-threshold memory cell circuit characterized by: comprising two PMOS transistors P1 and P2, five NMOS transistors N1, N2, N3, N4 and N5, and a total of seven transistors Double-ended write, high-density, highly robust sub-threshold memory cell circuit for single-ended read; wherein each of the two PMOS transistors and the NMOS transistors N3, N4, and N5 are connected to the gate terminal of the transistor, the NMOS transistor The body terminal and the source terminal of N1 and N2 are grounded, and the source ends of the two PMOS transistors are connected to the power supply voltage.
  • the drain terminal and the gate terminal of the NMOS transistor N1 are respectively connected with the drain terminal and the gate terminal of the PMOS transistor P1 to form an inverse.
  • the drain terminal and the gate terminal of the NMOS transistor N2 are respectively connected with the drain terminal and the gate terminal of the PMOS transistor P2 to form another inverter; the drain terminal of the NMOS transistor N1 and the drain terminal of the PMOS transistor P1 and the gate of the NMOS transistor N2
  • the terminals of the PMOS transistor P2 are connected together, and the connection between the gate end of the NMOS transistor N1 and the gate terminal of the PMOS transistor P1 and the drain terminal of the NMOS transistor N2 and the drain terminal of the PMOS transistor P2 are respectively connected to the NMOS transistor N5.
  • the gate of the NMOS transistor N5 and the external control signal are read.
  • the inversion signal connection of the word line, the connection end between the drain end of the NMOS transistor N1 and the drain end of the PMOS transistor P1 and the write bit line are respectively connected at either end of the source and drain ends of the NMOS transistor N3, and the gate terminal of the NMOS transistor N3
  • the write line, the connection end between the N2 drain terminal of the NMOS transistor and the drain terminal of the PMOS transistor P2 and the shared bit line of the non-read bit line of the write bit line are respectively connected at either end of the source and drain ends of the NMOS transistor N4, the NMOS transistor
  • the N4 gate is connected to the word line shared by the write word line and the read word line.
  • the NMOS transistors N3 and N4 function as matching tubes, and the NMOS transistor N5 functions as a shutdown tube. Since the circuit of the present invention is designed to operate in a memory cell, the operating state of the circuit is determined.
  • the source and drain terminals of the three transistors N3, N4, and N5 can be dynamically converted with each other, and can be automatically converted according to the potential changes of the two terminals connected to the source and the drain respectively. Therefore, the source and drain terminals of N3, N4, and N5 can be arbitrarily connected to their corresponding terminals.
  • the present invention has the following advantages and remarkable effects:
  • the unit area consumption is the smallest in the currently known subthreshold memory cells.
  • the circuit structure of the 7 transistors is simple and reliable.
  • the invention is less affected by process variations, each transistor being of a minimum size design with no proportional design requirements.
  • the body terminals of the P1, P2, N3 ⁇ N5 transistors are all connected to the gate terminals of the corresponding transistors.
  • the connection of the body ends of N1 and N2 to the conventional ground allows the present invention to increase the turn-off current of the memory cell matching tube while ensuring the balance of the pull-up and pull-down driving capabilities.
  • the turn-on and turn-off current of the present invention is the largest in the turn-on and turn-off current of sub-threshold memory cells of the currently known design. Thus, the influence of the leakage current accumulated in the unselected memory cells is correspondingly weak.
  • the present invention can support more memory cells on the same bit line. This, on the other hand, solves the problem of fewer tandem memory cells on the same bit line that are ubiquitous in sub-threshold memory cell arrays. The capacity and density of the subthreshold memory cell array are increased.
  • FIG. 1 is a circuit diagram of a high-density, high-resistance subthreshold memory cell of the present invention
  • FIG. 2 is a logic block diagram of a column of subthreshold memory arrays and a schematic diagram of the influence of bit line leakage current in the worst case;
  • FIG. 3 is a bit line output waveform diagram when "1" is read when a conventional subthreshold memory cell is connected in series with 64 memory cells on the same bit line;
  • 4 is a bit line output waveform diagram when "0" is read when a conventional subthreshold memory cell is connected in series with 64 memory cells on the same bit line;
  • Figure 5 is a bit line of the present invention when reading "1" operation under the same conditions as a conventional subthreshold memory cell. Output waveform graph comparison. detailed description:
  • the high density, high robust subthreshold memory cell circuit of the present invention is composed of seven transistors, two P-type transistors (PI, P2) and five N-type transistors (N1 to N5).
  • the body ends of the PI, P2, N3 ⁇ N5 transistors are all connected to the gate terminals of the corresponding transistors.
  • the body ends of Nl, N2 are connected to the conventional ground gnd.
  • Nl, PI, and N2 P2 form two inverters (INV1, INV2) respectively, and the middle is connected by the turn-off tube N5 to be cross-coupled: the output of INV1 consisting of N1, PI is directly connected to N2 , P2 is composed of the input terminal of INV2; and the output terminal of INV2 is connected to the input terminal of INV1 via the cut-off pipe N5.
  • the gate of N5 is connected to the inverted signal E of the external control signal read word line (RWL).
  • N3, N4 are matching tubes: INV1 and write bit line (WBL) are connected through N3, and the write terminal (WWL) is connected to the gate terminal of N3; the bit line shared by INV2 and the non-read bit line of the write bit line is connected through N4 ( ⁇ I+RBL), the gate terminal of N4 is connected to the shared word line (WWL+RWL) of the write word line and the read word line.
  • the read operation is to effectively control the turn-on transistor N4 by reading the word line RWL signal, turn off the cut-off tube N5, and transfer the internal signal of the memory cell to the read bit line (RBL), only by the single-ended
  • the logic signal on the read bit line identifies the internal information of the memory unit and completes the single-ended read operation.
  • the write operation is controlled by the WWL signal, the read word line RWL signal is invalid, the matching transistors N3, N4, and the cut-off tube N5 are all turned on.
  • the signal on the non-( ⁇ ) of the write word line (WBL) and the write bit line will be transmitted to the internal node through the matching transistors ⁇ 3, ⁇ 4, and the information inside the memory cell will be changed to complete the double-ended write operation.
  • the present invention connects the memory cell pull-up tube PI, ⁇ 2 and the matching tube ⁇ 3, ⁇ 4 and the body end of the shutdown tube ⁇ 5 to the gate terminal, and the body of N1, ⁇ 2 The end is still directly connected to the ground gnd.
  • the invention adopts this method to properly solve the limitation of the storage unit on each bit line caused by the reading "1" operation while satisfying the balance of the read/write capability of the storage unit.
  • Another advantage of using this connection method is that the present invention is less affected by process variations, so that better process tolerance tolerance can be obtained without increasing the specific size of the memory cell transistors, that is, the present invention uses only the minimum size. Transistor design, a logic cell array consisting of the present invention can achieve good yields.
  • the working principle of the high density, high robust subthreshold memory cell circuit of the present invention is as follows: A, read operation
  • the shut-off tube N5 Since the shut-off tube N5 is turned off during the reading of the present invention, the voltage value of Q1 does not change significantly with the change of the Q value. In this way, signal interference of external information to the internal nodes of the storage unit is avoided. The problem that the sub-threshold storage unit has a small read noise margin is also solved.
  • the read bit line (RBL) is set to 0 and the turn-off tube (N5) is turned on (
  • the positive feedback of the structure of the double-ended write and the cross-coupling of the two inverters (INV1, INV2) guarantees the write and hold noise tolerance of the present invention.
  • the turn-off current ratio (Ion/Ioff) is one of the important indicators for memory cell array design. In normal design (under super-threshold state), the turn-on and turn-off current ratio (Ion/Ioff) is approximately 10 7 , whereas in subthreshold designs this value is only 10 3 -10 4 . If there is not enough redundancy (the number of serial memory cells on the bit line is greater than a certain limit), the turn-on current of the selected cell may be disturbed by the accumulated leakage current of the unselected memory cell, so that subsequent circuits cannot recognize the correct one. Logic, causing read and write failure of the memory unit ( Figure 2). The number of memory cells on a single bit line is further limited, taking into account process variations and the bias voltage of subsequent sensitive amplifiers.
  • Figures 3 and 4 show the simulation results of reading "1" and reading "0" under 64 memory cells in series on each bit line. All transistors are of minimum transistor width and are conventionally connected (the body of the P-type transistor is connected to the supply voltage Vdd, and the body of the N-type transistor is connected to the ground gnd). The simulation result is the worst case of the read cycle of the memory cell array (unselected memory cells and selected memory cells) Store the information instead) get it. In Fig.
  • V th V m - - ⁇ ⁇
  • the present invention connects the storage unit pull-up tubes PI, P2 and the matching tubes N3, N4 and the body ends of the shut-off tubes N5 to the gate terminals. This connection method makes: 1) When the state is on, the transistor threshold voltage is small, the turn-on current is large, and the increased turn-on current increases the driving capability of the transistor; 2) the threshold voltage and the threshold value of the conventional connector mode transistor when the state is off The voltage is the same, and the electrical properties such as the shutdown current are the same.
  • the turn-on and turn-off current ratio (Ion/Ioff) of the present invention is enhanced, which in one way weakens the influence of leakage current in the sub-threshold region circuit on circuit performance.
  • the pull-down capability of the N-type transistor in the sub-threshold region is relatively strong with respect to the P-type transistor in the sub-threshold region, only the body terminals and sources of P1, P2, N3-N5 are present in the design of the present invention. The ends are connected together, and the body ends of Nl and N2 are directly connected to the ground gnd.
  • Figure 5 shows that the potential information read by the read bit line RBL is 117.1 mV due to the increase in the turn-off current ratio.
  • the voltage loss of the read bit line RBL is reduced from 68.4% to 41.45%.
  • the internal node information of the memory cell is maintained at 97.6% of the power supply voltage (logic "1"), while the normal memory cell can only maintain 85.6%.
  • the present invention designed in this manner does not require a large-sized transistor, and has a small cell density. Since the same bit line can support a larger number of memory cells, the memory cell array of the present invention can obtain a larger capacity and obtain an overall density. Performance improvement.
  • the invention satisfactorily solves the limitation of the storage unit on each bit line caused by reading the "1" operation while satisfying the balance of the read/write capability of the storage unit. Another advantage of using this connection method is that it is less affected by the process variation, so that it is possible to obtain better process tolerance tolerance without increasing the specific size of the memory cell transistor, that is, only the minimum size design is required.
  • the logical unit array of the invention can achieve good yields.

Description

一种高密度、 高鲁棒性的亚阈值存储单元电路 技术领域
本发明涉及亚阈值工作区域下的存储单元， 尤其是一种高密度， 高鲁棒 性的亚阈值存储单元电路。它可以工作在 200mV的电源电压下，兼具高密度， 高鲁棒性， 超低功耗等特点。 背景技术
存储单元阵列是现代数字系统的重要组成部分， 也往往是系统设计的功 耗瓶颈。 市场对各种便携式设备需求的不断提高对存储单元阵列的降低功耗 技术提出了更高的要求。 亚阈值设计是当前超低功耗设计的热门。 通过降低 电源电压 （Vdd)进入电路的亚阈值区域—— Vdd小于阈值电压 （Vth)， 使得 系统工作在电路的线性区， 进而显著降低系统的动态、 静态功耗。 亚阈值存 储单元阵列的设计更是凸显了亚阈值设计的低功耗优越性。 但是在具体的实 现过程中该设计也引入了一系列问题： 1 ) 静态噪声容限 （static noise margin (SNM) ) 急剧恶化； 2) 写能力变弱； 3 ) 对工艺偏差的容忍度变差等。 为了解 决这些问题， 人们也提出了一些能够工作在 200〜300mV之间的亚阈值存储单 元。 但是， 这些设计都是以牺牲存储单元的密度为代价的。
在常规状态下， 与保持噪声容限和写噪声容限相比， 读噪声容限最小。 所以它是存储单元设计的关键设计指标。 有人可在传统 6 管存储单元的设计 基础上增加了 2个 NMOS管， 使得内部信息在读出的过程中不会干扰内部节 点的信息。 这样， 该亚阈值存储单元的读噪声容限就等于该单元的保持噪声 容限。但是， 与传统的 6管存储单元相比， 这种结构的存储单元要多消耗 30% 的面积。 另有人提出了一款单端的 6 管亚阈值存储单元。 虽然单端结构使得 该存储单元在读操作过程的鲁棒性较强， 但是这种结构的写能力较弱， 在写 过程中需要写辅助单元的协助。 而且为了解决亚阈值电路特性易受工艺偏差 影响等问题， 该设计普遍采用了较大尺寸的晶体管。 这样， 该设计的得密度 也会受到一定的影响。
采用亚阈值设计技术可以成平方项关系降低系统功耗， 亚阈值存储电路 的设计已经证实了存储单元的动态功耗、 静态功耗可以随着电源电压的下降 成平方项减少。 考虑到存储单元阵列的容量， 这一减少的功耗将非常可观。 但是处于亚阈值区域的电路有着它本身特有的电路特性。 常规设计中 （超阈 值状态下） 由调整存储单元各晶体管尺寸大小以达到存储单元读能力、 写能 力以及芯片面积消耗的平衡状态 （trade-off) 的方法已经完全不能适应亚阈值 电路设计的需求。 因此， 高密度， 高鲁棒的亚阈值存储单元设计是亚阈值电 路设计真正能够走向产业化的瓶颈。 发明内容
本发明的目的是克服现有技术之缺陷， 提供一种高密度、 高鲁棒性的亚 阈值存储单元电路， 为了平衡存储单元的各项指标， 达到系统性能最优。 本 发明针对亚阈值电路的实际特点设计了一种双端写， 单端读的高密度， 高鲁 棒性存储单元。 它能够在保证系统的超低功耗同时， 达到写噪声容限、 读噪 声容限、 保持噪声容限的兼优。 同时高密度的设计使得该存储单元阵列消耗 的芯片面积是目前已知芯片中最小的。 这使得亚阈值存储单元走向产业化， 商品化成为可能。
为实现以上目的， 本发明采用的技术方案如下：
一种高密度、 高鲁棒性的亚阈值存储单元电路， 其特征在于： 设有包括 两个 PMOS管 P1及 P2， 五个 NMOS管 Nl、 N2、 N3、 N4及 N5， 共七个 晶体管构成双端写， 单端读的高密度， 高鲁棒性亚阈值存储单元电路； 其中， 两个 PMOS管及 NMOS管 N3、 N4、 N5的各体端均与本晶体管的栅端连接， NMOS管 Nl、 N2的体端及源端接地，两个 PMOS管的源端连接到电源电压， NMOS管 N1的漏端和栅端分别与 PMOS管 P1的漏端和栅端连接在一起， 组 成一个反相器； NMOS管 N2的漏端和栅端分别与 PMOS管 P2的漏端和栅端 连接在一起， 组成另一个反相器； NMOS管 N1漏端及 PMOS管 P1漏端与 NMOS管 N2栅端及 PMOS管 P2栅端连接在一起， NMOS管 N1栅端和 PMOS 管 P1栅端之间的连接端与 NMOS管 N2漏端和 PMOS管 P2漏端之间的连接 端分别连接在 NMOS管 N5源、漏两端之任一端， NMOS管 N5的栅端与外部 控制信号读字线的取反信号连接， NMOS管 N1漏端和 PMOS管 P1漏端之间 的连接端与写位线分别连接在 NMOS管 N3源、 漏两端之任一端， NMOS管 N3的栅端连写字线， NMOS管 N2漏端和 PMOS管 P2漏端之间的连接端与 写位线的非和读位线的共享位线分别连接在 NMOS管 N4源、 漏两端之任一 端， NMOS管 N4栅端连接到写字线和读字线共享的字线上。
上述电路中， NMOS管 N3、 N4起匹配管作用， NMOS管 N5起关断管作 用。 由于本发明电路是为在亚于存储单元工作设计的， 电路的工作状态决定 了 N3、 N4、 N5三个晶体管的源端与漏端之间是可以互相动态转化的， 可随 着与此源、漏两端分别对应连接的两连接端的电位变化而自动转换。因此 N3、 N4及 N5的源端与漏端可与其对应的连接端任意相连。
与现有技术相比， 本发明具有以下优点及显著效果：
( 1 ) 在目前已知的亚阈值存储单元中单位面积消耗最小。 7 个晶体管的 电路结构简单可靠。 本发明受工艺偏差的影响较小， 每个晶体管均为最小尺 寸设计， 没有比例设计要求。
(2) Pl、 P2、 N3〜N5晶体管的体端均连接到相应晶体管的栅端。 Nl、 N2的体端连接到常规的地的连接方式使得本发明在保证上拉、 下拉驱动能力 平衡的同时增加存储单元匹配管的开启关断电流。这样就带来了两个好处： a) 上拉、 下拉驱动能力的平衡保证了存储单元的鲁棒性。 b) 本发明的开启关断 电流在目前已知设计的亚阈值存储单元的开启关断电流中最大。 这样， 未选 中存储单元累积的漏电流的影响相应变弱。 本发明可以在同一位线上支持更 多的存储单元。 这在另一方面解决了亚阈值存储单元阵列普遍存在的同一位 线上串联存储单元较少的问题。 提高了亚阈值存储单元阵列的容量和密度。
(3 ) 从单端读字线 RWL进行读取操作， 从写位线 （WBL) 和写位线的 非 （ ) 同时写的操作方式， 使得该发明能够在获得较大的读噪声容限的 同时不会损耗存储单元的写能力。 无需外加写辅助单元或者敏感放大器亦可 以正常工作。 关断管 N5的引入巧妙利用了亚阈值区域内 P型晶体管， N型晶 体管在 |Vgs|>0时能传送完整的数据信号， 而在 |Vgs|=0传送数据信号有损失的 特性， 在读周期关断 |Vgs|=0， 避免外部信息对内部节点的干扰； 在写和保持 周期开启 |Vgs|>0， 增加写能力和保持能力。 附图说明
图 1 是本发明高密度， 高鲁棒性的亚阈值存储单元电路结构图； 图 2 是一列亚阈值存储阵列的逻辑框图及最差情况下位线漏电流的影响 示意图；
图 3 是常规亚阈值存储单元在同一位线上串联 64个存储单元时， 读 " 1 " 时的位线输出波形图；
图 4是常规亚阈值存储单元在同一位线上串联 64个存储单元时， 读 "0" 时的位线输出波形图；
图 5 是本发明与常规亚阈值存储单元同等条件下读 " 1 " 操作时的位线 输出波形图比较。 具体实施方式：
参看图 1， 本发明的高密度、 高鲁棒性的亚阈值存储单元电路由 7个晶体 管组成，两个 P型晶体管（PI, P2)和五个 N型晶体管（N1〜N5 )。其中 PI, P2, N3〜N5晶体管的体端均连接到相应晶体管的栅端。 Nl, N2的体端连接到常规 的地 gnd。 Nl， PI禾卩 N2， P2分别组成了两个反相器 （INV1, INV2)， 中间由 关断管 N5连接成交叉耦合的方式： 由 Nl， PI组成的 INV1的输出端直接连 接到由 N2， P2组成的 INV2的输入端； 而 INV2的输出端经由关断管 N5连 接到 INV1的输入端。 N5的栅端连接外部控制信号读字线 （RWL) 的取反信 号 E。 N3， N4为匹配管： 通过 N3连接 INV1与写位线 （WBL)， N3的栅 端连接写字线 （WWL); 通过 N4连接 INV2与写位线的非和读位线共享的位 线（^I+RBL)， N4的栅端连接写字线和读字线的共享字线（WWL+RWL)。
在本发明实际的操作过程中， 读操作是通过读字线 RWL信号有效控制开 启晶体管 N4， 关断切断管 N5， 将存储单元的内部信号传送到读位线 （RBL) 上， 仅由单端读位线上逻辑信号识别存储单元的内部信息， 完成单端读的操 作过程。 写操作时通过 WWL信号控制， 此时读字线 RWL信号无效， 匹配晶 体管 N3、N4，切断管 N5均处于开启状态。写字线（WBL)和写位线的非（ ϋ ) 上的信号将通过匹配晶体管 Ν3、 Ν4传送到内部节点， 改变存储单元内部的信 息， 完成双端写的操作过程。
由于 Ρ型晶体管的驱动性能明显不如 Ν型晶体管， 本发明将存储单元上 拉管 PI, Ρ2和匹配管 Ν3, Ν4以及关断管 Ν5的体端均连接到栅端， 而 Nl, Ν2 的体端还是直接接在地 gnd上。 本发明采用这种方法在满足存储单元读写能 力平衡的同时妥善的解决了读 " 1 "操作中所引起的每条位线上存储单元的限 制。 采用此连接方法的另一个好处是， 本发明受工艺偏差的影响较小， 使得 无需增大存储单元晶体管的具体尺寸， 就可以得到较好的工艺偏差容忍性， 亦即本发明只采用最小尺寸晶体管设计， 由本发明组成的逻辑单元阵列就能 就能达到很好的良率。
本发明的高密度、 高鲁棒性的亚阈值存储单元电路的工作原理如下： A， 读操作
对于常规的存储单元， 假定存储单元存储的逻辑值为 0时， 即 Q为 " 0"， NQ为 " 1 "。 预充周期结束后， 在读 "0" 的操作中， 电压值 Q会随着预充到 电源电压 （Vdd) 的位线增加。 一旦该值大于反相器的翻转电压 （Vtrip) , 存 储单元就会经历一个错误的写 " 1 "过程。这在存储单元设计中被称做写破坏。 对于本发明， 预充电后， RWL置 1后， Q会拉高到 RBL的预充电值。 因为关 断管 N5在本发明的读过程中关断， Q1的电压值不会随着 Q值的变化明显变 化。 这样外部信息对存储单元内部节点的信号干扰即被避免。 亚阈值存储单 元读噪声容限较小的问题也被解决。
B， 写操作
较大的写噪声容限和保持噪声容限在亚阈值 SRAM设计中同样很重要。 在实际的写操作过程中， 读位线（RBL)置为 0， 关断管（N5 )开启 (|Vgs|>0)。 因为在亚阈值区域内晶体管开启时， 可以无损耗的传递数据信息， 所以 Q1节 点可以跟随 Q节点的变化而变化。 与此同时,双端写的组织结构和两个反相器 (INV1， INV2) 交叉耦合的连接方式的正反馈保证了本发明的写和保持噪声 容限。
C， 提升存储单元密度
开启关断电流比 （Ion/Ioff)是存储单元阵列设计的重要指标之一。 正常的 设计中 （超阈值状态下） 开启、 关断电流比 （Ion/Ioff) 大致为 107， 而在亚阈 值设计中该值仅为 103-104。 如果没有留有足够的冗余度 （位线上串联存储单 元数大于一定限度）， 被选中单元的开启电流可能会被累积的未被选中存储单 元的漏电流干扰， 以致后续电路无法识别正确的逻辑， 造成存储单元的读写 失效 （图 2)。 考虑到工艺偏差及后续敏感放大器的偏置电压， 单个位线上存 储单元数会被进一步限制。 目前的亚阈值区域的存储单元阵列设计倾向于两 种设计方式： 1 ) 仔细计算各种工艺角内晶体管开启电流和关断电流的比例关 系， 严格控制同一位线上串联的存储单元的数目 [1,2]; 2) 在存储单元内部加 上漏电流补偿逻辑 [3,4]。但是存储单元阵列是大容量逻辑部件，对设计密度有 着较高的要求， 上面两种方法都不能有效的解决存储单元阵列芯片面积消耗 过大的问题。
事实上 P型晶体管的驱动性能明显不如 N型晶体管 (P型晶体管漏电流的 最小值大约是 N型晶体管的 22% under |VdsHVgs|=200mV， 0.13um工艺)。 图 3和图 4是在每条位线上串联 64个存储单元下读 " 1 "和读 "0" 的仿真结 果。所有的晶体管都是最小晶体管宽度且均为常规的连接方式（P型晶体管的 体连接到电源电压 Vdd， N型晶体管的体连接到地 gnd)。 该仿真结果是在存 储单元阵列的读周期的最差情况 （未被选中的存储单元与被选中存储单元的 存储信息相反）得到的。在图 3中， 当读 " 1 "操作时，存储单元的读位线 RBL 被拉低到 63.19 mV, 引起了存储单元阵列的读错误。 存储单元内部的节点信 息也受到影响。 相比下， 当进行读 " 0"操作时， 读位线 RBL被拉到一个非常 低的值（12.99mV) , 存储单元内部的节点信息受干扰较小 （如图 4)。 所以在 亚阈值区域， 位线上未选中存储单元累积的漏电流导致的读 " 1 " 时产生错误 的几率高于读 "0" 时产生的。 亦即， 位线上能够串联的存储单元的数目受读
" 1 "操作时开启电流和关断电流的影响。
根据阈值电压赋值公式
Vth = Vm -
Figure imgf000008_0001
- ηνεο
其中 Vth0 是当 ί^ = 0时的阈值电压， γ是体效应参数. 1φρ 是硅表面势, VBS是源端到体端得电势差。本发明将存储单元上拉管 PI, P2和匹配管 N3, N4 以及关断管 N5 的体端均连接到栅端。 这种连接方式使得： 1 ) 开启状态时， 晶体管阈值电压较小， 开启电流大， 增加的开启电流提高了晶体管的驱动能 力； 2) 关断状态时， 阈值电压与常规连接体方式晶体管的阈值电压相同， 关 断电流等电气性能均相同。 在这种设计模式下， 本发明的开启、 关断电流比 (Ion/Ioff) 增强， 从一个方面削弱了处于亚阈值区域电路的漏电流对电路性 能的影响。 但是需要注意的是， 由于亚阈值区域内 N型晶体管下拉能力相对 与亚阈值区域内 P型晶体管上拉能力强， 所以在本发明的设计中只有 P1, P2， N3-N5的体端和源端连接在一起， Nl, N2的体端还是直接接在地 gnd上。
图 5 表明由于开启关断电流比的提高， 读位线 RBL 读出的电位信息为 117.1mV。 读位线 RBL的电压损耗从 68.4%减少到 41.45% 。 在读 " 1 "操作 中， 存储单元内部节点信息保持为电源电压的 97.6% (逻辑 "1"), 而通常的存 储单元只可以保持 85.6% 。
采用这种方式设计的本发明无需大尺寸晶体管， 单元密度较小， 由于同 一位线能够支撑较多的存储单元， 所以采用本发明的存储单元阵列可以获得 较大的容量以及在整体密度上获得性能的提升。
本发明在满足存储单元读写能力平衡的同时妥善的解决了读 " 1 "操作中 所引起的每条位线上存储单元的限制。 采用此连接方式的另一个好处是， 受 工艺偏差的影响较小， 使得无需增大存储单元晶体管的具体尺寸， 就可以得 到较好的工艺偏差容忍性， 亦即仅需采用最小尺寸设计， 由本发明组成的逻 辑单元阵列就能就能达到很好的良率。

Claims

利 要 求 书
1、 一种高密度、 高鲁棒性的亚阈值存储单元电路， 其特征在于： 设有包 括两个 PMOS管 P1及 P2， 五个 NMOS管 Nl、 N2、 N3、 N4及 N5， 共七 个晶体管构成双端写， 单端读的高密度， 高鲁棒性亚阈值存储单元电路； 其 中， 两个 PMOS管及 NMOS管 N3、 N4、 N5的各体端均与本晶体管的栅端 连接， NMOS管 Nl、 N2的体端及源端接地， 两个 PMOS管的源端连接到电 源电压， NMOS管 N1的漏端和栅端分别与 PMOS管 P1的漏端和栅端连接在 一起， 组成一个反相器； NMOS管 N2的漏端和栅端分别与 PMOS管 P2的漏 端和栅端连接在一起， 组成另一个反相器； NMOS管 N1漏端及 PMOS管 P1 漏端与 NMOS管 N2栅端及 PMOS管 P2栅端连接在一起， NMOS管 N1栅端 和 PMOS管 P1栅端之间的连接端与 NMOS管 N2漏端和 PMOS管 P2漏端之 间的连接端分别连接在 NMOS管 N5源、漏两端之任一端， NMOS管 N5的栅 端与外部控制信号读字线的取反信号连接， NMOS管 N1漏端和 PMOS管 P1 漏端之间的连接端与写位线分别连接在 NMOS管 N3源、 漏两端之任一端， NMOS管 N3的栅端连写字线， NMOS管 N2漏端和 PMOS管 P2漏端之间的 连接端与写位线的非和读位线的共享位线分别连接在 NMOS管 N4源、 漏两 端之任一端， NMOS管 N4栅端连接到写字线和读字线共享的字线上。
PCT/CN2009/073250 2009-08-13 2009-08-13 一种高密度、高鲁棒性的亚阈值存储单元电路 WO2011017843A1 (zh)

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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8305798B2 (en) * 2010-07-13 2012-11-06 Texas Instruments Incorporated Memory cell with equalization write assist in solid-state memory
JP5395009B2 (ja) * 2010-07-30 2014-01-22 株式会社半導体理工学研究センター サブスレッショルドｓｒａｍのための電源電圧制御回路及び制御方法
US8498143B2 (en) * 2011-03-04 2013-07-30 Texas Instruments Incorporated Solid-state memory cell with improved read stability
JP2016536822A (ja) * 2013-09-20 2016-11-24 ザ・リージェンツ・オブ・ザ・ユニバーシティ・オブ・ミシガンＴｈｅ Ｒｅｇｅｎｔｓ Ｏｆ Ｔｈｅ Ｕｎｉｖｅｒｓｉｔｙ Ｏｆ Ｍｉｃｈｉｇａｎ 自動干渉除去を有するウエイクアップ・レシーバ
US10037795B2 (en) * 2014-09-27 2018-07-31 Qualcomm Incorporated Seven-transistor static random-access memory bitcell with reduced read disturbance
KR20160096944A (ko) 2015-02-06 2016-08-17 강원대학교산학협력단 초저전력 내장형 양방향 포트 sram
US9779788B1 (en) * 2015-08-24 2017-10-03 Ambiq Micro, Inc. Sub-threshold enabled flash memory system
US11924573B2 (en) * 2016-03-15 2024-03-05 Trustees Of Dartmouth College Stacked backside-illuminated quanta image sensor with cluster-parallel readout
US9940999B2 (en) 2016-06-22 2018-04-10 Darryl G. Walker Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits
US10403384B2 (en) 2016-06-22 2019-09-03 Darryl G. Walker Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor
US11398274B2 (en) * 2020-08-25 2022-07-26 Qualcomm Incorporated Pseudo-triple-port SRAM
US11972793B2 (en) 2021-09-15 2024-04-30 Mavagail Technology, LLC Integrated circuit device including an SRAM portion having end power select circuits

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6061268A (en) * 1999-10-27 2000-05-09 Kuo; James B. 0.7V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique
US6285578B1 (en) * 1999-10-06 2001-09-04 Industrial Technology Research Institute Hidden refresh pseudo SRAM and hidden refresh method
CN1402353A (zh) * 2001-08-10 2003-03-12 三菱电机株式会社 半导体存储器
CN1992280A (zh) * 2005-12-30 2007-07-04 中国科学院半导体研究所 形成于pd soi 衬底上的静态随机存储器及其制作方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4725981A (en) * 1986-02-03 1988-02-16 Motorola, Inc. Random access memory cell resistant to inadvertant change of state due to charged particles
US5631863A (en) * 1995-02-14 1997-05-20 Honeywell Inc. Random access memory cell resistant to radiation induced upsets
JP3552068B2 (ja) * 1995-03-15 2004-08-11 株式会社ルネサステクノロジ Ｃｍｏｓ論理回路
JP3609868B2 (ja) * 1995-05-30 2005-01-12 株式会社ルネサステクノロジ スタティック型半導体記憶装置
US6058041A (en) * 1998-12-23 2000-05-02 Honeywell Inc. SEU hardening circuit
JP4038351B2 (ja) * 2001-05-29 2008-01-23 株式会社東芝 半導体記憶装置
US6775178B2 (en) * 2002-04-04 2004-08-10 Honeywell International Inc. SEU resistant SRAM using feedback MOSFET
KR100539229B1 (ko) * 2003-01-30 2005-12-27 삼성전자주식회사 듀얼 포트 반도체 메모리 장치
US7233518B2 (en) * 2005-02-04 2007-06-19 Honeywell International Inc. Radiation-hardened SRAM cell with write error protection
US7200031B2 (en) * 2005-03-16 2007-04-03 Honeywell International, Inc. Proton and heavy ion SEU resistant SRAM
JP4855786B2 (ja) * 2006-01-25 2012-01-18 株式会社東芝 半導体装置
US20070279964A1 (en) * 2006-05-25 2007-12-06 Honeywell International Inc. SRAM split write control for a delay element
FR2927722A1 (fr) * 2008-02-18 2009-08-21 Commissariat Energie Atomique Cellule memoire sram a transistor double grille dotee de moyens pour ameliorer la marge en ecriture

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6285578B1 (en) * 1999-10-06 2001-09-04 Industrial Technology Research Institute Hidden refresh pseudo SRAM and hidden refresh method
US6061268A (en) * 1999-10-27 2000-05-09 Kuo; James B. 0.7V two-port 6T SRAM memory cell structure with single-bit-line simultaneous read-and-write access (SBLSRWA) capability using partially-depleted SOI CMOS dynamic-threshold technique
CN1402353A (zh) * 2001-08-10 2003-03-12 三菱电机株式会社 半导体存储器
CN1992280A (zh) * 2005-12-30 2007-07-04 中国科学院半导体研究所 形成于pd soi 衬底上的静态随机存储器及其制作方法

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